Patents Assigned to MICROUNITY SYSTEMS
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Patent number: 7660973Abstract: Systems and apparatuses are presented relating a programmable processor comprising an execution unit that is operable to decode and execute instructions received from an instruction path and partition data stored in registers in the register file into multiple data elements, the execution unit capable of executing a plurality of different group floating-point and group integer arithmetic operations that each arithmetically operates on multiple data elements stored registers in a register file to produce a catenated result that is returned to a register in the register file, wherein the catenated result comprises a plurality of individual results, wherein the execution unit is capable of executing group data handling operations that re-arrange data elements in different ways in response to data handling instructions.Type: GrantFiled: July 27, 2007Date of Patent: February 9, 2010Assignee: Microunity Systems Engineering, Inc.Inventors: Craig Hansen, John Moussouris, Alexia Massalin
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Patent number: 7653806Abstract: Systems and apparatuses are presented relating a programmable processor comprising an execution unit that is operable to decode and execute instructions received from an instruction path and partition data stored in registers in the register file into multiple data elements, the execution unit capable of executing a plurality of different group floating-point and group integer arithmetic operations that each arithmetically operates on multiple data elements stored registers in a register file to produce a catenated result that is returned to a register in the register file, wherein the catenated result comprises a plurality of individual results, wherein the execution unit is capable of executing group data handling operations that re-arrange data elements in different ways in response to data handling instructions.Type: GrantFiled: October 29, 2007Date of Patent: January 26, 2010Assignee: Microunity Systems Engineering, Inc.Inventors: Craig Hansen, John Moussouris
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Patent number: 7565515Abstract: A system and software for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions specifying both a mask and a register containing data, the mask comprising fields that each correspond to a field of the data contained in the register, the execution unit is operable to detect some of the fields of the mask as having a predetermined value and identifying corresponding fields of the data contained in the register as write-enabled data fields; and cause the write-enabled data fields to be written to a specified memory location.Type: GrantFiled: January 16, 2004Date of Patent: July 21, 2009Assignee: Microunity Systems Engineering, Inc.Inventors: Craig Hansen, John Moussouris
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Publication number: 20090158012Abstract: Systems and apparatuses are presented relating a programmable processor comprising an execution unit that is operable to decode and execute instructions received from an instruction path and partition data stored in registers in the register file into multiple data elements, the execution unit capable of executing a plurality of different group floating-point and group integer arithmetic operations that each arithmetically operates on multiple data elements stored registers in a register file to produce a catenated result that is returned to a register in the register file, wherein the catenated result comprises a plurality of individual results, wherein the execution unit is capable of executing group data handling operations that re-arrange data elements in different ways in response to data handling instructions.Type: ApplicationFiled: October 29, 2007Publication date: June 18, 2009Applicant: MicroUnity Systems Engineering, Inc.Inventors: Craig Hansen, John Moussouris
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Publication number: 20090113187Abstract: A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.Type: ApplicationFiled: October 31, 2007Publication date: April 30, 2009Applicant: MicroUnity Systems Engineering, Inc.Inventors: Craig Hansen, John Moussouris, Alexia Massalin
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Publication number: 20090113185Abstract: A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.Type: ApplicationFiled: October 31, 2007Publication date: April 30, 2009Applicant: MicroUnity Systems Engineering, Inc.Inventors: Craig Hansen, John Moussouris, Alexia Massalin
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Publication number: 20090113176Abstract: A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.Type: ApplicationFiled: October 31, 2007Publication date: April 30, 2009Applicant: MicroUnity Systems Engineering, Inc.Inventors: Craig Hansen, John Moussouris, Alexia Massalin
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Publication number: 20090106536Abstract: A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.Type: ApplicationFiled: October 31, 2007Publication date: April 23, 2009Applicant: MicroUnity Systems Engineering, Inc.Inventors: Craig Hansen, John Moussouris, Alexia Massalin
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Publication number: 20090100227Abstract: A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.Type: ApplicationFiled: October 31, 2007Publication date: April 16, 2009Applicant: MicroUnity Systems Engineering, Inc.Inventors: Craig Hansen, John Moussouris, Alexia Massalin
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Publication number: 20090094309Abstract: The present invention provides a system and method for improving the performance of general-purpose processors by implementing a functional unit that computes the product of a matrix operand with a vector operand, producing a vector result. The functional unit fully utilizes the entire resources of a 128b by 128b multiplier regardless of the operand size, as the number of elements of the matrix and vector operands increase as operand size is reduced. The unit performs both fixed-point and floating-point multiplications and additions with the highest-possible intermediate accuracy with modest resources.Type: ApplicationFiled: December 9, 2008Publication date: April 9, 2009Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.Inventors: Craig HANSEN, Bruce Bateman, John Moussouris
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Patent number: 7516308Abstract: A system and method expands a source operand to a width greater than that of a general purpose register or a data path. Operands are provided substantially larger than the data path width of a processor. The general purpose register specifies a memory address from which several data path widths of data are read. A data path functional unit is augmented with dedicated storage to which the memory operand is copied on initial execution of the instruction. Further instructions specifying the same memory address read the dedicated storage to obtain the operand value, upon verification that the memory operand has not been altered by intervening instructions. If the memory operand remains current, the memory operand fetch is combined with register operands in the functional unit, producing a result the size of a general register, so no dedicated storage is required for the result.Type: GrantFiled: May 13, 2003Date of Patent: April 7, 2009Assignee: Microunity Systems Engineering, Inc.Inventors: Craig Hansen, John Moussouris
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Publication number: 20090089540Abstract: A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.Type: ApplicationFiled: October 31, 2007Publication date: April 2, 2009Applicant: MicroUnity Systems Engineering, Inc.Inventors: Craig Hansen, John Moussouris, Alexia Massalin
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Patent number: 7509366Abstract: A multiplier array processing system which improves the utilization of the multiplier and adder array for lower-precision arithmetic is described. New instructions are defined which provide for the deployment of additional multiply and add operations as a result of a single instruction, and for the deployment of greater multiply and add operands as the symbol size is decreased.Type: GrantFiled: April 18, 2003Date of Patent: March 24, 2009Assignee: Microunity Systems Engineering, Inc.Inventor: Craig C. Hansen
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Publication number: 20090031105Abstract: A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.Type: ApplicationFiled: October 31, 2007Publication date: January 29, 2009Applicant: MicroUnity Systems Engineering, Inc.Inventors: Craig Hansen, John Moussouris, Alexia Massalin
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Patent number: 7483935Abstract: The present invention provides a system and method for improving the performance of general-purpose processors by implementing a functional unit that computes the product of a matrix operand with a vector operand, producing a vector result. The functional unit fully utilizes the entire resources of a 128b by 128b multiplier regardless of the operand size, as the number of elements of the matrix and vector operands increase as operand size is reduced. The unit performs both fixed-point and floating-point multiplications and additions with the highest-possible intermediate accuracy with modest resources.Type: GrantFiled: September 4, 2002Date of Patent: January 27, 2009Assignee: Microunity Systems Engineering, Inc.Inventors: Craig Hansen, Bruce Bateman, John Moussouris
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Patent number: 7464252Abstract: A programmable processor and system for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions specifying three registers each containing a plurality of data elements, the execution unit operable to multiply the first and second registers and add the third register to produce a catenated result containing a plurality of data elements. Additional instructions provide group floating-point subtract, add, multiply, set less, and set greater equal operations. The set less and set greater equal operations produce alternatively zero or an identity element for each element of a catenated result, the result facilitating alternative selection of individual data elements using bitwise Boolean operations and without requiring conditional branch operations.Type: GrantFiled: January 16, 2004Date of Patent: December 9, 2008Assignee: Microunity Systems Engineering, Inc.Inventors: Craig Hansen, John Moussouris
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Patent number: 7430655Abstract: A system and software for improving the performance of processors by incorporating an execution unit configurable to execute a plurality of instruction streams from the plurality of threads, wherein each instruction stream includes a group instruction that operates on a plurality of data elements in partitioned fields of at least one of the registers to produce a catenated result.Type: GrantFiled: January 15, 2004Date of Patent: September 30, 2008Assignee: Microunity Systems Engineering, Inc.Inventors: Craig Hansen, John Moussouris
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Publication number: 20080189512Abstract: A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.Type: ApplicationFiled: October 31, 2007Publication date: August 7, 2008Applicant: MicroUnity Systems Engineering, Inc.Inventors: Craig Hansen, John Moussouris, Alexia Massalin
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Publication number: 20080177986Abstract: Methods and software are presented for processing data in a programmable processor, involving (a) decoding instructions for execution using an execution unit operable to execute instructions by partitioning data stored in registers in a register file into multiple data elements, the instructions selected from an instruction set that includes group arithmetic instructions and group data handling instructions, (b) in response to decoding different group arithmetic instructions, executing a plurality of different group floating-point and group integer arithmetic operations that each arithmetically operates on multiple data elements stored in registers in the register file to produce a catenated result that is returned to a register in the register file, wherein the catenated result comprises a plurality of individual results, and (c) in response to decoding different group data handling instructions, executing group data handling operations that re-arrange data elements in different ways.Type: ApplicationFiled: July 27, 2007Publication date: July 24, 2008Applicant: MICROUNITY SYSTEMSInventors: Craig Hansen, John Moussouris, Alexia Massalin
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Publication number: 20080162882Abstract: Systems and apparatuses are presented relating a programmable processor comprising an execution unit that is operable to decode and execute instructions received from an instruction path and partition data stored in registers in the register file into multiple data elements, the execution unit capable of executing a plurality of different group floating-point and group integer arithmetic operations that each arithmetically operates on multiple data elements stored registers in a register file to produce a catenated result that is returned to a register in the register file, wherein the catenated result comprises a plurality of individual results, wherein the execution unit is capable of executing group data handling operations that re-arrange data elements in different ways in response to data handling instructions.Type: ApplicationFiled: July 27, 2007Publication date: July 3, 2008Applicant: MICROUNITY SYSTEMSInventors: Craig Hansen, John Moussouris, Alexia Massalin