Abstract: A controller for a synchronous DRAM is provided for maximizing throughput of memory requests to the synchronous DRAM. The controller maintains the spacing between the commands to conform with the specifications for the synchronous DRAMs while preventing gaps from occurring in the data slots to the synchronous DRAM. Furthermore, the controller allows memory requests and commands to be issued out of order so that the throughput may be maximized by overlapping required operations which do not specifically involve data transfer. To achieve this maximized throughput, memory requests are tagged for indicating a sending order. Thereafter, the memory requests may be arbitrated when conflicting memory requests are queued and this arbitration process is then decoded for simultaneously updating scheduling constraints. The memory requests may be further qualified based on the scheduling constraints and a command stack of memory request is then developed for modifying update queues.

Abstract: A robust family of pre-conditioned complementary CMOS logic elements using scaled MOSFETs and a single clock phase which may be easily interconnected to form high speed logic networks. The family includes both N-type and P-type pre-conditioned logic elements using a skewed complementary CMOS structure to achieve low power and high speed. The logic elements achieve next generation CMOS performance yet are manufactured using present day processes and equipment. Logic element implementation is described in detail. A method for scaling the MOSFETs according to the present invention is provided, and several routing methods for reducing interconnection cross-talk are set forth.

Abstract: A direct digital synthesizer (DDS) for generating a waveform generates a sequence of n-bit phase signals representing phase of the waveform, wherein n is an integer greater than zero. Each n-bit phase signal comprises a phase estimate signal and a phase error signal. The phase estimate signal comprises a most-significant m bits of the n-bit quantity (0 <m<n). The phase-error signal comprises a least-significant n-m bits of the n-bit quantity. The DDS further has a sigma-delta modulator for generating a compensation signal from the phase error signals. The phase estimate signal is added to the compensation signal to produce a compensated phase signal, which may be used to address a look-up table having waveform samples stored in correspondence with look-up table addresses. A digital to analog converter may be coupled to receive waveform samples from the look-up table in order to generate a corresponding analog waveform signal.

Abstract: An apparatus and method for decorrelating pairs of mutually contaminated channels in a multi-channel digital signal including two identical data processing paths and a feedback path. Each pair of mutually contaminated channels consists of a first contaminated channel and a second contaminated channel. Initially, first and second shined signals are generated by shifting the original contaminated signal such that the first shined signal has the first contaminated channel centered at zero frequency and the second shined signal has the second contaminated channel centered at zero frequency. Each of the first and second shifted signals are coupled to one of the two identical signal processing paths. The first path generates an error corruption component corresponding to the first shifted input signal and subtracts this corruption component from the second shifted signal in order to generate a third decorrelated digital signal.

Abstract: A circuit for isolating an interconnect line from unwanted input signal voltage levels is described. One implementation of the circuit includes a transmission gate coupled in series between an input signal and an interconnect line having its gate coupled to the output of an inverter and the input of the inverter coupled to the input signal. The inverter senses the input signal and when it sense voltages that are either too high or low, the isolation circuit decouples the input signal from the interconnect line such that the input signal can transition independently with respect to the voltage levels on the interconnect line.

Abstract: An output buffer that controls the slew rate of its output signal is disclosed. The buffer includes a pull-up and a pull-down bipolar transistor coupled at a common output node in series between VDD and VSS. The buffer also includes a first set of parallel MOS devices coupled between the common output node and the base of the pull-down bipolar transistor. A second set of parallel MOS devices are coupled between the base of the pull-up output stage bipolar transistor and VDD. The gates of each set of MOS devices are coupled to a digital select signal. The amount of current driving the base of each of the pull-up and pull-down transistors (when they are enabled) is determined by the number of MOS devices enabled by the digital select signal. Thus, the buffer of the present invention is able to adjust the slew rate of its output signal to accommodate different loads coupled to the common output node.

Abstract: A bias generation and distribution system in which bias potentials are generated at one main location within a logic circuit and then distributed throughout the logic circuit to MOS load devices, MOS load networks, other bias voltage conversion centers, and logic circuits is disclosed. The system generates a first bias voltage that provides a temperature compensated voltage that is utilized to bias MOS load devices and parallel MOS load networks. The first bias voltage generator includes either a reference MOS load device or a reference parallel MOS load network which determines the value of the first bias voltage. The reference MOS load network includes a switching network responsive to a first set of control signals. The first set of control signals may be adjusted to vary the value of the first bias voltage to compensate for process variations. The first bias voltage is distributed to either remote single load MOS devices or to remote parallel MOS load networks.

Abstract: A compact Finite Impulse Response (FIR) filter using one or both of a compact address sequencer and a compact multiplier/accumulator. The address sequencer exploits certain symmetry properties existing between different phases of a polyphase FIR filter in order to reduce coefficient storage and simplify address sequencing. The multiplier/accumulator is capable of performing two multiply/accumulate operations per clock cycle, avoiding in certain instances the need to add a second multiplier/accumulator. The area required to realize a FIR filter for performing real-time filter is therefore reduced.

Abstract: In a lithographical tool utilizing off-axis illumination, masks to provide increased depth of focus and minimize CD differences between certain features is disclosed. A first mask for reducing proximity effects between isolated and densely packed features and increasing depth of focus (DOF) of isolated features is disclosed. The first mask comprises additional lines, referred to as scattering bars, disposed next to isolated edges. The bars are spaced a distance from isolated edges such that isolated and densely packed edge gradients substantially match so that proximity effects become negligible. The width of the bars set so that a maximum DOF range for the isolated feature is achieved. A second mask that is effective with quadrapole illumination only, is also disclosed. This mask "boosts" intensity levels and consequently DOF ranges for smaller square contacts so that they approximate intensity levels and DOF ranges of larger elongated contacts.

Abstract: A current mode access BiCMOS memory cell is disclosed. The memory cell includes a CMOS storage cell for storing first and second CMOS voltage potentials, VDD and VSS, corresponding to first and second logic levels. The storage cell includes two CMOS inverters coupled between VDD and VSS. The storage cell is coupled to a conversion circuit. The conversion circuit is coupled between third and fourth ECL working potentials. It functions to convert the first and second CMOS voltage potentials into the third and fourth working potentials. The third and fourth voltage potentials are coupled to the bases of two bipolar signal converters. The emitters of the bipolar signal converters are coupled to a selectable current source and the collectors of the bipolar signal converters are coupled to complementary bit lines. The selectable current source is responsive to a read word signal.

Abstract: A two-stage flash analog-to-digital signal converter has a first stage voltage divider network and a set of amplifiers that perform an initial interpolation. The initial interpolation results are directly coupled, i.e. no resistive or capacitive elements, to a second stage comprising a set of comparators having multiple inputs. The multiple inputs of the second stage comparators are weightily coupled to the first stage amplifiers in a manner so as to cause the second stage comparators to generate a digital representation of the analog signal.

Abstract: A large burst mode memory accessing system includes N discrete sub-memories and three main I/O ports. Data is stored in the sub-memories so that the sub-memories are accessed depending on their proximity to the main I/O ports. Three parallel pipelines provide a data path to/from the main I/O ports and the sub-memories. The first pipeline functions to couple address/control signals to the memories such that adjacent sub-memories are accessed in half cycle intervals. The second pipeline functions to propagate accessed data from the sub-memories to the main I/O ports such that data is outputted from the main output port every successive clock cycle. The third pipeline propagates write data to the memories such that data presented at the input of the third pipeline on successive clock cycles is written into successive sub-memories. Redundancy circuits preserve data integrity without memory access interruption.

Abstract: A bipolar transistor having an emitter, a base, and a collector includes an intrinsic base region having narrow side areas and a wider central area. The side areas are located adjacent to the extrinsic base region, while the central area is disposed underneath the emitter. The lateral doping profile of the base is tailored so that the doping concentrations in the extrinsic region and the central area are relatively high compared to the doping concentration of the narrow side areas of the intrinsic base. The combination of the narrow side areas and the lateral base doping profile constrains the depletion region within the base thereby lowering punch-through voltage of the transistor without loss of beta.

Abstract: A method of printing a sub-resolution device feature having first and second edges spaced in close proximity to one another on a semiconductor substrate includes the steps of first depositing a radiation-sensitive material on the substrate, then providing a first mask image segment which corresponds to the first edge. The first mask image segment is then exposed with radiation using an imaging tool to produce a first pattern edge gradient. The first pattern edge gradient defines the first edge of the feature in the material.A second mask image segment is then provided corresponding to the second feature edge. This second mask image segment is exposed to radiation to produce a second pattern edge gradient which defines the second edge of the feature. Once the radiation-sensitive material has been developed, the two-dimensional feature is reproduced on the substrate.

Abstract: A bipolar junction transistor (BJT) which exhibits a suppressed Kirk Effect comprises a lightly-doped n-type collector region formed above a more heavily-doped n+ layer. Directly above the collector is a p-type base which has an extrinsic region disposed laterally about an intrinsic region. An n+ emitter is positioned directly above the intrinsic base region. The BJT also includes a localized n+ region disposed directly beneath the intrinsic base region which significantly increases the current handling capabilities of the transistor.

Abstract: An improved BiCMOS logic circuit utilizes an emitter-coupled pair of bipolar transistors for differentially comparing an input signal with a logic reference level. Each of the bipolar transistors are resistively loaded by a network of p-channel metal-oxide-semiconductor (PMOS) transistors coupled in parallel. At least one of the parallel combination of transistors has its gate coupled to a control signal providing a variable load resistance. The control signal is preferably provided by a feedback network which maintains a constant voltage swing across the network over temperature.

Abstract: A microscopic laminar-flow heat exchanger, well-suited for cooling a heat generating device such as a semiconductor integrated circuit, includes a plurality of thin plates, laminated together to form a block. Each plate has a microscopic recessed portion etched into one face of the plate and a pair of holes cut through the plate such that when the block is formed, the holes align to form a pair of coolant distribution manifolds. The manifolds are connected via the plurality of microscopic channels formed from the recessed portions during the lamination process. Coolant flow through these channels effectuates heat removal.

Abstract: A method of making an ultra compact laminar-flow heat exchanger includes forming microscopic regions along the front side of an elongated ribbon of material and spirally laminating the ribbon into a core wherein the front side abuts the backside of the ribbon, thereby forming enclosed microscopic channels.

Abstract: A mask for transferring square and rectangular features having critical dimensions (CDs) close to the resolution limit of the exposure tool utilized to perform the transference is described. Intensity modulation lines having the opposite transparency as the rectangular feature to be transferred, and a width significantly less than the resolution of the exposure tool, are disposed within the rectangular feature. The intensity modulation lines have the affect of damping intensity levels on the resist layer in the center of the rectangular feature. As a result, the final CD measurement of the rectangular feature is within the CD tolerance of the original designed CD measurement. In addition, since modulation lines are have dimensions well below the resolution limit of the exposure tool, they are not seen in the final rectangular resist pattern.

Abstract: An improvement for reducing proximity effects comprised of additional lines, referred to as intensity leveling bars, into the mask pattern. The leveling bars perform the function of adjusting the edge intensity gradients of isolated edges in the mask pattern, to match the edge intensity gradients of densely packed edges. Leveling bars are placed parallel to isolated edges such that intensity gradient leveling occurs on all isolated edges of the mask pattern. In addition, the leveling bars are designed to have a width significantly less than the resolution of the exposure tool. Therefore, leveling bars that are present in the mask pattern produce resist patterns that completely developed away when a nominal exposure energy is utilized during exposure of photoresist.