Patents Assigned to MICROUNITY SYSTEMS
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Publication number: 20040205096Abstract: A programmable processor and system for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions specifying three registers each containing a plurality of data elements, the execution unit operable to multiply the first and second registers and add the third register to produce a catenated result containing a plurality of data elements. Additional instructions provide group floating-point subtract, add, multiply, set less, and set greater equal operations. The set less and set greater equal operations produce alternatively zero or an identity element for each element of a catenated result, the result facilitating alternative selection of individual data elements using bitwise Boolean operations and without requiring conditional branch operations.Type: ApplicationFiled: January 16, 2004Publication date: October 14, 2004Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.Inventors: Craig Hansen, John Moussouris
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Publication number: 20040205325Abstract: A system and software for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions specifying both a mask and a register containing data, the mask comprising fields that each correspond to a field of the data contained in the register, the execution unit is operable to detect some of the fields of the mask as having a predetermined value and identifying corresponding fields of the data contained in the register as write-enabled data fields; and cause the write-enabled data fields to be written to a specified memory location.Type: ApplicationFiled: January 16, 2004Publication date: October 14, 2004Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.Inventors: Craig Hansen, John Moussouris
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Publication number: 20040205323Abstract: A programmable processor and method for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions specifying a data selection operand and a first and a second register providing a plurality of data elements, the data selection operand comprising a plurality of fields each selecting one of the plurality of data elements, the execution unit operable to provide the data element selected by each field of the data selection operand to a predetermined position in a catenated result.Type: ApplicationFiled: January 15, 2004Publication date: October 14, 2004Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.Inventors: Craig Hansen, John Moussouris
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Publication number: 20040205324Abstract: A method and software for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions specifying three registers each containing a plurality of data elements, the execution unit operable to multiply the first and second registers and add the third register to produce a catenated result containing a plurality of data elements. Additional instructions provide group floating-point subtract, add, multiply, set less, and set greater equal operations. The set less and set greater equal operations produce alternatively zero or an identity element for each element of a catenated result, the result facilitating alternative selection of individual data elements using bitwise Boolean operations and without requiring conditional branch operations.Type: ApplicationFiled: January 16, 2004Publication date: October 14, 2004Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.Inventors: Craig Hansen, John Moussouris
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Publication number: 20040156248Abstract: A programmable processor and method for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions in an instruction set comprising (a) group instructions that operate on a plurality of data elements in partitioned fields of a register to produce a catenated result, (b) aligned memory operations that move data between memory and register where the memory operand is aligned, and (c) unaligned memory operations where the memory operand is unaligned.Type: ApplicationFiled: November 20, 2003Publication date: August 12, 2004Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.Inventors: Craig Hansen, John Moussouris
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Publication number: 20040158689Abstract: A system and software for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions in an instruction set comprising (a) group instructions that operate on a plurality of data elements in partitioned fields of a register to produce a catenated result, (b) aligned memory operations that move data between memory and register where the memory operand is aligned, and (c) unaligned memory operations where the memory operand is unaligned.Type: ApplicationFiled: November 20, 2003Publication date: August 12, 2004Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.Inventors: Craig Hansen, John Moussouris
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Publication number: 20040153632Abstract: A system and software for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions specifying a data selection operand and a first and a second register providing a plurality of data elements, the data selection operand comprising a plurality of fields each selecting one of the plurality of data elements, the execution unit operable to provide the data element selected by each field of the data selection operand to a predetermined position in a catenated result.Type: ApplicationFiled: January 16, 2004Publication date: August 5, 2004Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.Inventors: Craig Hansen, John Moussouris
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Publication number: 20040103266Abstract: A programmable processor and method for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions specifying both a shift amount and a register containing a plurality of data elements, wherein the execution unit is operable to shift a subfield of each of the plurality of data elements by the shift amount to produce a second plurality of data elements; and provide the second plurality of data elements as a catenated result.Type: ApplicationFiled: November 13, 2003Publication date: May 27, 2004Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.Inventors: Craig Hansen, John Moussouris
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Publication number: 20040098567Abstract: A programmable processor and method for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions specifying both a shift amount and a register containing a plurality of data elements, wherein the execution unit is operable to shift a subfield of each of the plurality of data elements by the shift amount to produce a second plurality of data elements; and provide the second plurality of data elements as a catenated result.Type: ApplicationFiled: November 14, 2003Publication date: May 20, 2004Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.Inventors: Craig Hansen, John Moussouris
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Patent number: 6725356Abstract: The present invention provides a system and method for improving the performance of general purpose processors by expanding at least one source operand to a width greater than the width of either the general purpose register or the data path width. In addition, the present invention provides several classes of instructions which cannot be performed efficiently if the operands are limited to the width and accessible number of general purpose registers. The present invention provides operands which are substantially larger than the data path width of the processor by using a general purpose register to specify a memory address from which at least more than one, but typically several data path widths of data can be read. The present invention also provides for the efficient usage of a multiplier array that is fully used for high precision arithmetic, but is only partly used for other, lower precision operations.Type: GrantFiled: August 2, 2001Date of Patent: April 20, 2004Assignee: MicroUnity Systems Engineering, Inc.Inventors: Craig Hansen, John Moussouris
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Publication number: 20040049663Abstract: The present invention provides a system and method for expanding at least one source operand to a width greater than the width of either the general purpose register or the data path width. Operands are provided which are substantially larger than the data path width of the processor. A general purpose register is used to specify a memory address from which at least more than one, but typically several data path widths of data can be read. The data path functional unit is augmented with dedicated storage to which the memory operand is copied on an initial execution of the instruction. Further execution of the instruction or other similar instructions that specify the same memory address can read the dedicated storage to obtain the operand value. However, such reads are subject to conditions to verify that the memory operand has not been altered by intervening instructions.Type: ApplicationFiled: May 13, 2003Publication date: March 11, 2004Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.Inventors: Craig Hansen, John Moussouris
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Publication number: 20040015533Abstract: A multiplier array processing system which improves the utilization of the multiplier and adder array for lower-precision arithmetic is described. New instructions are defined which provide for the deployment of additional multiply and add operations as a result of a single instruction, and for the deployment of greater multiply and add operands as the symbol size is decreased.Type: ApplicationFiled: April 18, 2003Publication date: January 22, 2004Applicant: MicroUnity Systems Engineering, Inc.Inventors: Craig C. Hansen, Alexia Massalin
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Patent number: 6643765Abstract: A programmable processor that comprises a general purpose processor architecture, capable of operation independent of another host processor, having a virtual memory addressing unit, an instruction path and a data path; an external interface; a cache operable to retain data communicated between the external interface and the data path; at least one register file configurable to receive and store data from the data path and to communicate the stored data to the data path; and a multi-precision execution unit coupled to the data path. The multi-precision execution unit is configurable to dynamically partition data received from the data path to account for an elemental width of the data and is capable of performing group floating-point operations on multiple operands in partitioned fields of operand registers and returning catenated results. In other embodiments the multi-precision execution unit is additionally configurable to execute group integer and/or group data handling operations.Type: GrantFiled: March 24, 2000Date of Patent: November 4, 2003Assignee: Microunity Systems Engineering, Inc.Inventors: Craig Hansen, John Moussouris
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Patent number: 6584482Abstract: A multiplier array processing system which improves the utilization of the multiplier and adder array for lower-precision arithmetic is described. New instructions are defined which provide for the deployment of additional multiply and add operations as a result of a single instruction, and for the deployment of greater multiply and add operands as the symbol size is decreased.Type: GrantFiled: August 19, 1999Date of Patent: June 24, 2003Assignee: Microunity Systems Engineering, Inc.Inventors: Craig C. Hansen, Henry Massalin
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Patent number: 6427190Abstract: A virtual memory system including a local-to-global virtual address translator for translating local virtual addresses having associated task specific address spaces into global virtual addresses corresponding to an address space associated with multiple tasks, and a global virtual-to-physical address translator for translating global virtual addresses to physical addresses. Protection information is provided by each of the local virtual-to-global virtual address translator, the global virtual-to-physical address translator, the cache tag storage, or a protection information buffer depending on whether a cache hit or miss occurs during a given data or instruction access. The cache is configurable such that it can be configured into a buffer portion or a cache portion for faster cache accesses.Type: GrantFiled: May 12, 2000Date of Patent: July 30, 2002Assignee: MicroUnity Systems Engineering, Inc.Inventor: Craig C. Hansen
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Patent number: 6378060Abstract: The present invention provides a cross-bar circuit that implements a switch of a broadband processor. In an exemplary embodiment, the present invention provides a cross-bar circuit that, in response to partially-decoded instruction information and in response to datapath information, (1) allows any bit from a 2n-bit (e.g. 256-bit) input source word to be switched into any bit position of a 2m-bit (e.g. 128-bit) output destination word and (2) provides the ability to set-to-zero any bit in said 2m-bit output destination word. The cross-bar circuit includes: (1) a switch circuit which includes 2m 2n:1 multiplexor circuits, where each of the 2n:1 multiplexor circuits (a) has a unique n-bit (e.g.Type: GrantFiled: February 11, 2000Date of Patent: April 23, 2002Assignee: Microunity Systems Engineering, Inc.Inventors: Craig Hansen, Bruce Bateman, John Moussouris
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Patent number: 6295599Abstract: The present invention provides a system and method for improving the performance of general purpose processors by expanding at least one source operand to a width greater than the width of either the general purpose register or the data path width. In addition, the present invention provides several classes of instructions which cannot be performed efficiently if the operands are limited to the width and accessible number of general purpose registers. The present invention provides operands which are substantially larger than the data path width of the processor by using a general purpose register to specify a memory address from which at least more than one, but typically several data path widths of data can be read. The present invention also provides for the efficient usage of a multiplier array that is fully used for high precision arithmetic, but is only partly used for other, lower precision operations.Type: GrantFiled: August 24, 1999Date of Patent: September 25, 2001Assignee: MicroUnity Systems EngineeringInventors: Craig Hansen, John Moussouris
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Patent number: 6269136Abstract: A digital differential analyzer data synchronizer receives data at a first clock rate and synchronizes the data to a second clock rate. The two clock rates are related by a ratio of two integers, but have a variable phase relationship. The synchronizer places incoming data into a series of registers at the first clock rate. A digital differential analyzer functions to generate a synchronization signal having a frequency proportional to a ratio of the first clock rate and the second clock rate. A multiplexer is utilized for sequentially reading the plurality of registers at a rate corresponding to the frequency of the synchronization signal.Type: GrantFiled: February 2, 1998Date of Patent: July 31, 2001Assignee: Microunity Systems Engineering, Inc.Inventors: Craig C. Hansen, Timothy B. Robinson
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Patent number: 6006318Abstract: A general purpose, programmable media processor for processing and transmitting a media data stream of audio, video, radio, graphics, encryption, authentication, and networking information in real-time. The media processor incorporates an execution unit that maintains substantially peak data throughout of media data streams. The execution unit includes a dynamically partionable multi-precision arithmetic unit, programmable switch and programmable extended mathematical element. A high bandwidth external interface supplies media data streams at substantially peak rates to a general purpose register file and the multi-precision execution unit. A memory management unit, and instruction and data cache/buffers are also provided. High bandwidth memory controllers are linked in series to provide a memory channel to the general purpose, programmable media processor.Type: GrantFiled: October 13, 1998Date of Patent: December 21, 1999Assignee: MicroUnity Systems Engineering, Inc.Inventors: Craig C. Hansen, John Moussouris
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Patent number: 5968165Abstract: A dynamic word size processing system which determines for each instruction the number of cycles required by a data path to compute the result. Values in a register file are augmented with additional information which permits a determination of the number of cycles required based on the values in the register file which are referenced by each instruction. A control path combines the information for each register file operand, and computes a value for the additional information to be stored with the result of the instruction.Type: GrantFiled: May 8, 1997Date of Patent: October 19, 1999Assignee: Microunity Systems Engineering, Inc.Inventor: Craig C. Hansen