Patents Assigned to Mie Fujitsu Semiconductor Limited
  • Publication number: 20180277618
    Abstract: A semiconductor device includes as a resistance element a first polycrystalline silicon and a second polycrystalline silicon containing impurities, such as boron, of the same kind and having different widths. The first polycrystalline silicon contains the impurities at a concentration CX. The second polycrystalline silicon has a width larger than a width of the first polycrystalline silicon and contains the impurities of the same kind at a concentration CY lower than the concentration CX. A sign of a temperature coefficient of resistance (TCR) of the first polycrystalline silicon changes at the concentration CX. A sign of a TCR of the second polycrystalline silicon changes at the concentration CY.
    Type: Application
    Filed: May 30, 2018
    Publication date: September 27, 2018
    Applicant: MIE FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Taiji Ema, Nobuhiro Misawa, Kazuyuki Kumeno, Makoto Yasuda
  • Publication number: 20180277478
    Abstract: There is provided a semiconductor device including a memory region and a logic region. The memory region includes a transistor (memory transistor) that stores information by accumulating charge in a sidewall insulating film. The width of the sidewall insulating film of the memory transistor included in the memory region is made larger than the width of a sidewall insulating film of a transistor (logic transistor) included in the logic region.
    Type: Application
    Filed: May 31, 2018
    Publication date: September 27, 2018
    Applicant: MIE FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Taiji Ema, Makoto Yasuda, Kazuhiro Mizutani
  • Publication number: 20180269286
    Abstract: One aspect of a semiconductor device includes a plurality of first structures, in which each of the first structures includes: a first N-type region; a P-type region which is surrounded by the first N-type region; and a second N-type region which is surrounded by the P-type region. The first N-type region and the P-type region are wired, and the plurality of first structures are connected in parallel to form one diode.
    Type: Application
    Filed: February 22, 2018
    Publication date: September 20, 2018
    Applicant: MIE FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Katsuyoshi Matsuura
  • Publication number: 20180261617
    Abstract: A manufacturing method of a semiconductor device includes: forming a tunnel oxide layer and a charge-storage layer in a region of a flash memory transistor; forming a first oxide film; removing the first oxide film in regions of a first transistor and a second transistor; forming a third oxide film by adding a first oxide layer between a first oxide film and a semiconductor substrate in a region of a third transistor while forming a second oxide film in the regions of the first transistor and the second transistor by oxidation; removing the second oxide film in the region of the first transistor; and forming a fifth oxide film by adding a second oxide layer between the second oxide film and the semiconductor substrate in the region of the second transistor while forming a fourth oxide film in the region of the first transistor by oxidation, and forming a sixth oxide film by adding a third oxide layer between the first oxide layer and the semiconductor substrate in the region of the third transistor.
    Type: Application
    Filed: February 22, 2018
    Publication date: September 13, 2018
    Applicant: MIE FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Satoshi Torii, Hideaki Matsumura, Shu Ishihara
  • Publication number: 20180261683
    Abstract: A semiconductor structure includes first, second, and third transistor elements each having a first screening region concurrently formed therein. A second screening region is formed in the second and third transistor elements such that there is at least one characteristic of the screening region in the second transistor element that is different than the second screening region in the third transistor element. Different characteristics include doping concentration and depth of implant.
    Type: Application
    Filed: April 26, 2018
    Publication date: September 13, 2018
    Applicant: Mie Fujitsu Semiconductor Limited
    Inventors: Dalong Zhao, Teymur Bakhishev, Lance Scudder, Paul E. Gregory, Michael Duane, U.C. Sridharan, Pushkar Ranade, Lucian Shifren, Thomas Hoffmann
  • Patent number: 10074568
    Abstract: Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced sigma VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. Additional structures, configurations, and methods presented herein can be used alone or in conjunction with the DDC to yield additional and different benefits.
    Type: Grant
    Filed: March 9, 2015
    Date of Patent: September 11, 2018
    Assignee: MIE Fujitsu Semiconductor Limited
    Inventors: Scott E. Thompson, Damodar R. Thummalapally
  • Publication number: 20180248548
    Abstract: Digital circuits are disclosed that may include multiple transistors having controllable current paths coupled between first and second logic nodes. One or more of the transistors may have a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region. Resulting reductions in threshold voltage variation may improve digital circuit performance. Logic circuit, static random access memory (SRAM) cell, and passgate embodiments are disclosed.
    Type: Application
    Filed: April 27, 2018
    Publication date: August 30, 2018
    Applicant: Mie Fujitsu Semiconductor Limited
    Inventors: Scott E. Thompson, Lawrence T. Clark
  • Publication number: 20180226401
    Abstract: An integrated circuit can include a plurality of first transistors formed in a substrate and having gate lengths of less than one micron and at least one tipless transistor formed in the substrate and having a source-drain path coupled between a circuit node and a first power supply voltage. In addition or alternatively, an integrated circuit can include minimum feature size transistors; a signal driving circuit comprising a first transistor of a first conductivity type having a source-drain path coupled between a first power supply node and an output node, and a second transistor of a second conductivity type having a source-drain path coupled between a second power supply node and the output node, and a gate coupled to a gate of the first transistor, wherein the first or second transistor is a tipless transistor.
    Type: Application
    Filed: March 27, 2018
    Publication date: August 9, 2018
    Applicant: Mie Fujitsu Semiconductor Limited
    Inventor: David A. Kidd
  • Patent number: 10014363
    Abstract: A semiconductor device includes as a resistance element a first polycrystalline silicon and a second polycrystalline silicon containing impurities, such as boron, of the same kind and having different widths. The first polycrystalline silicon contains the impurities at a concentration CX. The second polycrystalline silicon has a width larger than a width of the first polycrystalline silicon and contains the impurities of the same kind at a concentration CY lower than the concentration CX. A sign of a temperature coefficient of resistance (TCR) of the first polycrystalline silicon changes at the concentration CX. A sign of a TCR of the second polycrystalline silicon changes at the concentration CY.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: July 3, 2018
    Assignee: MIE FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Taiji Ema, Nobuhiro Misawa, Kazuyuki Kumeno, Makoto Yasuda
  • Patent number: 10014254
    Abstract: There is provided a semiconductor device including a memory region and a logic region. The memory region includes a transistor (memory transistor) that stores information by accumulating charge in a sidewall insulating film. The width of the sidewall insulating film of the memory transistor included in the memory region is made larger than the width of a sidewall insulating film of a transistor (logic transistor) included in the logic region.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: July 3, 2018
    Assignee: MIE FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Taiji Ema, Makoto Yasuda, Kazuhiro Mizutani
  • Patent number: 10014387
    Abstract: A semiconductor structure includes first, second, and third transistor elements each having a first screening region concurrently formed therein. A second screening region is formed in the second and third transistor elements such that there is at least one characteristic of the screening region in the second transistor element that is different than the second screening region in the third transistor element. Different characteristics include doping concentration and depth of implant. In addition, a different characteristic may be achieved by concurrently implanting the second screening region in the second and third transistor element followed by implanting an additional dopant into the second screening region of the third transistor element.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: July 3, 2018
    Assignee: MIE FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Dalong Zhao, Teymur Bakhishev, Lance Scudder, Paul E. Gregory, Michael Duane, U. C. Sridharan, Pushkar Ranade, Lucian Shifren, Thomas Hoffmann
  • Patent number: 9991300
    Abstract: Semiconductor devices and methods of fabricating such devices are provided. The devices include source and drain regions on one conductivity type separated by a channel length and a gate structure. The devices also include a channel region of the one conductivity type formed in the device region between the source and drain regions and a screening region of another conductivity type formed below the channel region and between the source and drain regions. In operation, the channel region forms, in response to a bias voltage at the gate structure, a surface depletion region below the gate structure, a buried depletion region at an interface of the channel region and the screening region, and a buried channel region between the surface depletion region and the buried depletion region, where the buried depletion region is substantially located in channel region.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: June 5, 2018
    Assignee: MIE Fujitsu Semiconductor Limited
    Inventors: Teymur Bakhishev, Lingquan Wang, Dalong Zhao, Pushkar Ranade, Scott E. Thompson
  • Patent number: 9985631
    Abstract: Digital circuits are disclosed that may include multiple transistors having controllable current paths coupled between first and second logic nodes. One or more of the transistors may have a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region. Resulting reductions in threshold voltage variation may improve digital circuit performance. Logic circuit, static random access memory (SRAM) cell, and passgate embodiments are disclosed.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: May 29, 2018
    Assignee: MIE FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Scott E. Thompson, Lawrence T. Clark
  • Publication number: 20180130663
    Abstract: A method of manufacturing a semiconductor device includes the following processes. A metal film forming process in which a metal film including cobalt is formed on a surface of silicon. A cap film forming process in which a cap film including titanium is formed on a surface of the metal film. A first thermal processing process in which a cobalt silicide is formed at a specific location of the semiconductor substrate by heating the semiconductor substrate at a first temperature. A second thermal processing process in which the semiconductor substrate is heated at a second temperature higher than the first temperature in nitrogen atmosphere. A removal process in which the cap film and unreacted cobalt are removed. A third thermal processing process in which the cobalt silicide is caused to phase transition by heating the semiconductor substrate at a third temperature higher than the second temperature.
    Type: Application
    Filed: October 19, 2017
    Publication date: May 10, 2018
    Applicant: MIE FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Tetsuo Yoshimura
  • Patent number: 9966130
    Abstract: An integrated circuit can include multiple SRAM cells, each including at least two pull-up transistors, at least two pull-down transistors, and at least two pass-gate transistors, each of the transistors having a gate; at least one of the pull-up transistors, the pull-down transistors, or the pass-gate transistors having a screening region a distance below the gate and separated from the gate by a semiconductor layer, the screening region having a concentration of screening region dopants, the concentration of screening region dopants being higher than a concentration of dopants in the semiconductor layer, the screening region providing an enhanced body coefficient for the pull-down transistors and the pass-gate transistors to increase the read static noise margin for the SRAM cell when a bias voltage is applied to the screening region; and a bias voltage network operable to apply one or more bias voltages to the multiple SRAM cells.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: May 8, 2018
    Assignee: MIE Fujitsu Semiconductor Limited
    Inventors: Lawrence T. Clark, Scott E. Thompson, Richard S. Roy, Robert Rogenmoser, Damodar R. Thummalapally
  • Patent number: 9953974
    Abstract: An integrated circuit can include a plurality of first transistors formed in a substrate and having gate lengths of less than one micron and at least one tipless transistor formed in the substrate and having a source-drain path coupled between a circuit node and a first power supply voltage. In addition or alternatively, an integrated circuit can include minimum feature size transistors; a signal driving circuit comprising a first transistor of a first conductivity type having a source-drain path coupled between a first power supply node and an output node, and a second transistor of a second conductivity type having a source-drain path coupled between a second power supply node and the output node, and a gate coupled to a gate of the first transistor, wherein the first or second transistor is a tipless transistor.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: April 24, 2018
    Assignee: MIE Fujitsu Semiconductor Limited
    Inventor: David A. Kidd
  • Patent number: 9935097
    Abstract: A semiconductor integrated circuit apparatus and a manufacturing method for the same are provided in such a manner that a leak current caused by a ballast resistor is reduced, and at the same time, the inconsistency in the leak current is reduced. The peak impurity concentration of the ballast resistors is made smaller than the peak impurity concentration in the extension regions, and the depth of the ballast resistors is made greater than the depth of the extension regions.
    Type: Grant
    Filed: January 12, 2015
    Date of Patent: April 3, 2018
    Assignee: MIE FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Katsuyoshi Matsuura, Junichi Ariyoshi
  • Patent number: 9922977
    Abstract: A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced ?VT (variation in VT) compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. A novel dopant profile indicative of a distinctive notch enables tuning of the VT setting within a precise range. This VT set range may be extended by appropriate selection of metals of a gate electrode material so that a very wide range of VT settings is accommodated on the die. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. The result is the ability to independently control VT (with a low ?VT) and VDD (the operating voltage supplied to the transistor), so that the body bias can be tuned separately from VT for a given device.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: March 20, 2018
    Assignee: Mie Fujitsu Semiconductor Limited
    Inventors: Reza Arghavani, Pushkar Ranade, Lucian Shifren, Scott E. Thompson, Catherine de Villeneuve
  • Patent number: 9893148
    Abstract: A transistor device with a tuned dopant profile is fabricated by implanting one or more dopant migrating mitigating material such as carbon. The process conditions for the carbon implant are selected to achieve a desired peak location and height of the dopant profile for each dopant implant, such as boron. Different transistor devices with similar boron implants may be fabricated with different peak locations and heights for their respective dopant profiles by tailoring the carbon implant energy to effect tuned dopant profiles for the boron.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: February 13, 2018
    Assignee: MIE Fujitsu Semiconductor Limited
    Inventors: Teymur Bakhishev, Sameer Pradhan, Thomas Hoffmann, Sachin R. Sonkusale
  • Patent number: 9865596
    Abstract: A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced ?VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. The semiconductor structure includes an analog device and a digital device each having an epitaxial channel layer where a single gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the digital device and one of a double and triple gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the analog device.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: January 9, 2018
    Assignee: MIE Fujitsu Semiconductor Limited
    Inventors: Lucian Shifren, Pushkar Ranade, Scott E. Thompson, Sachin R. Sonkusale, Weimin Zhang