Abstract: A switching regulator circuit and a reference compensation module employed for compensating a reference signal in the switching regulator circuit. The switching regulator circuit with a reference ground having an average offset voltage referenced to a package ground pin, wherein the average offset voltage is proportional to an output current of the switching regulator circuit with a first factor. The reference compensation module may be configured to receive a second reference signal having a bandgap reference voltage with respect to the reference ground and a reference compensation signal proportional to the output current with a second factor, and configured to provide the first reference signal based on compensating the second reference signal with the reference compensation signal to substantially cancel out the average offset voltage from the first reference signal with respect to the ground pin.

Abstract: A high voltage FET device provides drain voltage information with less overall silicon area consumption by forming a spiral resistance poly structure over a drift region of the high voltage FET device. The spiral resistance poly structure has an inner most end coupled to a drain region, and an outer most end coupled to a reference ground.

Abstract: An ESD protection circuit has a clamp control circuit and a clamp switch. The clamp switch has a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled to a first node, and the second terminal is coupled to a second node. The clamp control circuit is coupled between the first node and the second node, wherein the clamp control circuit is configured to detect the rising time of the voltage between the first node and the second node, and to provide a clamp control signal to the control terminal of the clamp switch based on the rising time, if the rising time is shorter than a first time threshold, the clamp switch is turned ON for a second time threshold, and wherein the first time threshold is shorter than the second time threshold.

Abstract: An off-line regulator has a rectification circuit configured to rectify an AC line voltage into a rectified line voltage, a pass device coupled between the rectified line voltage and a first capacitor, and a converter. The pass device is configured to be turned ON or OFF according to a comparison signal indicating whether the rectified line voltage is over a threshold voltage. The first capacitor delivers an interim voltage into the converter which supplies power to a load. Wherein a second capacitor coupled across a driver which driving the pass device is charged by the first capacitor when the comparison signal is at a first state, and the driver is boosted when the comparison signal is at a second state.

Abstract: The present disclosure discloses a high voltage semiconductor device and the associated methods of manufacturing. In one embodiment, the high voltage semiconductor device comprises: an epitaxial layer, a first low voltage well formed in the epitaxial layer; a second low voltage well formed in the epitaxial layer; a high voltage well formed in the epitaxial layer, wherein the second low voltage well is surrounded by the high voltage well; a first highly doping region formed in the first low voltage well; a second highly doping region and a third highly doping region formed in the second low voltage well, wherein the third highly doping region is adjacent to the second highly doping region; a field oxide formed in the epitaxial layer as a shallow-trench isolation structure; and a gate region formed on the epitaxial layer.

Abstract: A SMPS having a switch; an output port coupled to a load, configured to provide a voltage feedback signal and a current feedback signal; an on-time generator, having an input end coupled to the current feedback signal, and having an output end providing a time signal indicating a time period; and a PWM generator, having a first input end coupled to the voltage feedback signal, a second input end coupled to the time signal, and an output end providing a PWM signal that is coupled to the control end of the switch, and wherein the PWM signal is configured to turn ON the switch when the voltage feedback signal is lower than a threshold voltage, and the PWM signal is configured to turn OFF the switch after the time period.

Abstract: Method of forming dual gate insulation layers and semiconductor device having dual gate insulation layers is disclosed. The method of forming dual gate insulation layers comprises forming a first thin layer of a thick gate insulation layer on a semiconductor substrate by oxidizing the semiconductor substrate, depositing a second thicker layer of the thick gate insulation layer on the first thin layer, removing a portion of the thick gate insulation layer to expose a surface area of the semiconductor substrate and forming a thin gate insulation layer on the exposed surface area of the semiconductor substrate. The method of forming dual gate insulation layers, when applied in fabricating semiconductor devices having dual gate insulation layers and trench isolation structures, may help to reduce a silicon stress near edges of the trench isolation structures and reduce/alleviate/prevent the formation of a leaky junction around the edges of the trench isolation structures.

Abstract: Processes of assembling microelectronic packages with lead frames and/or other suitable substrates are described herein. In one embodiment, a method for fabricating a semiconductor assembly includes forming an attachment area and a non-attachment area on a lead finger of a lead frame. The attachment area is more wettable to the solder ball than the non-attachment area during reflow. The method also includes contacting a solder ball carried by a semiconductor die with the attachment area of the lead finger, reflowing the solder ball while the solder ball is in contact with the attachment area of the lead finger, and controllably collapsing the solder ball to establish an electrical connection between the semiconductor die and the lead finger of the lead frame.

Abstract: A field effect transistor (“FET”), a termination structure and associated method for manufacturing. The FET has a plurality of active transistor cells and a termination structure. The termination structure for the FET includes a plurality of termination cells arranged substantially in parallel from an inner side toward an outer side of a termination area of the FET. Each of the termination cells comprises a termination trench lined with a termination insulation layer and filled with a termination conduction layer. The innermost termination cell is electrically coupled to gate regions of the active transistor cells while the rest of the termination cells are electrically floating.

Abstract: A method having a negative output voltage at a negative output terminal of a charge pump tracking a positive output voltage at a positive output terminal of the charge pump. The charge pump comprises a plurality of switches and each of the plurality of switches has a serially coupled resistance. The method comprises selecting the serially coupled resistance for at least one of the plurality of switches to be different to each of the other respective serially coupled resistances associated to the other switches.

Abstract: A LED driving system comprising: an input port to receive an input signal; a switch node to provide a switching signal; an energy storage component coupled between the input port and the switch node; a main switch coupled between the switch node and ground; n output lines coupled in parallel, and each output line having a first and second terminals, and wherein the first terminal is coupled to the switch node, and the second terminal is coupled the reference ground, and wherein each output line having an output switch, a diode and a LED string coupled in series between the first and second terminals, and wherein each output line having a capacitor coupled in parallel with the LED string; and a controller providing a control signal to the main switch and providing corresponding n control signals to the corresponding n output switches in the corresponding n output lines.

Abstract: The present invention discloses an analog switching circuit having a first terminal receiving an input signal, a second terminal providing an output signal and a control terminal receiving a switching control signal. The analog switching circuit has a first logic circuit providing a first control signal and a second control signal based on the switching control signal; an NMOS and a PMOS coupled between the first terminal and the second terminal, and controlled by the first control signal and the second control signal respectively; a first control circuit controls the backgate voltage of the NMOS based on the input signal and the switching control signal; and a second control circuit controls the backgate voltage of the PMOS based on the input signal and the switching control signal.

Abstract: In one embodiment, a switch mode power supply comprising a switch and a control circuit is disclosed. The control circuit may comprise a multi-function pin configured to receive a first current sampling signal and a first voltage sampling signal. A first comparing signal may be provided by comparing the first voltage sampling signal with a first threshold signal when the switch is turned OFF, and a second comparing signal may be provided by comparing the first current sampling signal with a second threshold signal when the switch is turned ON. The control circuit may be configured to control the switch in accordance with the first comparing signal and the second comparing signal.

Abstract: A high voltage FET device provides drain voltage information with less overall silicon area consumption by forming a spiral resistance poly structure over a drift region of the high voltage FET device. The spiral resistance poly structure has an inner most end coupled to a drain region, and an outer most end coupled to a reference ground.

Abstract: A switch-mode voltage converter has a switching transistor coupled between an input voltage (Vin) and the ground and a controller coupled directly between the input voltage (Vin) and the ground. The controller periodically turns on the switching transistor for a generally constant period of time. The controller is further coupled to a DC bias voltage (Vbias) and generates a control current based on the input voltage (Vin) and the DC bias voltage (Vbias) for generating a switching signal to the switching transistor.

Abstract: An offline power converter provides low EMI and quick reaction by slowly turning off a power switch at normal operation, and fast turning off the power switch when surge event happens.

Abstract: The present technology relates generally to a closed-loop power stage and audio amplifier circuits comprising the same. The present technology further provides a method for controlling an amplifier circuit. The closed-loop power stage is configured to receive a PWM input signal having a first frequency and a first duty cycle, a power supply voltage, and a bias signal related to the power supply voltage, and to output a square-wave signal having a second frequency and a second duty cycle. The closed-loop power stage comprises a feedback loop which is configured to regulate the second duty cycle of the square-wave signal in response to a variation in the power supply voltage. The audio amplifier circuit comprising the closed-loop power stage may have a stable output voltage and thus have good power supply rejection performance.

Abstract: A switching regulator circuit and a reference compensation module employed for compensating a reference signal in the switching regulator circuit. The switching regulator circuit with a reference ground having an average offset voltage referenced to a package ground pin, wherein the average offset voltage is proportional to an output current of the switching regulator circuit with a first factor. The reference compensation module may be configured to receive a second reference signal having a bandgap reference voltage with respect to the reference ground and a reference compensation signal proportional to the output current with a second factor, and configured to provide the first reference signal based on compensating the second reference signal with the reference compensation signal to substantially cancel out the average offset voltage from the first reference signal with respect to the ground pin.

Abstract: The present technology is related generally to a switching mode power supply with virtual current sensing. The switching mode power supply comprises a power stage that includes a first power switch and a second power switch coupled in series. The switching mode power supply senses a first current flowing through the first power switch during on-time and provides a virtual current sense signal that is proportional to a second current flowing through the second power switch during on-time. The switching mode power supply further combines the real current sense signal and the virtual current sense signal to form a current sense signal, which is sent to the controller to realize desired control.

Abstract: An integrated circuit for implementing a switch-mode power converter is disclosed. The integrated circuit comprises at least a first semiconductor die having an electrically quiet surface, a second semiconductor die for controlling the operation of said first semiconductor die stacked on said first semiconductor die having said electrically quiet surface and a lead frame structure for supporting said first semiconductor die and electrically coupling said first and second semiconductor dies to external circuitry.