Abstract: A method for fabricating a LDMOS device in a well region of a semiconductor substrate, including: etching a polysilicon layer above the well region through a window for a body region; and forming spacers at side walls of the polysilicon layer, to define positions of source regions in the well region.

Abstract: A multiphase power supply includes several constant ON-time (COT) DC-DC converter integrated circuits (ICs). One of the COT DC-DC converter ICs generates a synchronization signal, which is received in parallel by the other COT DC-DC converter ICs. Two or more COT DC-DC converter ICs are turned ON at the same time in synchronization with the synchronization signal (e.g., an edge of a pulse of the synchronization signal) that is received in parallel and with another synchronization signal that is propagated from one COT DC-DC converter IC to another.

Abstract: A lateral DMOS device with peak electric field moved below a top surface of the device along a body-drain junction is introduced. The LDMOS has a deep body and a drift region formed by a series of P-type and N-type implants, respectively. The implant doses and depths are tuned so that the highest concentration gradient of the body-drift junction is formed below the surface, which suppresses the injection and trapping of hot holes in the device drain-gate oxide region vicinity, and the associated device performance changes, during operation in breakdown.

Abstract: An ESD protection circuit used to protect a protected circuit coupled between a first node and a second node against an ESD event. The ESD protection circuit has a discharging circuit and a control circuit. The discharging circuit selectively provides a current path for discharging a current from the first node to the second node. The control circuit controls the discharging circuit to switch on the current path during an ESD event. The control circuit further controls the discharging circuit to switch off the current path during the normal operation of the protected circuit.

Abstract: A method for fabricating a LDMOS device in a well region of a semiconductor substrate, including: forming a body region and a source layer in the well region through a window of a polysilicon layer above the well region, wherein the body region has a deeper junction depth than the source layer; forming spacers at side walls of the polysilicon layer; and etching through the source layer through a window shaped by the spacers, wherein the source layer under the spacers is protected from etching, and is defined as source regions of the LDMOS device.

Abstract: A current sense circuit for sensing a target current flowing through a sensing resistor, has a first operational amplifier, a first transistor and a common mode adjust circuit. The first operational amplifier has a first input terminal coupled to a positive terminal of the sensing resistor, a second input terminal coupled to a negative terminal of the sensing resistor, and an output terminal. The first transistor has a first terminal coupled to the first input terminal of the first operational amplifier, a second terminal configured to provide a first output voltage in responsive to the target current, and a control terminal coupled to the output terminal of the first operational amplifier. The common mode adjust circuit adaptively adjusts a common mode voltage of the first operational amplifier.

Abstract: A monolithic integrated circuit (IC) switch device includes an input pin that receives an input power supply and an output pin that is connected to a load. The monolithic IC switch device includes driving circuitry that controls a switching operation of a power switch to connect and disconnect the input power supply to and from the load. A microcontroller can enable or disable the monolithic IC switch device based on indicator signals received by the microcontroller from the monolithic IC switch device.

Abstract: A reference signal generator used with a switching mode power supply which converts an input voltage to an output voltage. The reference signal generator provides a reference signal consisting of a constant voltage signal and a variable voltage signal which is varying according to a duty cycle of the switching mode power supply during a startup period of the switching mode power supply and is varying according to a ratio of the input voltage at an end of the startup period to the input voltage of real time after the startup period.

Abstract: An electronic device with substrate current management. The electronic device has a semiconductor substrate in which a Schottky diode is formed. A parasitic PN diode is also formed in the semiconductor substrate, and coexisted with the Schottky diode in parallel. The forward voltage of the Schottky diode is limited to be larger than the forward conduction threshold voltage of the Schottky diode and to be smaller than the forward conduction threshold voltage of the parasitic PN diode.

Abstract: A power supply includes a half-bridge circuit. The power supply further includes an output inductor connected to a switch node that is common to a high side switch and a low side switch of the half-bridge. During a turn ON time of the low side switch, a current detection circuit of the power supply samples and holds in a capacitor a valley of an inductor current flowing through the output inductor. Also during the turn ON time of the low side switch, the current detection circuit samples and holds in another capacitor a peak of the inductor current. During a turn OFF time of the low side switch, a sense inductor current that is representative of the inductor current is generated by combining the charges stored in the capacitors.

Abstract: An integrated circuit (IC) chip includes a copper structure with an intermetallic coating on the surface. The IC chip includes a substrate with an integrated circuit. A metal pad electrically connects to the integrated circuit. The copper structure electrically connects to the metal pad. A solder bump is disposed on the copper structure. The surface of the copper structure has a coating of intermetallic. The copper structure can be a redistribution layer and a copper pillar that is disposed on the redistribution layer.

Abstract: In one embodiment, a current sensing circuit includes a differential current sensing amplifier adapted for sensing a voltage drop across a main transistor, the differential current sensing amplifier being adapted for providing a switched current output to a timing circuit which is adapted for providing a timing signal to one or more switching current sample-and-hold circuits based on a current waveform of the switched current output, and the one or more switching current sample-and-hold circuits, each of which are adapted for producing a substantially continuous output current. In another embodiment, a method for detecting a current includes driving a main transistor with a first current, driving one or more sensing transistors with a second current, measuring a sensing inductor current of the one or more sensing transistors, and determining the first current based on the sensing inductor current, wherein the sensing inductor current is related to the first current.

Abstract: A power supply includes a half-bridge circuit. The power supply further includes an output inductor connected to a switch node that is common to a high side switch and a low side switch of the half-bridge. During a turn ON time of the low side switch, a current detection circuit of the power supply samples and holds in a capacitor a valley of an inductor current flowing through the output inductor. Also during the turn ON time of the low side switch, the current detection circuit samples and holds in another capacitor a peak of the inductor current. During a turn OFF time of the low side switch, a sense inductor current that is representative of the inductor current is generated by combining the charges stored in the capacitors.

Abstract: A control method of frequency jittering with a switching mode power supply, comprising: turning on and off a power switch of the switching mode power supply alternatively; updating a peak current signal of the switching mode power supply at a beginning of an on time of the power switch according to a length of a switching period before the beginning of the on time of the power switch, wherein the peak current signal varies as the length of the switching period changes.

Abstract: A switching circuit with a fault instruction circuit used in a voltage converter or a multi-phase voltage converter. The switching circuit has a pin, the pin is configured to receive a control signal during a normal operation, and the pin is also configured to output a fault instruction signal when one or more faults occur in the switching circuit. The instruction signal represents each of the one or more faults with a particular value.

Abstract: A voltage control circuit for a memory cell having a floating gate transistor and a capacitive device, comprising a first input terminal, a second input terminal, a first output terminal and a second input terminal, wherein the first input terminal is configured to receive a power supply voltage, the second input terminal is configured to receive a ground reference, and wherein based on the power supply voltage and the ground reference, the first output terminal and the second output terminal respectively provides a first voltage signal and a second voltage signal, and wherein a voltage value of the first voltage signal is twice the power supply voltage, and a maximum of a voltage difference between the first voltage signal and the second voltage signal is three times the power supply voltage.

Abstract: The present disclosure discloses a semiconductor device having conductive bumps formed on a conductive redistribution layer and associated method for manufacturing. The semiconductor device may further include a first type shallow trench formed on a passivation layer overlying a semiconductor substrate. The conductive redistribution layer is formed in the first type shallow trench. A polyimide layer may be formed between neighboring conductive redistribution layers should a plurality of the conductive redistribution layers are formed with or without the first type shallow trench formed for each of the plurality of conductive redistribution layers.

Abstract: An integrated circuit (IC) chip includes a copper structure with an intermetallic coating on the surface. The IC chip includes a substrate with an integrated circuit. A metal pad electrically connects to the integrated circuit. The copper structure electrically connects to the metal pad. A solder bump is disposed on the copper structure. The surface of the copper structure has a coating of intermetallic. The copper structure can be a redistribution layer and a copper pillar that is disposed on the redistribution layer.

Abstract: A current balance circuit for a power management device having a first current channel and a second current channel, having: a first current sense circuit configured to detect a current flowing through the first current channel, and to provide a first current sense signal indicative of the current flowing through the first current channel; wherein the current balance circuit draws current from the second current channel to the first current channel based on the first current sense signal.

Abstract: A computer provides a graphical user interface for displaying a virtual representation of a voltage regulator and for accepting a user requirement for the voltage regulator. The computer automatically determines an internal calibration setting of the voltage regulator that meets the user requirement. The computer simulates operation of the voltage regulator as calibrated with the internal calibration setting. The internal calibration setting is downloaded to the voltage regulator. A calibration controller of the voltage regulator receives the internal calibration setting and outputs digital calibration bits in accordance with the internal calibration setting. The digital calibration bits works in conjunction with interface circuits to adjust circuits of a voltage regulator core to digitally calibrate the voltage regulator.