Abstract: A light-emitting element driving device and controller and dimming method for the light-emitting element driving device. The light-emitting driving device has a dimming resistor and a power converter. A first current is provided to the dimming resistor, and a voltage across the dimming resistor is compared with a first threshold voltage. Then a second current is provided according to the comparison result. A dimming signal is generated based the voltage across the dimming resistor and a current flowing through the dimming resistor, to control the power converter to drive a plurality of light-emitting elements. A plurality of voltage windows may be configured for the dimming signal. a 2-step dimming function may be activated for high precision.

Abstract: A multi-input single output power system for outputting an output voltage on an output node. It includes a first integrated circuit (IC) converter device and a second IC converter device. The first IC converter device has a first pin to receive a first input voltage, a second pin to output the output voltage, and a first power unit coupled between the first pin and the second pin. The second IC converter device has a first pin to receive a second input voltage, a second pin to output the output voltage, a second power unit coupled between the first pin of the second IC converter device and the second pin of the second IC converter device, and a third pin. The third pin receives an external phase shedding control signal to determine whether to stop the second power unit from providing power to the output node.

Abstract: A buck-boost converter working in a buck mode with buck switching cycles, a boost mode with boost switching cycles or a buck-boost mode with buck-boost switching cycles. Each of the buck-boost switching cycles has an AC phase, an AD phase and a BD Phase, and the duty cycle of the AC phase is determined by a reference signal, a feedback signal and an inductor current sense signal, the duty cycle of the AD phase is controlled and maintained at a preset duty threshold, the time period of the buck-boost switching cycle equals the time period of the buck switching cycle and the time period of the boost switching cycle.

Abstract: A feedback control circuit in an LED driving circuit for driving a plurality of LED strings. Each LED string provides a headroom detecting voltage. The feedback control circuit has a status detecting circuit, a counting circuit and a modulating circuit. The status detecting circuit compares each headroom detecting voltage with a low headroom threshold voltage and a high headroom threshold voltage and generates an up self-status signal and a down self-status signal. The counting circuit counts or keeps unchanged and then generates a counting signal based on the up self-status signal and the down self-status signal. The modulating circuit generates a modulating signal based on the counting signal. And based on the modulating signal, the feedback control circuit generates a feedback control signal to regulate a bias voltage supplying the plurality of LED strings.

Abstract: A trans-inductor voltage regulator (TLVR) circuit has multiple phases and a switching circuit for each phase. Each switching circuit has a winding of a transformer as an output inductor. The other windings of the transformers are connected in series with a nonlinear compensation inductor. An on-time period of each switching circuit is reduced when a load transient condition occurs or when a load current starts to be stable after the load transient condition.

Abstract: The present disclosure describes vertical transistor device and methods of making the same. The vertical transistor device includes substrate layer of first conductivity type, drift layer of first conductivity type formed over substrate layer, body region of second conductivity type extending vertically into drift layer from top surface of drift layer, source region of first conductivity type extending vertically from top surface of drift layer into body region, dielectric region including first and second sections formed over top surface, buried channel region of first conductivity type at least partially sandwiched between body region on first side and first and second sections of dielectric region on second side opposite to first side, gate electrode formed over dielectric region, and drain electrode formed below substrate layer. Dielectric region laterally overlaps with portion of body region. Thickness of first section is uniform and thickness of second section is greater than first section.

Abstract: A FET device has a substrate, a plurality of repetitive source stripes, a first layout of drain stripe having a first drift region and a first drain region, a second layout of drain stripe having a second drift region and a second drain region, a first drain contactor contacted with the first drain region and connected to a drain terminal, a second drain contactor contacted with the second drain region and connected to a first gate terminal, a source contactor contacted with a source region in each of the plurality of repetitive source stripes and connected to a source terminal, a first gate region positioned between the source region and the first drain region and connected to the first gate terminal, and a second gate region positioned between the source region and the second drain region and connected to a second gate terminal.

Abstract: A fault detection method is sampling currents flowing through a plurality of switching circuits to generate a plurality of current sampling signals, generating a first reference signal and a second reference signal based on a predetermined reference signal and a ripple threshold signal, and generating a plurality of fault signals based on comparison results of each of the plurality of current sampling signals with the first reference signal and the second reference signal. When one of the plurality of current sampling signals is between the first reference signal and the second reference signal, a corresponding one of the plurality of fault signals changes to a first state, and when the corresponding one of the plurality of fault signals remains the first state for more than a predetermined time period, a corresponding one of control signals turns off a corresponding one of the plurality of switching circuits.

Abstract: A control circuit used in a resonant converter with a switching circuit and a resonant circuit is provided, the switching circuit has a high side transistor and a low side transistor, the resonant circuit has a resonant capacitor and a resonant inductor. The control circuit includes: a calculating module used to generate an output current calculating value based on a voltage across the resonant capacitor and a correction signal at an off moment of the high side transistor; a comparing module used to compare the output current calculating value with a burst mode threshold value and generate a burst mode control signal by comparing the output current calculating value with the burst mode threshold value; and a switching control module used to control the resonant converter to work in a burst mode or a normal mode based on the burst mode control signal.

Abstract: Junction field effect transistors (JFETs) and related manufacturing methods are disclosed herein. A disclosed JFET includes a vertical channel region located in a mesa and a first channel control region located on a first side of the mesa. The first channel control region is at least one of a gate region and a first base region. The JEFT also includes a second base region located on a second side of the mesa and extending through the mesa to contact the vertical channel region. The vertical channel can be an implanted vertical channel. The vertical channel can be asymmetrically located in the mesa towards the first side of the mesa.

Abstract: A control method for regulating the switching frequency of a resonant converter having an input terminal to receive an input voltage and an output terminal to output an output voltage. The control method is sensing the input voltage and adjusting the switching frequency based on the comparison of the input voltage with a reference threshold voltage. When the input voltage is less than the reference threshold voltage, the switching frequency is adjusted to decrease, and when the input voltage is higher than the reference threshold voltage, the switching frequency is adjusted to increase.

Abstract: A driving circuit for driving a synchronous rectifier device. The driving circuit may include a controllable clamping circuit having a first terminal coupled to a sensing terminal of the driving circuit, a second terminal coupled to a reference ground terminal of the driving circuit, a third terminal coupled to a driving terminal of the driving circuit, and a control terminal configured to receive a supply indication signal indicative of a voltage potential at a supply terminal of the driving circuit. The third terminal of the controllable clamping circuit may be connected to the second terminal of the controllable clamping circuit when the supply indication signal indicates that the voltage potential at the supply terminal has not been established to maintain the synchronous rectifier device off.

Abstract: A control circuit having: a logic circuit, configured to provide a high side boot-strap capacitor control signal set and a low side boot-strap capacitor control signal set; a high side boot-strap capacitor control circuit, configured to provide a high side power signal to control a high side power switch; a high side boot-strap capacitor, having a first terminal coupled to a control terminal of the high side power switch, and a second terminal coupled to the high side boot-strap capacitor control circuit; a low side boot-strap capacitor control circuit, configured to provide a low side power signal to control a low side power switch; and a low side boot-strap capacitor, having a first terminal coupled to a control terminal of the low side power switch, and a second terminal coupled to the low side boot-strap capacitor control circuit.

Abstract: A switching mode power supply preventing false triggering of an over current protection due to a surge pulse. The switching mode power supply has a switch and an inductor. An inductor current flows through the inductor. The switching mode power supply turns off the switch and meanwhile starts timing for a preset period of time when the inductor current is larger than a preset value. The switch is kept off during the preset period of time and is then turned on when the preset period of time expires.

Abstract: A charging termination control module and a battery charger circuit comprising the same. The charging termination control module may detect/monitor/sense a charging current flowing through a charging control transistor of the battery charger circuit to provide a current sense signal, and to maintain a transistor voltage drop across the charging control transistor at a predetermined difference value once the transistor voltage drop reaches the predetermined difference value. The charging termination control module may also turn the charging control transistor off once the current sense signal is decreased to reach or to be lower than a charging termination threshold.

Abstract: A voltage converter with a high side power switch, having: an off control circuit, having a first input terminal configured to receive an input voltage, a second input terminal configured to receive an output voltage, a third input terminal configured to receive a current representing signal indicative of a current flowing through the high side power switch, a fourth input terminal configured to receive an on-set signal in response to an on operation of the high side power switch, and an output terminal configured to provide an off control signal to indicate an end of an on time period of the high side power switch; wherein the on time period of the high side power switch is regulated by the input voltage, the output voltage and the current representing signal.

Abstract: Voltage regulators generate voltage rails that power a central processing unit (CPU). The CPU communicates power management instructions to a power supply controller that drives the voltage regulators. The power supply controller sets a voltage level of a voltage rail generated by a voltage regulator in accordance with a power management instruction received from the CPU. The power supply controller enables the voltage regulator to operate in discontinuous conduction mode (DCM) independent of power state commands from the CPU.

Abstract: The present disclosure describes vertical transistor device and methods of making the same. The vertical transistor device includes substrate layer of first conductivity type, drift layer of first conductivity type formed over substrate layer, body region of second conductivity type extending vertically into drift layer from top surface of drift layer, source region of first conductivity type extending vertically from top surface of drift layer into body region, dielectric region including first and second sections formed over top surface, buried channel region of first conductivity type at least partially sandwiched between body region on first side and first and second sections of dielectric region on second side opposite to first side, gate electrode formed over dielectric region, and drain electrode formed below substrate layer. Dielectric region laterally overlaps with portion of body region. Thickness of first section is uniform and thickness of second section is greater than first section.

Abstract: A lateral DMOS having a well region, a source region, a drain region, a first gate region and a second gate region. The first gate region may be positioned atop a portion of the well region near the source region side. The second gate region may be formed in a portion of the well region near the drain region side. The second gate region includes a shallow trench isolation structure formed in a shallow trench opened from a top surface of the well region and extended vertically into the well region, and having a first sidewall contacting with the drain region or abut the drain region, and further having a second sidewall opposite to the first sidewall and laterally extended below the first gate region.

Abstract: An LED driving system with a master-slave architecture. The LED driving system has at least two LED driving circuits which both have a first status detecting circuit, a second status detecting circuit and a first feedback control circuit. The first status detecting circuit receives a plurality of headroom detecting voltages provided by a plurality of LED strings and generates at least one self-status signal. The second status detecting circuit receives a downstream feedback signal and generates at least one downstream status signal. The first feedback control circuit generates a first feedback control signal based on the at least one self-status signal and the at least one downstream status signal. The second status detecting circuit of one LED driving circuit is coupled to the first feedback control circuit of the other LED driving circuit.