Abstract: A controller of an isolated switching converter having a primary and secondary switch, the controller includes a valley detection circuit for providing a valley pulse signal in response to valleys of a resonant voltage, a pulse frequency modulation circuit for providing a pulse frequency modulation signal based on a feedback signal indicative of an output voltage, a primary on enable circuit for providing a primary on enable signal based on the pulse frequency modulation signal and valley pulse signal, a secondary logic circuit for generating a secondary control signal to control the secondary switch based on a primary off detection signal, a zero cross detection signal and the primary on enable signal, and a primary logic circuit for generating a primary control signal to control the primary switch based on a synchronous signal electrically isolated from the primary on enable signal.

Abstract: A power supply circuit for a switching mode power supply, having: a charging capacitor coupled to an auxiliary winding; a power supply diode coupled to a power supply capacitor, wherein the charging capacitor has a connecting terminal coupled to the power supply diode, and the charging capacitor and the power supply diode are serially coupled between the auxiliary winding of the switching mode power supply and the power supply capacitor; and a power supply switch coupled between the connecting terminal and a primary ground of the switching mode power supply.

Abstract: A controller of a switching converter includes an error amplifying circuit, a first comparison circuit, a valley detection circuit, a valley selection circuit and a frequency control circuit. The error amplifying circuit generates a compensation signal based on the difference between a reference signal and a feedback signal. The first comparison circuit compares the compensation signal with a modulation signal and generates a pulse frequency modulation signal. The valley detection circuit detects valleys of a resonant voltage of the switching converter and generates a valley pulse signal. The valley selection circuit generates a valley enable signal corresponding to a target valley number based on the pulse frequency modulation signal and the valley pulse signal. The frequency control circuit generates a frequency control signal to control the switching frequency of the first switch based on the valley enable signal and the valley pulse signal.

Abstract: An LLC resonant converter including a transformer, a switching full-bridge circuit, a resonant circuit, and a bridge rectifier. The switching full-bridge circuit has a first pair of switches and a second pair of switches, with the first pair of switches being connected between a DC input voltage and a second end of a secondary winding of the transformer, the second pair of switches being connected between a DC input voltage and a first end of the secondary winding of the transformer.

Abstract: A gate driver is configured to drive a normally-on device and a normally-off device coupled in series. The gate driver controls the normally-on device in response to a PWM signal, and to control a normally-off device to maintain ON in normal operations. If an under voltage condition of a negative power supply of a first driver used to drive the normally-on device, or a positive power supply of a second driver used to drive the normally-off device, or an input supply voltage is detected, the normally-off device is controlled to be OFF.

Abstract: A field-plate trench FET having a drain region, an epitaxial layer, a source region, a gate conductive layer formed in a trench, a field-plate dielectric layer formed on vertical sidewalls of the trench, a well region formed below the trench, a source contact and a gate contact. When the well region is in direct physical contact with the gate conductive layer, the field-plate trench FET can be used as a normally-on device working depletion mode, and when the well region is electrically isolated from the gate conductive layer by the field-plate layer, the field-plate trench FET can be used as a normally-off device working in an accumulation-depletion mode.

Abstract: The present disclosure describes vertical transistor device and methods of making the same. The vertical transistor device includes substrate layer of first conductivity type, drift layer of first conductivity type formed over substrate layer, body region of second conductivity type extending vertically into drift layer from top surface of drift layer, source region of first conductivity type extending vertically from top surface of drift layer into body region, dielectric region including first and second sections formed over top surface, buried channel region of first conductivity type at least partially sandwiched between body region on first side and first and second sections of dielectric region on second side opposite to first side, gate electrode formed over dielectric region, and drain electrode formed below substrate layer. Dielectric region laterally overlaps with portion of body region. Thickness of first section is uniform and thickness of second section is greater than first section.

Abstract: An inductor has one or more wires and a multipart magnetic core. The multipart magnetic core has magnetic core parts that are adjacent and magnetically coupled. The inductor provides an inductance of at least 40 nH for currents greater than 1 A and less than 60 A, and at least 20 nH for currents of at least 60 A.

Abstract: A panel-shaped metal wall grids array for panel level IC packaging and associated manufacturing method. Each metal wall grid in the metal wall grids array has a continuous and closed metal wall of a predetermined wall height. The metal wall grids are connected to form a monolithic panel through a plurality of metal connecting portions. When the panel-shaped metal wall grids array is used for panel level IC packaging, at least one IC chip/IC die is disposed in each metal wall grid with a top surface of each IC chip/IC die facing downwards, and a panel-shaped metal layer matching with the panel-shaped wall grids array may be further formed on the entire back side of the panel-shaped metal wall grids array so that the panel-shaped metal layer is bonded to the metal wall of each metal wall grid.

Abstract: A 3-D package structure for isolated power module is discussed. The package structure has metal trace in a support layer (e.g. a substrate board), which is covered by two magnetic films from both sides, thus an effective transformer is formed. An IC die which contains a voltage regulator is stacked above the support layer, which significantly reduces the package size.

Abstract: A trans-inductor voltage regulator (TLVR) has regulator blocks and transformers. Secondary windings of the transformers are connected in series with a compensation inductor to form a trans-inductor loop, which is connected to the output voltage of the TLVR instead of to ground. Primary windings of the transformers serve as output inductors of the regulator blocks. The inductance of each output inductor and the output inductance of the TLVR are input to an averaging network of an averaging inductor direct current resistance (DCR) current sense circuit to generate an average sensed voltage. The average sensed voltage is converted to an average sensed current, which is used by a controller to generate control signals that drive the regulator blocks to generate the output voltage of the TLVR.

Abstract: A switching converter has four switches and a control circuit. The control circuit provides a first drive signal to control a first switch and a second drive signal to control a second switch based on a first set signal, and provides a third drive signal to control the third switch and a fourth drive signal to control the fourth switch based on a second set signal. When an output voltage is larger than an input voltage, an on-time period of the third switch is adaptively adjusted according to the input voltage, the output voltage and a first parameter. When the output voltage is less than the input voltage, the on-time period of the third switch is adaptively adjusted according to the input voltage, the output voltage and a second parameter.

Abstract: A position sensing system has a trim unit to trim hall voltages generated by a first sensor and a second sensor in response to an excitation current, to compensate a non-orthogonality of the first sensor and the second sensor.

Abstract: A control circuit for controlling a switching converter having a low quiescent current. The control circuit has an error amplifying circuit, an on time generator, a first comparing circuit and a second comparing circuit. When the switching converter operates in a light load operation mode, the error amplifying circuit and the on time generator are deactivated. Meanwhile, the first comparing circuit compares a current sensing signal indicative of inductor current with a current reference signal to provide an off time control signal during an on state of a low side switch to determine an on moment of a high side switch. The second comparing circuit compares the voltage feedback signal with a voltage reference signal to provide an on time control signal to determine an off moment of the high side switch.

Abstract: A bi-directional buffer for applications using in an I2C or SMBUS or other bus systems. The bi-directional buffer has an input terminal to receive an input voltage signal and an output terminal for providing an output voltage signal, and the output voltage signal follows the input voltage signal. The output voltage signal is regulated to have a first bias voltage greater than the input voltage signal by a first operational amplifier, or to have a second bias voltage greater than the input voltage signal by a second operational amplifier, the second bias voltage is smaller than the first bias voltage.

Abstract: An IC package structure and an IC package unit are disclosed. The IC package includes an array of metal wall grids formed into a panel, each one of the metal wall grids having a continuous and closed metal wall to surround an IC package unit with at least one IC chip/IC die disposed therein. Each IC chip/IC die has a top surface with a plurality of metal pads formed thereon. A panel-shaped metal layer is formed on entire back side of the panel of the array of metal wall grids and bonded to the metal wall of each metal wall grid. A panel-shaped rewiring substrate having a plurality of metal pillars is connected to each IC chip/IC die with each one of the plurality of metal pillars soldered with a corresponding one of the plurality of metal pads.

Abstract: A multi-phase voltage converter has a plurality of integrated circuits (ICs), and a controller. Each IC has a control pin to receive a control signal, a monitoring pin and a temperature sensing circuit, the controller has a monitoring pin connected to the monitoring pin of each of the plurality of ICs to receive a monitoring signal. The temperature sensing circuit is connected to or disconnected from the monitoring pin of the corresponding one of the plurality of ICs in response to the control signal and the monitoring signal.

Abstract: A clock self-testing method and circuit. The clock self-testing method includes introducing a first clock signal and a second clock signal, counting cycles of the first clock signal and the second clock signal respectively beginning at the same moment, and if one of the number of cycles of the first clock signal being counted and the number of cycles of the second clock signal being counted is equal to N, determining whether the remained number of cycles is in a count range from M to N. If the remained number of cycles is out of the count range from M to N, the first clock signal and the second clock signal have errors.

Abstract: An LLC resonant converter includes a transformer, a switching half-bridge circuit, a resonant circuit, and a full-bridge rectifier. Both the switching half-bridge circuit and the full-bridge rectifier are on the same side of the transformer. The switching half-bridge circuit has a pair of switches, with one of the switches being connected to the output voltage node of the converter.

Abstract: A trans-inductor voltage regulator (TLVR) has regulator blocks and transformers. Secondary windings of the transformers are connected in series with a compensation inductor to form a trans-inductor loop, which is connected to the output voltage of the TLVR instead of to ground. Primary windings of the transformers serve as output inductors of the regulator blocks. The inductance of each output inductor and the output inductance of the TLVR are input to an averaging network of an averaging inductor direct current resistance (DCR) current sense circuit to generate an average sensed voltage. The average sensed voltage is converted to an average sensed current, which is used by a controller to generate control signals that drive the regulator blocks to generate the output voltage of the TLVR.