Abstract: A diode structure and a manufacturing method are disclosed. The diode structure includes a semiconductor substrate, a first semiconductor layer, a second semiconductor layer and an epitaxy layer. The semiconductor substrate includes a first surface. The first semiconductor layer and the second semiconductor layer are extended toward the interior of the semiconductor substrate from the first surface by implanting a dopant. Both of the semiconductor types of the first semiconductor layer and the second semiconductor layer are opposite to the semiconductor type of the semiconductor substrate. The epitaxy layer is formed on the first surface, connected with the first semiconductor layer and the second semiconductor layer and extended outwardly from the first surface. The first semiconductor layer and the second semiconductor layer are connected with each other, continuously.

Abstract: A manufacturing method of a gate structure includes steps of forming a mask oxide layer on the substrate, performing a photolithography process on the mask oxide layer and the substrate to form a trench, etching the trench, removing the mask oxide layer, forming a bottom oxide layer on a surface of the substrate and a trench surface of the trench, forming a silicon nitride layer on the trench, removing a part of the bottom oxide layer, removing the silicon nitride layer, forming a gate oxide layer on the surface and a part of the trench surface, and forming a poly layer on the trench. Therefore, the advantages of simplifying the gate structure process and reducing the production cost are achieved.

Abstract: A manufacturing method of a split gate structure includes steps of forming a mask oxide layer on the substrate, performing photolithography and etching on the mask oxide layer and the substrate, forming a trench, removing the mask oxide layer, forming a bottom oxide layer on a bottom part and a side wall of the trench and a surface of the substrate, forming a silicon nitride layer on the trench, removing a part of the bottom oxide layer, forming a gate oxide layer on part of the side wall and the surface, forming a gate poly layer on the trench, removing the silicon nitride layer, forming an inter-poly oxide layer on the gate poly layer, and forming a shield poly layer on the trench, thereby benefiting the increasing of the thickness of the inter-poly oxide layer, so that the advantages of improving the characteristics of the split gate structure are achieved.

Abstract: A MOSFET includes a substrate, a trench, a bottom oxide, a shield poly, two gate polys and an inter-poly oxide. The trench is formed on the substrate. The bottom oxide is formed on the trench. The shield poly is formed on the trench, and a part of the bottom oxide is separated by the shield poly. The two gate polys are formed on the bottom oxide. The inter-poly oxide is formed between the two gate polys. The shield poly is staggered from at least one of the two gate polys in a horizontal direction and a vertical direction. Therefore, the capacitance between a source electrode and a gate electrode is effectively reduced, and the delay time during switching is shorten and the energy loss is reduced at the same time.

Abstract: A transient-voltage-suppression diode structure and a manufacturing method thereof are disclosed. The structure includes a substrate, an N? type epitaxial layer, a first metal layer, a first N+ type implant layer, a deep N+ type implant layer and plural polycrystalline plugs. The N? type epitaxial layer is disposed on the substrate. The first metal layer is disposed on the N? type epitaxial layer to form a working-voltage terminal. The first N+ type implant layer spatially corresponding to the working-voltage terminal and embedded in the N? type epitaxial layer is connected with the working-voltage terminal. The deep N+ type implant layer spatially corresponding to the working-voltage terminal and embedded in the N? type epitaxial layer is spaced apart from the first N+ type implant layer at a separation distance. The plural polycrystalline plugs are connected between the working-voltage terminal of the first metal layer and the deep N+ type implant layer.

Abstract: A method for forming a shielded gate of a MOSFET includes steps as following: providing a semiconductor substrate having at least one trench, forming a bottom gate oxide region and a shielded gate poly region in the trench of the semiconductor substrate, forming an inter-poly oxide region on the shielded gate poly region through high temperature plasma deposition, poly etching back and oxide etching back; and forming a gate oxide region and a gate poly region on the inter-poly oxide region. By utilizing the etching back processes in replace of traditional chemical mechanical polishing processes, the manufacturing cost of manufacturing a shielded gate structure is reduced, and the total cost of manufacturing a FET is also reduced. Meanwhile, the gate charge is effectively reduced due to the shielded gate structure, so that the performance of a MOSFET is enhanced.

Abstract: A method for forming a shielded gate of a MOSFET includes steps as following: providing a semiconductor substrate having at least one trench, forming a bottom gate oxide region and a shielded gate poly region in the trench of the semiconductor substrate, forming an inter-poly oxide region on the shielded gate poly region through high temperature plasma deposition, poly etching back and oxide etching back; and forming a gate oxide region and a gate poly region on the inter-poly oxide region. By utilizing the etching back processes in replace of traditional chemical mechanical polishing processes, the manufacturing cost of manufacturing a shielded gate structure is reduced, and the total cost of manufacturing a FET is also reduced. Meanwhile, the gate charge is effectively reduced due to the shielded gate structure, so that the performance of a MOSFET is enhanced.

Abstract: A manufacturing method of a complementary metal oxide semiconductor includes steps as following: providing a semiconductor substrate; forming a metal oxide semiconductor region having an oxide layer, which has a thickness greater than 1 micrometer, on a first surface of the semiconductor substrate; forming the oxide layer as an isolation region of the metal oxide semiconductor region and a heat-isolation region of a poly heater; forming a poly gate of the metal oxide semiconductor region as at least a portion of the poly heater; forming an interlayer dielectric layer; and processing a selenium etching. Under this circumstance, the oxide layer is applied so as to be the isolation region of the metal oxide semiconductor region and a heat-isolation region of the poly heater, the poly gate of the metal oxide semiconductor region is sufficiently utilized as the poly heater, and the heat-dissipation of the poly heater is optimized.

Abstract: A method of fabricating a power semiconductor device includes the following steps. Firstly, a substrate is provided. A first epitaxial layer is formed over the substrate. A first trench is formed in the first epitaxial layer. A second epitaxial layer is refilled into the first trench. The first epitaxial layer and the second epitaxial layer are collaboratively defined as a first semiconductor layer. A third epitaxial layer is formed over the substrate, and a second trench is formed in the third epitaxial layer. A first doping region is formed in a sidewall of the second trench. An insulation layer is refilled into the second trench. The insulation layer, the first doping region and the third epitaxial layer are collaboratively defined as a second semiconductor layer. The power semiconductor device fabricated by the fabricating method can withstand high voltage and has low on-resistance.

Abstract: A manufacturing method of a power semiconductor includes steps of providing a first semiconductor substrate and a second semiconductor substrate, forming a metal oxide semiconductor layer on a first surface of the first semiconductor substrate, grinding a second surface of the first semiconductor substrate, forming a N-type buffer layer and a P-type injection layer on a third surface of the second semiconductor substrate through ion implanting, grinding a fourth surface of the second semiconductor substrate, and combining the second surface of the first semiconductor substrate with the third surface of the second semiconductor substrate for forming a third semiconductor substrate. As a result, the present invention achieves the advantages of enhancing the process flexibility and un-limiting the characteristics of the power semiconductor.

Abstract: A manufacturing method of a power semiconductor includes steps of providing a first semiconductor substrate and a second semiconductor substrate, forming a metal oxide semiconductor layer on a first surface of the first semiconductor substrate, grinding a second surface of the first semiconductor substrate, forming a N-type buffer layer and a P-type injection layer on a third surface of the second semiconductor substrate through ion implanting, grinding a fourth surface of the second semiconductor substrate, and combining the second surface of the first semiconductor substrate with the third surface of the second semiconductor substrate for forming a third semiconductor substrate. As a result, the present invention achieves the advantages of enhancing the process flexibility and un-limiting the characteristics of the power semiconductor.

Abstract: A process of manufacturing a solar cell is disclosed. The process comprises steps of (a) providing a semiconductor substrate, (b) forming a dielectric layer with amorphous silicon structure on the semiconductor substrate, (c) partially removing the dielectric layer with amorphous silicon structure to expose parts of the semiconductor substrate, (d) simultaneously forming a heavily doped region on a surface of the exposed semiconductor substrate and a lightly doped region on a surface of the unexposed semiconductor substrate using the dielectric layer with amorphous silicon structure as a translucent barrier layer, (e) removing the dielectric layer with amorphous silicon structure, (f) forming an anti-reflection coating on the semiconductor substrate, and (g) forming a first electrode on the anti-reflection coating and coupled with the heavily doped region.

Abstract: A solar cell includes a semiconductor substrate, an emitter layer, an anti-reflective coating, a first electrode, a second electrode, and a first light conversion layer. The emitter layer is formed on a light-receiving side of the semiconductor substrate. A p-n junction is formed between the emitter layer and the semiconductor substrate. The anti-reflective coating is formed on the emitter layer. The first electrode is connected to the emitter layer. The second electrode is formed on a back-lighted side of the semiconductor substrate. The first light conversion layer is formed on the anti-reflective coating. The first light conversion layer absorbs a first light with a first wavelength and emits a second light with a second wavelength, thereby performing a photoelectric converting operation.

Abstract: A process of manufacturing a solar cell is disclosed. The process comprises steps of (a) providing a semiconductor substrate, (b) forming a dielectric layer with amorphous silicon structure on the semiconductor substrate, (c) partially removing the dielectric layer with amorphous silicon structure to expose parts of the semiconductor substrate, (d) simultaneously forming a heavily doped region on a surface of the exposed semiconductor substrate and a lightly doped region on a surface of the unexposed semiconductor substrate using the dielectric layer with amorphous silicon structure as a translucent barrier layer, (e) removing the dielectric layer with amorphous silicon structure, (f) forming an anti-reflection coating on the semiconductor substrate, and (g) forming a first electrode on the anti-reflection coating and coupled with the heavily doped region.

Abstract: A method for fabricating a trench metal-oxide-semiconductor field effect transistor is disclosed. The method comprises steps of providing a substrate with an epitaxy layer thereon and etching the epitaxy layer to form a trench structure; forming a gate oxide layer on the surface of the epitaxy layer and the inner sidewalls of the trench structure and depositing a polysilicon layer to fill the trench structure; introducing a nitrogen gas and performing a driving-in procedure to form a body structure; performing an implantation procedure to form a source layer; forming a dielectric layer on the trench structure and the source layer; etching the dielectric layer and the source layer to define a source structure and form a contact region; filling the contact region with a contact structure layer; and forming a conductive metal layer on the contact structure layer and the dielectric layer.

Abstract: A method for manufacturing a selective emitter of a solar cell is provided. The method includes steps of providing a substrate; forming an emitter layer on the substrate, wherein the emitter layer has a heavily doped portion located on a top thereof and a relatively lightly doped portion located at a bottom thereof; forming a patterned mask layer on the emitter layer; and performing a wet etching for exposing a region of the relatively lightly doped portion which is not covered by the patterned mask layer.

Abstract: A fabrication method for forming a gate structure through an amorphous silicon layer includes providing a substrate layer, forming an amorphous silicon layer of a selected thickness on the substrate layer at a reaction temperature between about 520° C. and 560° C., and forming a doped amorphous silicon layer in a upper portion of the amorphous silicon layer at a reaction temperature between about 520° C. and 560° C.

Abstract: A solar cell includes a semiconductor substrate, an emitter layer, at least one emitter contact region and at least one first electrode. The emitter layer is formed on at least one surface of the semiconductor substrate. A p-n junction is formed between the emitter layer and the semiconductor substrate. The emitter contact region is formed on portions of the emitter layer and has the same type of dopant as the emitter layer. The emitter contact region has a higher dopant concentration than the emitter layer. The first electrode is coupled with the emitter contact region.

Abstract: A photovoltaic power device is provided. The photovoltaic power device includes a donor substrate, a first emitting substrate; a second emitting substrate, a first anti-reflection layer, a first metal electrode, a second metal electrode and a second anti-reflection layer. In the photovoltaic power device, the first and the second emitting substrate are disposed in the opposite sides of the donor substrate to generate two electronic flows, and the first metal electrode is insulated from the second metal electrode by the second anti-reflection layer.

Abstract: A method of forming films in a trench is applied to the manufacturing process of a power MOS device. In one embodiment, the method comprises providing a semiconductor substrate, forming a trench in the semiconductor substrate, forming a first dielectric layer on sidewalls of the trench, forming a second dielectric layer on the first dielectric layer, and forming a polysilicon layer in the trench. The method of forming films in a trench of the present invention can reduce or eliminate the thermal stress resulting from the different thermal expansion coefficients of different material layers after high temperature process.