Abstract: A power MOSFET layout according to one embodiment of the invention comprises a substrate and a plurality of cells. Each of the cells includes a base portion, a plurality of protruding portions extending from the base portion, and a plurality of photo-resist regions. Each of the cells is geometrically configured with the base portion and the plurality of protruding portions defining a closed cell boundary enclosing each of said cells. The cells are formed over the substrate, and the closed cell boundaries of the cells are arranged regularly with each other with no overlapping among the cells. The base portions are disposed in a matrix arrangement having rows and columns. The base portions are oriented from end to end in a direction of the columns and the protruding portions extend from the base portions along a direction of the rows. The photo-resist regions cover the base portions on the same column. None of the protruding portions are disposed between the base portions on the same column.

Abstract: Embodiments of the present invention are directed to providing a leakage detecting method for use in an oxidizing system of forming an oxide layer so as to shorten leakage detecting time period. In one embodiment, a leakage detecting method for use in an oxidizing system of forming an oxide layer comprises performing oxidizing processes on a plurality of test wafers in a plurality of test runs under a specified operating condition in an oxidizing system having an oxidizing chamber to form oxide layers on the test wafers having a plurality of oxide thicknesses for the plurality of test runs by flowing an oxidizing gas through the oxidizing chamber containing the test wafers. An oxygen concentration of the oxidizing gas exiting the oxidizing chamber is measured in each of the plurality of test runs.

Abstract: In a method of manufacturing MOSFET devices, and particularly to the trench-type MOSFET devices, embodiments of the present invention provide methods of forming bottom oxide layers having uniform thickness on the bottom of the trenches and avoiding undesired damage in the partial semiconductor substrate near the top of the trenches. In one embodiment, a method for manufacturing a trench-type MOSFET comprises providing a semiconductor substrate and forming a trench on the semiconductor substrate; forming a first oxide layer on a bottom and sidewalls of the trench and on the semiconductor substrate; forming a bottom anti-reflective coating (BARC) layer in the trench to cover the first oxide layer; forming a photoresist layer on the bottom anti-reflective coating layer; removing the photoresist layer; removing the bottom anti-reflective coating layer; and removing the first oxide layer on the sidewalls of the trench to form a bottom oxide layer on the bottom of the trench.

Abstract: A polishing system such as a chemical mechanical belt polisher includes a hydrostatic fluid bearing that supports polishing pads and incorporates one or more of the following novel aspects. One aspect uses compliant surfaces surrounding fluid inlets in an array of inlets to extend areas of elevated support pressure around the inlets. Another aspect modulates or reverses fluid flow in the bearing to reduce deviations in the time averaged support pressure and to induce vibrations in the polishing pads to improve polishing performance. Another aspect provides a hydrostatic bearing with a cavity having a lateral extent greater than that of an object being polished. The depth and bottom contour of cavity can be adjusted to provide nearly uniform support pressure across an area that is surrounded by a retaining ring support. Changing fluid pressure to the retaining ring support adjusts the fluid film thickness of the bearing.

Abstract: Embodiments of the present invention are directed to improving the reclamation rate of the waste water of wet benches in semiconductor fabrication. In accordance with an aspect of the invention, a method for improvement of water reclamation rate comprises choosing a rinse recipe for a wet bench. The wet bench is activated, and waste water quality of waste water produced by the rinse recipe from the wet bench is detected to generate water quality data for a plurality of reclamation switch time levels. The waste water is directed to a water reclamation system during a reclamation time period after each of the plurality of reclamation switch time levels. The water quality data of the waste water is analyzed for the plurality of reclamation switch time levels. The method further comprises determining from analyzing the water quality data the best reclamation switch time for the chosen rinse recipe for the wet bench.

Abstract: Embodiments of the present invention provide a developing method, which can efficiently prevent the developing solution from remaining on the backside surface of the wafer, so as to avoid the influence of the contamination on the subsequent processes. In one embodiment, a developing method comprises providing a wafer in a reaction space, wherein the wafer has an exposed photoresist thereon; coating a developing solution on a surface of the wafer; rotating the wafer; rinsing a normal surface and a backside surface of the wafer; and stopping rinsing the normal surface of the wafer while keeping rinsing the backside surface of the wafer for a specific time period.

Abstract: A method and structure are provided with reduced gate wrap around to advantageously control for threshold voltage and increase stability in semiconductor devices. A spacer is provided aligned to field dielectric layers to protect the dielectric layers during subsequent etch processes. The spacer is then removed prior to subsequently forming a part of a gate oxide layer and a gate conductor layer. Advantageously, the spacer protects the corner area o the field dielectric and also allows for enhanced thickness of the gate oxide near the corners.

Abstract: A statistical process control (SPC) method, wherein a post-stage process corresponds to a pre-stage process, is disclosed in the present invention. In one embodiment, the SPC method comprises: collecting a plurality of pre-stage measurements and post-stage measurements respectively during the pre-stage process and the post-stage process; evaluating an equation for approaching a relation between the plurality of post-stage measurements and the plurality of pre-stage measurements; calculating based on the equation a post-stage variance being independent of the fluctuation of the plurality of pre-stage measurements; and monitoring the post-stage process of mass production by an upper and a lower control limits, wherein the upper control limit is equal to the equation plus half order of the post-stage variance and the lower control limit is equal to the equation minus half order of the post-stage variance.

Abstract: Embodiments of the present invention are directed to a termination structure provided for a trench DMOS device to reduce occurrence of current leakage resulting from electric field crowding at the border of the active area and a method of manufacturing the same. In one embodiment, the termination structure for the trench DMOS device comprises a substrate of a first type conductivity and an epitaxial layer of the first type conductivity over the substrate. The epitaxial layer has a lower doping concentration than the substrate. A body region of a second type conductivity is provided within the epitaxial layer. A trench extends through the body region between an active area and an edge of the substrate. A gate oxide layer lines the trench and extends to the upper surface of the body region between the trench and the active area. A passivation layer is formed on the gate oxide layer, including sidewalls and a bottom surface of the trench.

Abstract: Embodiments of the invention provide a termination structure of DMOS device and a method of forming the same. In forming the termination structure, a silicon substrate with an epitaxial layer formed thereon is provided. A body region defined by doping the epitaxial layer is then selectively etched to form a plurality of DMOS trenches therein. Thereafter, a gate oxide layer is formed over exposed surfaces in the body region and a termination oxide layer is formed to encircle the body region. Afterward, a polysilicon layer is deposited over all the exposed surfaces, and then selectively etched to form a plurality of poly gates in the DMOS trenches and a polysilicon plate having an extending portion toward the body region over the termination oxide layer. By using the termination polysilicon layer as an implantation mask, sources are formed in the body region.

Abstract: A method for forming a trench having rounded corners in a semiconductor device comprises providing a substrate; forming a first pad oxide layer, a first silicon nitride layer, and a first oxide layer on the substrate sequentially; removing portions of the first oxide layer, the first silicon nitride layer, the first pad oxide layer, and the substrate to form at least one trench; and removing portions of the first oxide layer, the first silicon nitride layer, and the first pad oxide layer in the trench above an upper corner of the substrate in the trench. The substrate includes a lower corner at a bottom of the trench.

Abstract: One embodiment is directed to a method for trimming a rubber plate which is configured to be placed on a platform of an ion implanter, wherein the platform of the ion implanter includes a plurality of primary holes and a plurality of primary notches. The method comprises providing a template including a plurality of secondary holes corresponding to the plurality of primary holes of the platform of the ion implanter and a plurality of secondary notches corresponding to the plurality of primary notches of the platform of the ion implanter; and trimming the rubber plate using the template as a guide to form a plurality of tertiary holes in the rubber plate corresponding to the plurality of secondary holes of the template and to form a plurality of tertiary notches in the rubber plate corresponding to the plurality of secondary notches of the template.

Abstract: Embodiments of the present invention are directed to an improved method for forming dual oxide layers at the bottom of a trench of a substrate. A substrate has a trench which includes a bottom and a sidewall. The trench may be created by forming a mask oxide layer on the substrate; defining the mask oxide layer to form a patterned mask oxide layer and exposing a partial surface of the substrate to form a window; and using the patterned mask oxide layer as an etching mask to form the trench in the window. A first oxide layer is formed on the sidewall and the bottom of the trench of the substrate. A photoresist layer is formed on the substrate, filling the trench of the substrate. The method further comprises partially etching back the photoresist layer to leave a remaining photoresist layer in the trench. The height of the remaining photoresist layer is lower than the depth of the trench. A curing treatment of the remaining photoresist layer is performed after the partial etching.

Abstract: To fabricate a semiconductor memory, one or more pairs of first structures are formed over a semiconductor substrate. Each first structure comprises (a) a plurality of floating gates of memory cells and (b) a first conductive line providing control gates for the memory cells. The control gates overlie the floating gates. Each pair of the first structures corresponds to a plurality of doped regions each of which provides a source/drain region to a memory cell having the floating and control gates in one or the structure and a source/drain region to a memory cell having floating and control gates in the other one of the structures. For each pair, a second conductive line is formed whose bottom surface extends between the two structures and physically contacts the corresponding first doped regions. In some embodiments, the first doped regions are separated by insulation trenches. The second conductive line may form a conductive plug at least partially filling the region between the two first structures.

Abstract: Embodiments of the present invention are directed to a termination structure provided for a trench DMOS device to reduce occurrence of current leakage resulting from electric field crowding at the border of the active area and a method of manufacturing the same. In one embodiment, the termination structure for the trench DMOS device comprises a substrate of a first type conductivity and an epitaxial layer of the first type conductivity over the substrate. The epitaxial layer has a lower doping concentration than the substrate. A body region of a second type conductivity is provided within the epitaxial layer. A trench extends through the body region between an active area and an edge of the substrate. A gate oxide layer lines the trench and extends to the upper surface of the body region between the trench and the active area. A passivation layer is formed on the gate oxide layer, including sidewalls and a bottom surface of the trench.

Abstract: To fabricate a semiconductor memory, one or more pairs of first structures are formed over a semiconductor substrate. Each first structure comprises (a) a plurality of floating gates of memory cells and (b) a first conductive line providing control gates for the memory cells. The control gates overlie the floating gates. Each pair of the first structures corresponds to a plurality of doped regions each of which provides a source/drain region to a memory cell having the floating and control gates in one or the structure and a source/drain region to a memory cell having floating and control gates in the other one of the structures. For each pair, a second conductive line is formed whose bottom surface extends between the two structures and physically contacts the corresponding first doped regions. In some embodiments, the first doped regions are separated by insulation trenches. The second conductive line may form a conductive plug at least partially filling the region between the two first structures.

Abstract: A DMOS device having a trench bus structure thereof is introduced. The trench bus structure comprises a field oxide layer formed on a P substrate, and a trench extending from an top surface of the field oxide layer down to a lower portion of the P substrate. A gate oxide layer and a polysilicon bus are formed to fill the trench as a main portion of the bus structure. In addition, an isolation layer and a metal line are formed atop the polysilicon bus and the field oxide layer. An opening is formed in the isolation layer to form connections between the polysilicon bus and the metal line. In specific embodiments, the bus trench and the gate trenches of the DMOS device are formed simultaneously, and the polysilicon bus and the gate electrode are formed simultaneously as well. Therefore, the bus structure is able to form the DMOS transistor without demanding any lithographic step for defining the position of the polysilicon bus.

Abstract: Embodiments of the present invention relate to a method for preventing gate oxide thinning in a recess LOCOS process. The plurality of trenches are separated by a patterned pad oxide and a patterned silicon nitride layer The patterned silicon nitride layer and the patterned pad oxide layer are removed to expose a surface of the substrate as an active area of the semiconductor device. An ion drive-in to the active area on the substrate is performed by directing a flow of oxygen and nitrogen toward the substrate at a predetermined temperature and with a sufficient amount of oxygen to at least substantially prevent silicon nitride from forming on the field oxide regions. The method further comprises forming a sacrificial oxide layer on the active area, removing the sacrificial oxide layer to expose the active area, and forming a gate oxide layer on the active area.

Abstract: Embodiments of the present invention are directed to a method of forming a bottom oxide layer in the trench in semiconductor devices, such as Double-Diffused Metal-Oxide Semiconductor (DMOS) devices. In one embodiment, a method of forming a bottom oxide layer in a trench structure comprises providing a semiconductor substrate; forming a silicon nitride layer on the semiconductor substrate; forming a first oxide layer on the silicon nitride layer; forming a trench structure in the semiconductor substrate; forming a second oxide layer on a bottom and sidewalls of the trench and on a surface of the first oxide layer; removing the first oxide layer and the second oxide layer on the surface of the silicon nitride layer; and removing the second oxide layer on the sidewalls of the trench and a portion of the second oxide layer on the bottom of the trench.

Abstract: An applying method for an adhesive according to an embodiment includes the following steps. First, gas is exhausted from a first exhaust pipe, so as to eliminate a part of the gas in a closed container. Next, the gas continues to be exhausted from the first exhaust pipe, so as to have the adhesive in the transmission pipeline become bubbled, and also to convey the bubbled adhesive to reach the supply vent. Later, gas is exhausted from the second exhaust pipe and continues to be exhausted from the first exhaust pipe, so as to greatly exhaust the gas in the closed container, and also to increase bubbling in the adhesive. Subsequently, the gas continues to be exhausted from the second exhaust pipe and ceases to be exhausted from the first exhaust pipe, so as to cause the adhesive to reach a gasified state. Also the gasified adhesive is supplied to the closed container from the supply vent, so that the gasified adhesive can adhere to and coat above the SiO2 layer.