Abstract: A cobalt silicide fabrication process entails first depositing a cobalt layer (120) on a silicon-containing EPROM region. A titanium layer (130) is formed over the cobalt layer by ionized physical vapor deposition (“IPVD”) to protect the cobalt layer from contaminant gases. Cobalt of the cobalt layer is reacted with silicon of the EPROM region to form a cobalt silicide layer (210) after which the titanium layer and any unreacted cobalt are removed. Use of IPVD to form the titanium layer by improves the step coverage to produce a better cobalt silicide layer.

Abstract: Embodiments of the invention relate to a fabrication method of an electronic device, more particularly to a fabrication method of a power device in which an oxide layer at the bottom of the trench is provided to reduce Miller capacitance and further reduce RC delay. In one embodiment, a method for forming an oxide layer at the bottom of a trench comprises providing a first substrate with at least one trench therein; forming a first oxide layer on the bottom and sidewalls of the trench; removing the first oxide layer at the bottom of the trench; and forming a second oxide layer at the bottom of the trench.

Abstract: A memory such as a flash EPROM contains writing circuitry (58 and 60) that adjusts how much current or/and voltage is provided to a writing conductor (92) connected to the memory cells (50) of a cell group for simultaneously writing the bits of a bit group such as a word or byte into the cells of that cell group as a function of how many of those bits are in one of a pair of opposite logic states.

Abstract: Embodiments of the present invention are directed to a method of forming a bottom oxide layer in the trench in semiconductor devices, such as Double-Diffused Metal-Oxide Semiconductor (DMOS) devices. In one embodiment, a method of forming a bottom oxide layer in a trench structure comprises providing a semiconductor substrate; forming a silicon nitride layer on the semiconductor substrate; forming a first oxide layer on the silicon nitride layer; forming a trench structure in the semiconductor substrate; forming a second oxide layer on a bottom and sidewalls of the trench and on a surface of the first oxide layer; removing the first oxide layer and the second oxide layer on the surface of the silicon nitride layer; and removing the second oxide layer on the sidewalls of the trench and a portion of the second oxide layer on the bottom of the trench.

Abstract: A method of forming films in a trench is applied to the manufacturing process of a power MOS device. In one embodiment, the method comprises providing a semiconductor substrate, forming a trench in the semiconductor substrate, forming a first dielectric layer on sidewalls of the trench, forming a second dielectric layer on the first dielectric layer, and forming a polysilicon layer in the trench. The method of forming films in a trench of the present invention can reduce or eliminate the thermal stress resulting from the different thermal expansion coefficients of different material layers after high temperature process.

Abstract: In order to use an etching solution of less complicated composition for recovering used wafers, embodiments of the present invention provide a recovering method, and also provide a kind of wafer, which is used as a process control wafer or dummy wafer, and fabrication methods. In one embodiment, a wafer-recovering method comprises providing a first wafer, wherein the first wafer has a base, a first conductive layer on the base, and a second conductive layer on the first conductive layer. The method further comprises removing the first and second conductive layers with an acidic solution to obtain a second wafer; and washing the second wafer with a liquid. The second conductive layer is formed on the first conductive layer in a deposition process, and the first conductive layer is more easily removed by the acidic solution than the second conductive layer.

Abstract: A shallow junction that previously would require the use of a low-energy ion implanter can be directly formed by high-energy or middle-energy ion implanters such that the manufacturer need not purchase a new low-energy ion implanter. In one embodiment, an ion-implantation method for forming a shallow junction comprises providing a semiconductor substrate including at least one transistor structure. During ion implantation to form a shallow junction, a buffer layer is formed on the implantation region. The buffer layer has a predetermined thickness. Charged ions are implanted into the implantation region through the buffer layer by an energy provided by a middle-energy ion implanter, and the buffer layer is removed. The buffer layer is used for blocking the amount of the charged ions that will be implanted into the implantation region so as to form a shallow junction that would require a low-energy ion implanter without the buffer layer.

Abstract: Embodiments of the present invention provide a method for reclaiming and reusing a wafer. In one embodiment, a method for reclaiming a wafer comprises providing a used, nonproductive wafer having a semiconductor substrate and a polysilicon layer formed on the semiconductor substrate; oxidizing a first part of the polysilicon layer to form a first oxide layer; removing the first oxide layer; and oxidizing a second part of the polysilicon layer to form a second oxide layer on the used wafer which is to be used as a reclaimed wafer. The nonproductive wafer is used to improve the quality of a deposition process of the polysilicon layer on one or more productive wafers.

Abstract: A mask, the layout thereon and the method therefore are provided. In one embodiment, a mask layout structure comprises a plurality of unit patterns, wherein each unit pattern comprises a plurality of angle portions, and each angle portion has an extending portion extended outwardly therefrom. The mask can be used for defining the pattern of the photoresist layer before the ion implantation process. The use of the make layout structure not only avoids the lifting of the photoresist layer in the ion implantation process, but also produces outstanding features in the field of power devices. The mask can be used in the fabrication of power devices, especially in the fabrication of sources of trench power devices.

Abstract: A wafer and the manufacturing and reclaiming methods thereof are disclosed. The wafer includes a semiconductor substrate and a protective layer formed on the surface of the semiconductor substrate. The reclaiming method of the wafer includes providing a wafer having a semiconductor substrate, a protective layer formed on the semiconductor substrate, and a polysilicon layer formed on the protective layer; and removing the polysilicon layer. The wafer and the reclaiming method of the wafer can prevent the substrate of the wafer from being destroyed during the reclaiming process and increase the reclaiming rate of the wafer.

Abstract: In a method of manufacturing MOSFET devices, and particularly to the trench-type MOSFET devices, embodiments of the present invention provide methods of forming bottom oxide layers having uniform thickness on the bottom of the trenches and avoiding undesired damage in the partial semiconductor substrate near the top of the trenches. In one embodiment, a method for manufacturing a trench-type MOSFET comprises providing a semiconductor substrate and forming a trench on the semiconductor substrate; forming a first oxide layer on a bottom and sidewalls of the trench and on the semiconductor substrate; forming a bottom anti-reflective coating (BARC) layer in the trench to cover the first oxide layer; forming a photoresist layer on the bottom anti-reflective coating layer; removing the photoresist layer; removing the bottom anti-reflective coating layer; and removing the first oxide layer on the sidewalls of the trench to form a bottom oxide layer on the bottom of the trench.

Abstract: Chemical-mechanical polishing (“CMP”) processes performed on bodies (10), each having areas (16 and 18) of different depression pattern densities, are compared by correlating polishing data accumulated, for one such body, on an area (16) of one pattern density to polishing data accumulated, for that body, on an area of another pattern density for each of the CMP processes.

Abstract: Embodiments of the present invention are directed to a termination structure provided for a trench DMOS device to reduce occurrence of current leakage resulting from electric field crowding at the border of the active area and a method of manufacturing the same. In one embodiment, the termination structure for the trench DMOS device comprises a substrate of a first type conductivity and an epitaxial layer of the first type conductivity over the substrate. The epitaxial layer has a lower doping concentration than the substrate. A body region of a second type conductivity is provided within the epitaxial layer. A trench extends through the body region between an active area and an edge of the substrate. A gate oxide layer lines the trench and extends to the upper surface of the body region between the trench and the active area. A passivation layer is formed on the gate oxide layer, including sidewalls and a bottom surface of the trench.

Abstract: An OXO-type inter-poly insulator (where X is a high-K metal oxide and O is an insulative oxide) is defined by forming an amorphous metal oxide layer on a silicon-based insulator (e.g., a silicon oxide layer) and then nitridating at least upper and lower sub-layers of the amorphous metal oxide with a low temperature plasma treatment that maintains temperature below the recrystallization temperature of the amorphous material. Such a plasma treatment has been found to improve breakdown voltage characteristics of the insulator. In one embodiment, the metal oxide includes aluminum oxide and it is fluorinated with low temperature plasma prior to nitridation.

Abstract: Embodiments of the present invention are directed to providing a leakage detecting method for use in an oxidizing system of forming an oxide layer so as to shorten leakage detecting time period. In one embodiment, a leakage detecting method for use in an oxidizing system of forming an oxide layer comprises performing oxidizing processes on a plurality of test wafers in a plurality of test runs under a specified operating condition in an oxidizing system having an oxidizing chamber to form oxide layers on the test wafers having a plurality of oxide thicknesses for the plurality of test runs by flowing an oxidizing gas through the oxidizing chamber containing the test wafers. An oxygen concentration of the oxidizing gas exiting the oxidizing chamber is measured in each of the plurality of test runs.

Abstract: Embodiments of the present invention provide a developing method, which can efficiently prevent the developing solution from remaining on the backside surface of the wafer, so as to avoid the influence of the contamination on the subsequent processes. In one embodiment, a developing method comprises providing a wafer in a reaction space, wherein the wafer has an exposed photoresist thereon; coating a developing solution on a surface of the wafer; rotating the wafer; rinsing a normal surface and a backside surface of the wafer; and stopping rinsing the normal surface of the wafer while keeping rinsing the backside surface of the wafer for a specific time period.

Abstract: A method for monitoring an ion implanter is disclosed. In one embodiment, the method comprises providing a wafer, forming a barrier layer on the surface of the wafer wherein the barrier layer has a substantial blocking effect on ion implantation, performing an ion implantation process to the wafer, performing a thermal treatment process, removing the barrier layer, and measuring a physical property of the wafer. The measured physical property of the wafer can be used to ascertain the status of the ion implanter. For instance, the measured physical property can be used to determine whether the ion implanter has problems when the energy or concentration of the implanted ions is changed.

Abstract: A mask applied in the process of miniaturizing a structural device is disclosed. The mask comprises a plurality of layout pattern areas for defining layers of the structural device, wherein at least one layout pattern area is arranged on the mask in a regular rule. A method for exposure is also disclosed. First, a mask comprising a plurality of layout pattern areas for defining layers of the structural device is provided, wherein at least one layout pattern area is arranged on the mask in a regular rule. Then one of the layout pattern areas is selected and the other layout pattern areas are covered. Finally, the mask is aligned with a substrate and the exposure is performed to transfer the pattern of the selected layout pattern area to the substrate.

Abstract: In a nonvolatile memory cell, the floating gate (160) has an upward protruding portion. This portion can be formed as a spacer over a sidewall of the select gate (140). The spacer can be formed from a layer (160.2) deposited after the layer (160.1) which provides a lower portion of the floating gate. Alternatively, the upward protruding portion and the lower portion can be formed from the same layers or sub-layers all of which are present in both portions. The control gate (170) can be defined without photolithography. Other embodiments are also provided.

Abstract: The present invention provides a method and a set of trimming accessories for trimming rubber plate used in an ion implanter. The rubber plate is suitable for use in an ion implanter, wherein the ion implanter has a platform with multiple primary holes and multiple primary notches. In specific embodiments, the set of trimming accessories includes trimming equipment such as a knife or preferably a laser; a template with secondary holes corresponding to primary holes and secondary notches corresponding to primary notches. The template is used as a guide to form a plurality of tertiary holes in the rubber plate corresponding to the plurality of secondary holes of the template and to form a plurality of tertiary notches in the rubber plate corresponding to the plurality of secondary notches of the template.