Abstract: A method and apparatus for filtering a slurry used in a chemical mechanical polishing apparatus is disclosed. Magnets are provided along the piping network between a slurry reservoir and the CMP apparatus. A magnet may also be placed adjacent to the slurry reservoir to prevent iron oxide particles from traveling with the slurry to the CMP apparatus. The magnets attract iron oxide particles from the slurry and remove those particles from the slurry prior to polishing. This reduces the amount of defects caused by the iron oxide particles in the slurry.

Abstract: A wafer-fetching sensing device for wafer storage apparatus uses a planar detection means to replace a conventional linear detection means to detect if a wafer is properly positioned at a desirable access level before being moved out of an access opening of the wafer storage apparatus by a robot. Wafer tilting and damage incident that might otherwise happen thus may be avoided. Only a correctly positioned wafer will be fetched. A warning signal will be generated when the wafer is not properly positioned so that preventive action may be taken to avoid wafer damage. Production yield thus may be increased.

Abstract: A method for forming a Trench Mask ROM cell comprises the steps of: Providing a substrate doped lightly with p-type dopant; forming plural trenches and then, forming a gate layer on each trench, further, implanting n+-type ions on substrate beneath the gate oxide layer on bottom of each trench and position between each two adjacent trench; and then, forming a nitride layer on the gate oxide layer; forming an oxide layer on the nitride layer and each trench being filled with the oxide layer; and removing the oxide layer and the nitride layer of partial trenches, namely, partial trenches reserving the oxide and the nitride layer to define coding regions of the Trench Mask ROM cell; finally, depositing a polysilicon layer on the top surfaces of the substrate wherein the polysilicon being word line of the Trench Mask ROM cell.

Abstract: A method for manufacturing a capacitor includes the steps of a) forming a sacrificial layer over the etching stop layer, b) partially removing the sacrificial layer, the etching stop layer, and the dielectric layer to form a contact window, c) forming a first conducting layer over the sacrificial layer and in the contact window, d) partially removing the first conducting layer and the sacrificial layer to expose a portion of the sacrificial layer and retain a portion of the first conducting layer, e) forming a second conducting layer over top surfaces and sidewalls of the portion of the first conducting layer and the portion of the sacrificial layer, and f) partially removing the second conducting layer while retaining a portion of the second conducting layer alongside the portion of the first conducting layer and the portion of the sacrificial layer, and removing the portion of the sacrificial layer to expose the etching stop layer and construct a capacitor plate with a generally cross-sectionally modified T

Abstract: The invention has disclosed a method for forming a multi-cylinder capacitor with simplified steps. First, first and second insulating layers are sequentially formed on a semiconductor substrate. Next, an alternate polysilicon layer is deposited. The alternate polysilicon layer includes a plurality of undoped polysilicon films alternating with a plurality of doped polysilicon films. Thereafter, a portion of said plurality of doped polysilicon films is selectively etched by utilizing the etching selectivity between said plurality of undoped and doped polysilicon films. Finally, the second insulating layer is removed and the undoped polysilicon films are doped to form multi-cylinder electrodes. According to the invention, the reliability of the multi-cylinder capacitor is improved and the cost of production is reduced. In addition, it is not necessary to add other steps if the number of cylindrical electrodes increases.

Abstract: A method for fabricating deep-submicron vertically arranged capacitors is disclosed which allows the capacitor to enjoy an enhanced sidewall surface so as to attain a capacitance of 40 pF or more.

Abstract: A process for fabricating a semiconductor device comprising a gate electrode, a raised source, a raised drain and an interconnect inlaid into an isolation region.

Abstract: An object of the present invention is to provide a method for accurately determining a swing curve in the &mgr;m order's semiconductor technology. Photoresist films with different thicknesses are coated on silicon dummy wafers, respectively. Using a mask with a critical dimension bar's pattern, each of the chips of the silicon dummy wafers is exposed by different exposure doses such that the pattern is transferred on each of the chips. After the silicon dummy wafers are developed, each of the chips of the silicon dummy wafers is inspected by using a scanning electron microscope. For each of the silicon dummy wafers, the exposure dose resulting in completely removing the photoresist film on the region between the adjacent critical dimension bars of the pattern by developing is recorded. According to the present invention, it is easy to obtain an accurate swing curve since the resolution of the scanning electron microscope is up to the order of &mgr;m.

Abstract: A method used in some step of processing for ashing a photoresist resin film of a semiconductor wafer is disclosed. Generally the present method will conclude the following steps. Firstly adjusting Etch-Module-Asher endpoint is carried out. Then placing the substrate coated with the resist film in a vacuum chamber will be achieved. The next step is that positing silicon wafer into asher through the vacuum chamber having a wafer holding-set plate, it is for closely receiving and orderly stepped ranking the wafer. Here, the silicon wafer is pushed to the chamber. Finally, the last process is that adjusting second Etch-Module-Asher Endpoint. Simultaneously ashing the resist film by an oxygen plasma is carried out while heating the substrate to remove the resist film, therefore photoresist is peeled up a first end of the silicon wafer and the silicon wafer is cleaned up and the other end of the silicon wafer.

Abstract: A method for manufacturing a semiconductor device having an excellent metallization is provided. The method includes the steps of a) providing a semiconductor substrate, b) forming a conductive layer on the semiconductor substrate, c) forming a dielectric layer on the conductive layer, d) forming a titanium nitride layer directly on the dielectric layer without contacting the conductive layer, and e) patternizing the titanium nitride layer, the dielectric layer and the conductive layer, wherein the dielectric layer is used for avoiding spontaneous electrochemical reaction between the titanium nitride layer and the conductive layer.

Abstract: A non-volatile programmable latch (210) has a fuse (F1) connected between a non-ground voltage terminal (212) and an output terminal (OUT). A NMOS transistor (110) is connected between the output terminal and ground. An inverter (120) has an input connected to the output terminal and an output connected to the gate of the NMOS transistor. A diode connects the output terminal to the non-ground voltage terminal (212) to prevent a charge build up on the output terminal when the power is off.

Abstract: The present invention relates to a shallow trench isolation method of a semiconductor wafer for filling dielectric material in each shallow trench between components on the surface of the semiconductor wafer to isolate the components electrically and prevent dishing when the chemical-mechanical polishing is performed on the surface of dielectric material in each shallow trench.

Abstract: A process for forming a contact structure of a semiconductor device includes the steps of (a) providing a substrate having a plurality of gates thereon and a first oxide layer formed between the gates, (b) forming a first dielectric layer on the oxide layer and the gates, (c) forming a second oxide layer on the first dielectric layer, and (d) removing a portion of the second oxide layer for forming first spacers alongside each of the gates.

Abstract: A method for forming the gate electrode in an integrated circuit, in which a cap silicon nitride layer is deposited in a two step process to improve the condition of silicon nitride residue remaining on the surface of tungsten silicide. First, a layer of polysilicon and a layer of tungsten silicide are sequentially formed on the semiconductor substrate, subsequently, a thin film of silicon nitride is formed at a first temperature and a second silicon nitride is formed at a second temperature, then the pattern of the contact window of gate is defined and the first etching is performed to remove the second and the second silicon nitride, finally, the second etching is performed to remove the layers of polysilicon and tungsten silicide to form a gate electrode.

Abstract: A method for making conductive plugs in a semiconductor wafer. In involves the steps of: (a) forming at least one through hole in a dielectric layer, which is formed above a conductive substrate; (b) subjecting the wafer to a NH4OH/H2O2 wet washing process and HCl/H2O2 wet washing process; (c) drying the wafer; (d) subjecting the wafer to a dilute hydrogen fluoride or buffered hydrogen fluoride wet washing process to remove the native oxide layer that maybe formed on the conductive substrate; (e) drying the wafer again; and (i) filling the at least one through hole with a conductive material to form at least one conductive channel. The wet washing station is modified such that the wet washing processes and the drying process are performed in the same station and without removing the wafer from the washing station during the wet washing and drying process.

Abstract: A method of forming a shallow trench isolation on a substrate is disclosed. The method comprises: forming a pad oxide layer on the substrate; forming a dielectric layer on the pad oxide layer; forming at least one trench in the substrate; forming an oxide liner along the walls and bottom of the trench, the oxide liner formed from a UV/O3 process; and forming a CVD oxide layer for isolation atop the oxide liner and within the trench.

Abstract: A method of forming field isolation regions (300) on a semiconductor substrate for an integrated circuit. The present method includes forming a sandwich type structure as an oxidation mask (140), (160), and (200). The present sandwich type structure includes an underlying oxide layer (120) formed overlying the top surface. The present sandwich type structure includes a polysilicon layer (140) overlying the oxide layer (120), a first silicon nitride layer (160) overlying the polysilicon layer (140), and a second silicon nitride layer (200) overlying the first silicon nitride layer (160) where the second silicon nitride layer (200) is much thicker than the first layer of silicon nitride (160). The present method also includes patterning the second silicon nitride layer (200), the first silicon nitride layer (160), and the polysilicon layer (140) to define an oxidation mask.

Abstract: A testing apparatus has a load board and a device under test electrically interconnected with the load board. A pressure jig, which has a forcing unit and a structural member for fixing a fixed portion of the forcing unit with respect to the load board, also has a pressure actuating component moveable with respect to the fixed portion of the forcing unit. The pressure actuating component contacts the device under test. The apparatus may include a probe that contacts a terminal of the device under test for monitoring the signal state of the terminal as the device under test interacts with the load board.

Abstract: An improved process of fabricating a shallow trench isolation structure is provided. A semiconductor substrate is provided and an insulating layer is formed over the substrate. A nitride masking layer is formed over the insulating layer. The nitride masking layer and the insulating layer are patterned and etched to expose a portion of the substrate, and to expose edges of the nitride masking layer and the insulating layer. The exposed portion of the substrate substantially defines boundaries of the isolation structure. A first oxide layer is deposited superjacent the exposed portion of the substrate, and over the nitride masking layer. A removing step includes removing portions of the first oxide layer lying over the nitride masking layer, a central portion of the first oxide layer superjacent the substrate, and a portion of the substrate to form a trench, leaving an oxide spacer disposed between the exposed edges of the nitride masking layer and the insulating layer, and the edge of the trench.

Abstract: A dual-gate cell structure with self-aligned gates. A polysilicon spacer forms a second gate (213) separated from a first gate (201), which is also polysilicon, by a dielectric layer (207). A drain region (219) and a source region (221) are formed next to the gates. In one embodiment, the second gate (213) acts as a floating gate in a flash cell. The floating gate may be programmed and erased by the application of appropriate voltage levels to the first gate (201), source (221), and/or drain (219). The self-aligned nature of the second gate (213) to the first gate (201) allows a very small dual-gate cell to be formed.