Abstract: A structure for connecting fluid channel of fluid delivery system is disclosed. This connecting structure limits the length of the flow-guiding pipe extending into the delivery channel, to reduce particle contaminates and the probability of crack. The present pipe union connecting structure comprises a first pipe, a second pipe mounted to the first pipe, and an inner pipe extending from the first pipe into the second pipe with a certain extending length. The extending length of the inner pipe is less than the proportion of the minimum distance between the inner wall of the second pipe and the outlet of the inner pipe when standstill, to the tangent value of a certain angle &thgr;, which is the maximum inclined angle between the second pipe and the inner pipe.

Abstract: A method for polysilicon etching with HBr, He and He/O2 as reactive gas source is disclosed. A chamber pressure greater than 30 mTorr is held to achieve high selectivity to polysilicon over silicon oxide. A total flow rate of HBr and He greater than 420 sccm is provided. Under this condition of the total flow rate of HBr and He, the flow rates of HBr and He are respectively held in the range of about 180-280 sccm, and the flow rate of He/O2 is at about 5-10 sccm.

Abstract: A novel insulating apparatus for a conductive line is disclosed. The proposed insulating apparatus can be applied to various conductive lines with different shapes. The problem of short circuit can be solved by the present insulating apparatus with the novel connecting configuration. The present invention comprises a plurality of insulator rings worn on the conductive line in series, wherein the insulator rings are annular cylinders. Each of the annular cylinders has an outer diameter larger than the inner diameter of the ones next to it. In addition, each of the annular cylinders has a length sized according to the desired flexibility of the conductive line.

Abstract: A method of fabricating deep trench capacitors of high density Dynamic Random Access Memory (DRAM) cells is disclosed: first, providing a semiconductor substrate, and then forming a trench on the semiconductor substrate; sequentially forming a capacitor dielectric layer, a first polysilicon storage node, dielectric collars and a second polysilicon stud inside the trench; performing two-step ion implantation to form shallow and deep strap regions on one side of the trench; forming a third polysilicon layer and an isolation layer overlaying the dielectric collars and second polysilicon stud inside the trench to complete a buried strap formation; and forming an access field effect transistor on the semiconductor substrate.

Abstract: A method of fabricating an IC device on a substrate comprising MOS transistors and other IC components. Each of the transistors of the IC device comprises a raised source electrode, a raised drain electrode, dual gate electrodes and self-aligned interconnect contact windows, and is connected to other transistors and other IC components through interconnects formed on top of such self-aligned contact windows.

Abstract: An apparatus and method to polish a wafer using abrasive flow machining (AFM) is provided. Under a high-pressure condition, the wafer is polished by flowing abrasive media with high viscosity, on the wafer in order to planarize the wafer. Therefore, the polishing efficiency is higher, and the attained roughness is lower than the conventional method. In addition, the selectivity of this method is lower.

Abstract: A probe card treatment method, which is applicable on a probe card comprising multiple probe needles, is described. A thermal treatment is conducted on the probe card by placing the probe card in a closed heating device, wherein the temperature of the thermal treatment is enough to restore the elasticity and the planarity of the probe needles without softening the probe card. The probe card and the probe needles thereon are then rapidly cooled by cool air such that the elasticity of the probe needles is retained and the lifetime of the probe needles is extended.

Abstract: The present invention discloses a piping system for etch equipment including an exhaust gas tube connected with an etching chamber for conveying exhaust gas out of the chamber. A cooling gas tube connected to the etching chamber allows cooling gas to flow around a back side of the wafer placed in the chamber for cooling the wafer's temperature. A cooling gas bypass tube connected between the cooling gas tube and the exhaust gas tube is used for regulating a gas flow in the cooling gas tube. Moreover, a plurality of heaters are set out of conjunctions of the cooling gas tube and cooling gas bypass tube with the exhaust gas tube so as to retard particle accumulation in the conjunctions of these tubes.

Abstract: A method and system is provided for determining the fail patterns of fabricated wafers in an automated WAT procedure. First, N test items are performed on selected samples from each lot of fabricated wafers, from which a total of N fail percentages are obtained respectively from the N test items. Next, the N fail percentages are formulated as an N-dimensional test-result vector, in which the (i)th element represents the fail percentage of the (i)th test item, for i=1 to N. Subsequently, an N×N conversion matrix is provided to convert the N-dimensional test-result vector into an N-dimensional fail-pattern vector with fail patterns as a basis. In this fail-pattern vector, the (j)th element represents the percentage of the (j)th fail pattern, for j=1 to N. By the method and system, the results from the WAT procedure can be extended to all the fabricated wafers in the lot.

Abstract: A method of planarizing a layer of dielectric material is disclosed herein that is particularly suitable for planarizing inter-layer-dielectrics (ILD) or inter-metal-dielectrics (IMD). The planarizing method comprises the steps of depositing a layer of sacrificial oxide over the dielectric material, depositing a layer of amorphous silicon over the sacrificial oxide layer by either sputtering or plasma enhanced chemical vapor deposition (PECVD) at a temperature less than about 500 degrees Celsius, performing a first chemical-mechanical polishing of the amorphous silicon layer to form a self-aligned mask for a subsequent etching step, etching a portion of the sacrificial oxide layer to form a channel therein, and performing a second chemical-mechanical polishing to remove the remaining amorphous silicon layer and the remaining sacrificial oxide, and to substantially planarize the underlying dielectric material.

Abstract: A method for preventing corrosion and particulate in a load-lock chamber is disclosed. The load-lock chamber is adjourning with an etching chamber and a wafer transferred module, each time a wafer in the cassette is transferred into the etching chamber for etching by a transfer arm. After that, the etched wafer is withdrawn by the same way to the cassette. The load-lock chamber comprising an outlet of N2-purge tube therein for venting the vacuum in the load-lock chamber to the surrounding. The method comprising at least a step of coupling heating means to the N2-purge tube, or heating N2 gases before injecting into the N2-purge tube so that the temperature of the N2-purge tube will at least not lower than the temperature of an environment within the load-lock chamber.

Abstract: The present invention provides a method of forming trench capacitor with a sacrificial silicon nitride. A deep trench structure is formed in a substrate. A TEOS oxide layer is formed on the substrate and filled in said trench region, etched to a first level subsequently, wherein a portion of the TEOS oxide layer is remained in the trench region and a portion of the substrate exposed to form a trench sidewall. A thermally oxidation process is performed to form a collar oxide on the exposed substrate. A silicon nitride sidewall is formed on the collar oxide, then removing the residual TEOS oxide layer by wet etching. The trench region is then etched using the silicon nitride sidewall as a barrier to form a bottle shape trench region for increasing the surface of the trench region. A bottom cell plate is formed in the fresh trench region. The silicon nitride sidewall is removed.

Abstract: The present invention provides a CMP device with a pressure-controlling mechanism comprising a rotating polishing plate, a slurry supplying system for supplying slurry, a rotating carrier that holds and rotates a silicon wafer such that the wafer surface is polished against the rotating polishing plate and the slurry during a CMP process, and a pressure-controlling mechanism capable of exerting different pressures to different locations on the wafer in response to different polishing rates corresponding to each of the specified locations. By utilizing the CMP device according to the present invention, the polishing rate and finish quality at different locations of the silicon wafer will be more uniform, which in turn contributes to an improved wafer planarizing effect.

Abstract: A dynamic random access memory (DRAM) integrated circuit (10). The DRAM (10) includes a recessed region (20) defined in a semiconductor substrate (22). This recessed region has substantially vertical sides (34) extending from a bottom surface (32). A field effect transistor (18) is defined adjacent to the recessed region (20). A capacitor structure, including a lower capacitor plate (26), a capacitor dielectric (28), and an upper capacitor plate (30), is defined in the recessed region (20) and over the field effect transistor (18), thereby providing a greater capacitor surface.

Abstract: An improved wafer polishing machine is disclosed. In one embodiment, the wafer polishing machine has a movable polishing surface and a holder that holds an object, such as a semiconductor wafer, against the movable polishing surface. The holder includes a support structure that supports the object in contact with the polishing surface and an annular retaining ring that retains the object in alignment with the support structure. The retaining ring has a plurality of projections projecting inwardly from its inner circumference. The projections are evenly spaced around the inner circumference of the retaining ring. In one embodiment, the projections on the retaining ring define a circle with a diameter no less than the diameter of the object being polished. In an alternative embodiment, the retaining ring has a smooth, circular inner circumference formed from a flexible material which distends to from a continuous arc of contact with the wafer during polishing.

Abstract: A method for forming a concave bottom oxide layer in a trench, comprising: providing a semiconductor substrate; forming a pad oxide layer on the semiconductor substrate; forming a silicon nitride layer on the pad oxide layer; etching the silicon nitride layer, the pad oxide layer and the semiconductor substrate to form the trench in the semiconductor substrate; depositing a silicon oxide layer to refill into the trench and cover on the silicon nitride layer, wherein the silicon oxide layer has overhang portions at corners of the trench; anisotropically etching the silicon oxide layer to form a concave bottom oxide layer in the trench; etching the silicon oxide layer to remove the silicon oxide layer on the silicon nitride layer and the sidewalls of the trench; removing the silicon nitride layer and the pad oxide layer.

Abstract: A non-volatile programmable latch (210) has a fuse (F1) connected between a non-ground voltage terminal (212) and an output terminal (OUT). A NMOS transistor (110) is connected between the output terminal and ground. An inverter (120) has an input connected to the output terminal and an output connected to the gate of the NMOS transistor. A diode connects the output terminal to the non-ground voltage terminal (212) to prevent a charge build up on the output terminal when the power is off.

Abstract: A method for determining a crack limit of a target film deposited on a wafer in production after a post annealing procedure is disclosed. The crack limit is determined by adopting and adjusting the thermal shrinkage rates of a plurality of target films deposited on bare wafers and annealed. The test results on bare wafers can be applied to the production wafers to prevent from film cracking and/or inspect instrumental conditions.

Abstract: A capped slit provides isolation between adjacent devices of an integrated circuit. The cap and slit provide very high immunity to punchthrough and protect the edge of the slit against becoming exposed during subsequent processing that could otherwise remove field oxide. In one embodiment, the capped slit isolates two cells of a flash EEPROM device, and the field oxide lines the slit and serves as the tunneling oxide in the cells. In another embodiment, the slit is filled with a plug of dielectric material.

Abstract: A reduced capacitance architecture for integrated circuits and particularly for memory integrated circuits is disclosed. The integrated circuit has a plurality of levels including first and second levels. A first signal conductor extends within the first level. A second signal conductor also extends within the first level and is positioned adjacent to and in close proximity with the first signal conductor. The second level is positioned adjacent to the first level and includes a third signal conductor extending within it. The third signal conductor is positioned laterally between the first and second conductors to eliminate vertical parallel plate capacitance.