Abstract: In a burst operation, a counter receives one or more bits of a starting column address. The count signal generated by the counter is provided to column decoders. The column decoders select two columns in response to a single value of the count signal. The two columns can be at non-consecutive column addresses. Alternatively, the two columns can be at consecutive column addresses starting at an odd column address boundary. Data are transferred between the two columns and a buffer in parallel. Data are transferred between the buffer and a data terminal serially. Some embodiments are suitable for burst operations defined by standards for synchronous dynamic random access memories.

Abstract: The present invention discloses a method to detect organic contamination in process environment of integrated circuits by using hemispherical-grain polysilicon layer that is formed in the process environment. The organic residue will contaminates the substrate which the hemispherical-grain polysilicon layer is formed thereon so as that the grain size of the polysilicon layer is between about 0.2 to 0.4 micrometers. The grain size of the hemispherical-grain polysilicon layer that is fabricated in a clean process environment is between about 0.5 to 0.8 micrometers. In other words, if organic contamination is residual in process environment, the grain size of the hemispherical-grain polysilicon layer that is fabricated in the process environment is smaller than a certain size to determine that the process environment is contaminated by organic contamination.

Abstract: This present discloses a method for making a concave bottom oxide within a trench, the steps comprising: providing a semiconductor substrate; forming an insulating layer on the semiconductor substrate; defining the insulating layer to form an opening exposing the surface of the semiconductor substrate; dry-etching the exposed semiconductor substrate within the opening by using the first insulating layer as an etching mask to form a trench; depositing a first oxide layer conformably over the insulating layer, the side-walls and the bottom of the trench; depositing a second oxide layer on the first oxide layer and filling-up the trench surrounded by the first oxide layer; annealing to densify the first and second oxide layers; etching-back the first and second oxide layer to remove the portion overlying the first insulating layer, and forming a spacer consisting of the residual first oxide layer on the side-walls of the trench, and a concave bottom oxide consisting of the first and second oxide layers on the bo

Abstract: An EPROM cell and a method that includes a gate structure having a sidewall spacer. The sidewall spacer is made by way of an amorphous or polycrystalline silicon layer, which is converted into an insulating layer such as silicon dioxide. Deposition of the amorphous or polycrystalline silicon layer is more accurate and produces a more uniform layer than conventional dielectric layer deposition.

Abstract: The present invention provides a method for evenly immersing a wafer in a solution held in a solution chamber, which comprises the following steps: (1) placing at least one disk-shaped wafer inside a wafer holder which is used for vertically holding at least one wafer, (2) immersing the wafer holder into the solution vertically so that each wafer in the wafer holder can be vertically immersed into and react with the solution, (3) vertically rotating the wafer holder in the solution so as to invert each wafer in the wafer holder upside down, and (4) removing the wafer holder from the solution vertically after immersing the wafer in the solution for a predetermined period of time.

Abstract: An improved method for forming a buried plate in a bottle-shaped deep trench capacitor. The method includes the steps of: (a) forming a deep trench into a semiconductive substrate; (b) filling the deep trench with a first dielectric material to a first predetermined depth; (c) forming a silicon nitride sidewall spacer in the deep trench above the dielectric layer; (d) removing the first dielectric layer, leaving the portion of the substrate below the sidewall spacer to be exposed; (e) using the sidewall spacer as a mask, causing the exposed portion of the substrate to be oxidized, then removing the oxidized substrate; (f) forming an arsenic-ion-dope conformal layer around the side walls of the deep trench, including the sidewall spacer; (g) heating the substrate to cause the arsenic ions to diffuse into the substrate in the deep trench not covered by the sidewall spacer; and (h) removing the entire arsenic-ion-doped layer.

Abstract: A system and method of compensating for non-linear voltage-to-delay characteristics in a voltage controlled delay line such as those used in delay-locked loop (“DLL”) circuits in integrated circuit (“IC”) devices such as double data rate (“DDR”) dynamic random access memory (“DRAM”), static random access memory (“SRAM”), processors and other IC devices. The technique renders the incremental changes for each correction to the control voltages to the voltage controlled delay line a function of the control voltage itself. The change in the control voltage becomes smaller as the control voltage gets lower thereby effectively precluding over-correction and excessive jitter.

Abstract: A method of fabricating an oxide/nitride multilayer structure is disclosed. The multilayer structure of dielectric films could be applied for manufacturing E2PROM, flash memories, or the dielectric layers of a DRAM capacitor. In accordance with the present invention, all films are formed in the same chamber, and only one heating and one cooling step are needed to form an oxide/nitride/oxide structure or an oxide/nitride/oxide/nitride structure.

Abstract: An improved method for reworking photoresist is provided for decreasing cycle time of photoresist reworking process. A semiconductor substrate with an underlying layer is provided for patterning. A photoresist pattern is formed on the underlying layer. A photoresist reworking process is performed after an after-development-inspection (ADI) is performed. The photoresist reworking method comprises the following steps. The semiconductor substrate is placed in organic stripper for removing the most portion of the photoresist pattern. Subsequently, the semiconductor substrate is placed in a single-wafer processor and an UV/O3 dry ashing is then performed to remove completely the residual photoresist pattern on the underlying layer. A new photoresist layer is deposited on the underlying layer after the photoresist pattern removed completely.

Abstract: In a nonvolatile memory, select gates are self-aligned spacers formed on sidewalls of floating/control gate stacks. The same mask (1710) is used to remove the select gate layer from over the source lines (144), to etch trench insulation in the source line regions, and to dope the source lines. The memory can be formed in and over an isolated substrate region. The source lines can be doped at least partially before the trench insulation is etched, to prevent a short before the source lines and a region isolating the isolated substrate region from below. The memory can be erased by sectors, or alternatively a chip erase operation can be performed to erase all the cells in parallel. Peripheral transistor gates can be formed from the same layer as the select gates. The select gate spacers have extensions to which low resistance contacts can be made from overlying metal lines.

Abstract: A method to prevent the formation of a thinner portion of insulating layer, especially a gate oxide layer, at the junction between the side walls and the bottom insulator is disclosed. First, a pad oxide layer is formed on the side walls and the bottom of the trench. Next, a bottom oxide is formed on the lower portion of the trench. Then, the upper portion of the bottom oxide and the exposed pad oxide layer are removed by wet etching to leave a bottom oxide having a concave surface. Next, the conformal gate oxide layer is grown on the exposed side walls of the trench.

Abstract: A method of forming an isolation structure includes the steps of: providing a silicon substrate; forming an upper pad oxide layer superjacent a top surface of the substrate, and a lower pad oxide layer subjacent a bottom surface of the substrate; forming a nitride masking layer superjacent the upper pad oxide layer, and a lower pad silicon nitride layer subjacent the lower pad oxide layer; patterning and etching the nitride masking layer to expose a portion of the upper pad oxide layer; applying a first etching solution to the exposed portion of the upper pad oxide layer to expose a portion of the substrate substantially defining the boundaries of an active area, and simultaneously forming an undercut cavity by removing a portion of the upper pad oxide layer under the exposed edges of the nitride masking layer surrounding the exposed portion of the substrate; performing an oxidation process to form an etching stop layer over the exposed portion of the substrate and in the undercut cavity, the oxidation proces

Abstract: Circuit elements (e.g. transistor gates) formed over a semiconductor substrate are protected by adjacent dummy structures during mechanical or chemical mechanical polishing of an overlying dielectric.

Abstract: A low power consumption delay locked loop for integrated circuit devices wherein a wider frequency range of operation is achieved by matching the delay of the clock comparison function of the phase detector to the slow operating condition of the programmable delay. In a particular embodiment, this may be effectuated by incorporating at least one additional flip-flop section in the phase detector circuit and more than one such section may be utilized depending on the operating targets of maximum frequency and frequency range. By latching the phase detector outputs through the use of a fast/slow latch circuit, a minimum control pulse is defined which allows a unitized change on the voltage signals that control the programmable delay in a voltage controlled delay line. This also improves efficiency and reduces power consumption by eliminating switching current through transistors that control the voltage levels determining the programmable delay.

Abstract: A process for creating a dual damascene structure without needing an etch stop is disclosed.

Abstract: A method for evaluating ratios of metallic impurities in lithographic materials is disclosed. The method comprises: separating said metal from said lithographic material by microwave heating; then adding said metal to an acid to form a solution; and finally analyzing said solution by a instrument to measure ratio of said metal.

Abstract: A method for producing identifying elements for identifying the specification of a MASK ROM, which can easily accompany the standard process of MASK ROM. Also disclosed a method for identifying a MASK ROM, which can identify the code specification of the MASK ROM produced using simple electrical tests before the product is delivered, thereby achieving high efficiency and low error rate.

Abstract: A method for protecting stepper alignment marks suitable for a substrate with an alignment mark on a scribe line and a metal layer that will be etched includes the following steps. First, a photoresist layer is formed over the metal layer. Next, a photo mask which has a predefined photo mask pattern for transfer to the metal layer is provided, and a pattern protecting the alignment marks is added to the photo mask pattern. Then, a photolithographic process is performed with the photo mask pattern on the photoresist layer to form the desired transferring photoresist mask to the metal layer and the protective photoresist mask for protecting the alignment marks.

Abstract: Disclosed is an apparatus and method for controlling boiling condition of hot H3PO4 solution by adjusting the vapor extracting rate thereof, wherein an acid tank filled with hot H3PO4 solution to a level surface is located in a treatment room and a temperature thermocouple is arranged above the level surface of the hot H3PO4 solution to monitor the vapor temperature near the level surface of the H3PO4 solution. The vapor temperature is used to adjust the extracting rate of the treatment room by control of a damper connected to an outlet of the treatment room. According to the present invention, the treatment apparatus and method can control the boiling condition of the hot H3PO4 solution thereof by properly adjusting the extracting rate, and therefore avoid defects and loss of control in manufacturing processes.

Abstract: A process for forming a gate oxide layer of a trench power MOSFET is provided. The process includes steps of providing a silicon substrate, forming a mask layer on the silicon substrate, removing a portion of the mask layer to expose a portion of the silicon substrate, removing the exposed portion of the silicon substrate to form the trench, removing remaining portion of the mask layer, forming a sacrificial oxide layer on the silicon substrate and on the bottom and sidewall of the trench by thermal oxidation under an operating temperature ranged from 1150 to 1300° C. and an operating time ranged from 20 to 60 minutes, removing the sacrificial oxide layer, and forming a gate oxide layer on the silicon substrate and on the bottom and sidewall of the trench.