Patents Assigned to N/A
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Publication number: 20240070254Abstract: Implementations generally relate to an image-based login and authentication system. In some implementations, a method includes displaying a plurality of random images to a user and receiving from the user a selection of at least one target image from the plurality of random images. The method further includes generating a hash number for the at least one target image, where the hash number identifies the at least one target image, and concealing the hash number in the at least one target image, where the concealing of the hash number provides security in an authentication of the at least one target image. The method further includes generating an encrypted identification token, where the encrypted identification token includes the hash number. The method further includes associating the encrypted identification token with the user, and storing the encrypted identification token in a database for authentication of at least one target image and the user.Type: ApplicationFiled: August 11, 2023Publication date: February 29, 2024Applicant: JPMorgan Chase Bank, N.A.Inventors: Alexander Buts, Ta-Wei Chen, Robert Newnam, Ben Sansom
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Publication number: 20240068701Abstract: An air-conditioning system includes: a compressor unit including a housing accommodating a refrigerant compressor; a high-pressure gas refrigerant pipe connected to a discharge side of the refrigerant compressor; a low-pressure gas refrigerant pipe connected to a suction side of the refrigerant compressor; and air-conditioners. The air-conditioners each include: a return-air inlet and a supply-air outlet each communicating with a predetermined space that is to be air-conditioned; a first heat exchanger configured to cause heat-exchange between refrigerant flowing in the first heat exchanger and air passing through the first heat exchanger; an exhaust-air outlet and an outside-air inlet each communicating with an outside of the predetermined space; and a second heat exchanger configured to cause heat-exchange between refrigerant flowing in the second heat exchanger and air passing through the second heat exchanger.Type: ApplicationFiled: November 6, 2023Publication date: February 29, 2024Applicants: DAIKIN INDUSTRIES, LTD., DAIKIN EUROPE N.V.Inventors: Takahiro Yamaguchi, Stefan Vandaele
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Publication number: 20240071480Abstract: Disclosed herein is an electronic device, including a plurality of row decoders. Each row decoder includes decoder logic generating an initial word line signal and word line driver circuitry generating an inverse word line signal at an intermediate node from the initial word line signal, and generating a word line signal at a word line node from the inverse word line signal. A word line underdrive p-channel transistor has a source coupled to the intermediate node, a drain coupled to a word line underdrive sink, and a gate controlled based upon the inverse word line signal. Negative bias generation circuitry generates the negative bias voltage at a gate of the word line underdrive p-channel transistor when the initial word line signal is at a logic high, and couples the gate of the word line underdrive p-channel transistor to ground when the initial word line signal is at a logic low.Type: ApplicationFiled: August 8, 2023Publication date: February 29, 2024Applicant: STMicroelectronics International N.V.Inventors: Ashish KUMAR, Dipti ARYA
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Publication number: 20240071546Abstract: The memory array of a memory includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A row decoder circuit supports two modes of memory circuit operation: a first mode where only one word line in the memory array is actuated during a memory read and a second mode where one word line per sub-array are simultaneously actuated during the memory read. An input/output circuit for each column includes inputs to the local bit lines of the sub-arrays, a column data output coupled to the bit line inputs, and a sub-array data output coupled to each bit line input. Both BIST and ATPG testing of the input/output circuit are supported. For BIST testing, multiple data paths between the bit line inputs and the column data output are selectively controlled to provide complete circuit testing.Type: ApplicationFiled: July 28, 2023Publication date: February 29, 2024Applicant: STMicroelectronics International N.V.Inventors: Hitesh CHAWLA, Tanuj KUMAR, Bhupender SINGH, Harsh RAWAT, Kedar Janardan DHORI, Manuj AYODHYAWASI, Nitin CHAWLA, Promod KUMAR
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Publication number: 20240074025Abstract: A chamber cross-sectional multi-stage plasma arrangement characterized by escalating charge movement towards chamber center axis through one or more escalation stages contributing to the heating of the plasma, the centering of the plasma on the chamber axis, and creating rotation of the plasma therein. Rotation of the plasma around its axis induces a self-generated magnetic field, which in turn increases plasma stability and confinement. Some of the said stages of the multi-stage arrangement may be created by physical elements and components while others may be induced or generated by externally applying magnetic and/or electric fields or their combinations and/or by injection of electrons, ions or other plasma.Type: ApplicationFiled: November 8, 2023Publication date: February 29, 2024Applicant: N.T. TAO LTD.Inventors: Doron WEINFELD, Boaz WEINFELD, Oded GOUR LAVIE
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Publication number: 20240069096Abstract: An array of a memory includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A row decoder supports two modes of memory operation: a first mode where only one word line in the memory array is actuated during a read and a second mode where one word line per sub-array are simultaneously actuated during the read. An input/output circuit for each column includes inputs to the local bit lines of the sub-arrays, a column data output coupled to the bit line inputs, and a sub-array data output coupled to each bit line input. BIST testing of the input/output circuit is supported through data at both the column data output and the sub-array data outputs in order to confirm proper memory operation in support of both the first and second modes of operation.Type: ApplicationFiled: July 31, 2023Publication date: February 29, 2024Applicant: STMicroelectronics International N.V.Inventors: Bhupender SINGH, Hitesh CHAWLA, Tanuj KUMAR, Harsh RAWAT, Kedar Janardan DHORI, Manuj AYODHYAWASI, Nitin CHAWLA, Promod KUMAR
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Publication number: 20240071429Abstract: The memory array of a circuit includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A control circuit supports two modes of circuit operation: a first mode where only one word line in the memory array is actuated during a memory read and a second mode where one word line per sub-array are simultaneously actuated during the memory read. An input/output circuit for each column includes inputs to the local bit lines of the sub-arrays, a column data output coupled to the bit line inputs, and a sub-array data output coupled to each bit line input. In memory computation operations are performed in the second mode as a function of feature data and weight data stored in the memory.Type: ApplicationFiled: August 14, 2023Publication date: February 29, 2024Applicant: STMicroelectronics International N.V.Inventors: Harsh RAWAT, Nitin CHAWLA, Promod KUMAR, Kedar Janardan DHORI, Manuj AYODHYAWASI
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Publication number: 20240065428Abstract: A brush, rotatably arranged in a cleaning device for cleaning surfaces, is described. The brush includes a core element and brush elements arranged on the core element. The brush elements are arranged in a bristle field extending in a direction of a longitudinal axis of the brush and in a peripheral direction about the longitudinal axis. Further, the brush elements include fiber hairs. Furthermore, a linear mass density of at least tip portions of the brush elements is lower than 15 g per 10 km. In addition, an average of a packing density of the brush elements in the bristle field is lower than 15,000 brush elements per 1 cm2 so as to ensure that for the purpose of moving the brush during a cleaning action, only a relatively small amount of energy is needed.Type: ApplicationFiled: September 30, 2021Publication date: February 29, 2024Applicant: KONINKLIJKE PHILIPS N.V.Inventors: Bastiaan Johannes DE WIT, Anke Rieka MEULENDIJKS, Jamila MIDHAT, Orhan KAHYA, Chengang CAO, Rinse Hendrik BOSMA, Fermín ESPÍN FRANCO, Robert Friso BURGERS, Albert AL-SHORACHI, Arjan Sander VONK
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Publication number: 20240068680Abstract: A humidifier includes a water containing arrangement for containing water and a nebulizing device for nebulizing water from said water containing arrangement. Further, the humidifier includes an evaporation chamber arranged over said nebulizing device and said evaporation chamber terminates at an impactor. A fan is arranged to generate an air flow through said evaporation chamber towards the impactor. The impactor includes an inner body having a plurality of apertures, and an outer body having a plurality of further apertures fluidly connected to said plurality of apertures. The plurality of further apertures are offset relative to said plurality of apertures, such that each aperture of the plurality of apertures in the inner body faces a section of a material of the outer body that is spatially separated from said aperture of said plurality of apertures. Further, described is an impactor for use with such a humidifier.Type: ApplicationFiled: December 10, 2021Publication date: February 29, 2024Applicant: KONINKLIJKE PHILIPS N.V.Inventors: Wei SU, Ruben Arnold Herman REEKERS
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Publication number: 20240071439Abstract: The memory array of a circuit includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A control circuit supports two modes of circuit operation: a first mode where only one word line in the memory array is actuated during a memory read and a second mode where one word line per sub-array are simultaneously actuated during the memory read. An input/output circuit for each column includes inputs to the local bit lines of the sub-arrays, a column data output coupled to the bit line inputs, and a sub-array data output coupled to each bit line input. In memory computation operations are performed in the second mode as a function of feature data and weight data stored in the memory.Type: ApplicationFiled: August 14, 2023Publication date: February 29, 2024Applicant: STMicroelectronics International N.V.Inventors: Harsh RAWAT, Nitin CHAWLA, Promod KUMAR, Kedar Janardan DHORI, Manuj AYODHYAWASI
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Patent number: 11911212Abstract: In an embodiment, an ultrasound scanning device is disclosed. One embodiment of the ultrasound scanning device comprises a housing configured for handheld use, an ultrasound assembly at least partially disposed within the housing and configured obtain ultrasound data, and a display coupled to the housing. The ultrasound scanning device further comprises a processor disposed within the housing, wherein the processor is in communication with the ultrasound assembly and the display.Type: GrantFiled: July 4, 2019Date of Patent: February 27, 2024Assignee: KONINKLIJKE PHILIPS N.V.Inventor: McKee Dunn Poland
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Patent number: 11913519Abstract: A shock absorber is provided having a cylinder, a piston rod, a piston body, and a valve. The cylinder is configured to receive fluid. The piston body is connected to the piston rod and is configured to reciprocate within the cylinder between a compression chamber and a rebound chamber. The valve is provided by the piston body having a fluid flow port, a valve seat, a circumferential valving element, and a spring configured to urge the valve body into the valve seat. A primary damping valve and an auxiliary damping valve are also provided.Type: GrantFiled: August 23, 2022Date of Patent: February 27, 2024Assignee: N10Z Performance Shocks LLCInventor: Peter Russell
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Patent number: 11914952Abstract: A method may include for intent-based natural language processing may include conversation engine: receiving from a conversation program executed on a user electronic device, a unique identifier for a user; calling an external controls program with the unique identifier and a type of the user electronic device, wherein the external controls program identifies a directive of intent and an alternate action; receiving the directive of intent and the alternate action; receiving text of an utterance in a conversation from the conversation program; selecting one of a plurality a priority of intents based on the text of the utterance; receiving a plurality of potential intents and a confidence score for each potential intent from a natural language understanding computer program; selecting a selected intent; determining that the directive of intent matches the selected intent; and executing the alternate action.Type: GrantFiled: October 25, 2021Date of Patent: February 27, 2024Assignee: JPMORGAN CHASE BANK, N.A.Inventors: Ben White, Janie Gordon, Honey L. Miller, Amit Kumar, Piyush Bisht
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Patent number: 11911207Abstract: Various embodiments of the present disclosure include a C-arm registration system employing a controller (70) for registering a C-arm (60) to a X-ray ring marker (20). The X-ray ring marker (20) includes a coaxial construction of a chirp ring (40) and a centric ring (50) on an annular base (30). In operation, the controller (70) acquires a baseline X-ray image illustrative of the X-ray ring marker (20) within a baseline X-ray projection by the C-arm (60) at a baseline imaging pose, derives baseline position parameters of the X-ray ring marker (20) within the baseline X-ray projection as a function of an illustration of the centric ring (50) within the baseline X-ray image, and derives a baseline twist parameter of the X-ray ring marker (20) within the baseline X-ray projection as a function of the baseline position parameters and of an illustration of the chirp ring (40) within the baseline X-ray image.Type: GrantFiled: March 25, 2020Date of Patent: February 27, 2024Assignee: KONINKLIJKE PHILIPS N.V.Inventors: Alexandru Patriciu, Alyssa Torjesen, Molly Lara Flexman, Ashish Sattyavrat Panse, Marcin Arkadiusz Balicki, Ronaldus Frederik Johannes Holthuizen
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Patent number: 11913858Abstract: Disclosed is a disc-shaped sample chamber for collecting molten metal, the chamber comprising: a chamber body having a left body and a right body bonded to each other to define a disc-shaped sample space therebetween; an inlet extending upward from the chamber body and connecting the sample space with the outside; and a welded bonding portion disposed on at least one lateral face of the chamber body for bonding the left body and the right body to each other. Further, a probe having the chamber is disclosed.Type: GrantFiled: December 11, 2020Date of Patent: February 27, 2024Assignee: HERAEUS ELECTRO-NITE INTERNATIONAL N.V.Inventors: Bong-Ki Baik, Young-jin Jung, Cheol-jung Kim
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Patent number: 11916734Abstract: The invention relates to a communication network which is configured to enable instantiation of network slices which represent virtual networks. The invention further relates to a content application server (CAS) for providing an application service via a network slice to at least one user equipment (UE). A network function (SREF) is provided which on the one hand may have access to one or more slice management network functions (CSMF, NSMF, NSSMF) and on the other hand may be accessible to the CAS. The network function (SREF) may abstract the properties of the network slice using a data structure representing a slice object and expose these abstracted properties to the CAS by providing access to the slice object. The slice object may comprise modifiable properties which represent modifiable properties of the corresponding network slice.Type: GrantFiled: March 20, 2020Date of Patent: February 27, 2024Assignees: KONINKLIJKE KPN N.V., NEDERLANDSE ORGANISATIE VOOR TOEGEPAST-NATUURWETENSCHAPPELIJK ONDERZOEK TNOInventors: Lucia D'Acunto, Toni Dimitrovski, Wieger IJntema, Wiltfried Pathuis
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Patent number: 11913046Abstract: Microbial cells genetically engineered with a heterologous nucleic acid sequence that increases export of 2? fucosyllactose are disclosed. Methods of increasing export of 2? fucosyllactose from a microbial cell and for identifying a heterologous nucleic acid sequence that increases export of 2? fucosyllactose from a microbial cell are also disclosed.Type: GrantFiled: April 23, 2018Date of Patent: February 27, 2024Assignee: INBIOSE N.V.Inventors: Kerry Hollands, Lori Anne Maggio-Hall, Steven Cary Rothman
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Patent number: 11914743Abstract: Systems, methods, and apparatuses for providing a central location to manage permissions provided to third-parties and devices to access and use user data and to manage accounts at multiple entities. A central portal may allow a user to manage all access to account data and personal information as well as usability and functionality of accounts. The user need not log into multiple third-party systems or customer devices to manage previously provided access to the information, provision new access to the information, and to manage financial or other accounts. A user is able to have user data and third-party accounts of the user deleted from devices, applications, and third-party systems via a central portal. The user is able to impose restrictions on how user data is used by devices, applications, and third-party systems, and control such features as recurring payments and use of rewards, via a central portal.Type: GrantFiled: September 14, 2020Date of Patent: February 27, 2024Assignee: Wells Fargo Bank, N.A.Inventors: Lila Fakhraie, Brian M. Pearce, Steven Pulido, Benjamin Soccorsy, James Stahley, Mojdeh Tomsich
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Patent number: 11914499Abstract: A trace-data preparation circuit including a filtering circuit to receive traced memory-write data and a First In First Out buffer coupled with the filtering circuit to receive selected memory-write data filtered by the filtering circuit. The trace-data preparation circuit further including a data compression circuit to provide packaging data to a packaging circuit that groups the selected memory-write data.Type: GrantFiled: October 29, 2021Date of Patent: February 27, 2024Assignees: STMicroelectronics Application GMBH, STMicroelectronics S.r.l., STMicroelectronics International N.V.Inventors: Avneep Kumar Goyal, Thomas Szurmant, Misaele Marletti, Alessandro Daolio
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Patent number: D1016075Type: GrantFiled: October 19, 2021Date of Patent: February 27, 2024Assignee: JPMORGAN CHASE BANK , N.A.Inventors: Patrick Guindon, John Frerichs, Inna Lobel, Francois D Nguyen, Jung Soo Park, Kebei Li, Adam Christopher Wrigley