Abstract: An ESD protection device includes at least one semiconductor electronic switch electrically coupled in parallel with a diode. The semiconductor electronic switch and the diode each include at least one finger extending substantially parallel to a first direction. The fingers of the semiconductor electronic switch and of the diode are aligned with each other along this first direction.

Abstract: An electrostatic discharge protection circuit protects a first transistor. The circuit includes N diodes in series between conduction terminals of the first transistor. A second transistor and third transistor are connected in series between the conduction terminals of the first transistor. A control terminal of the third transistor is coupled to an anode of the N diodes. A first inverter couples the control terminals of the first and second transistors. A fourth transistor is connected in parallel with the first transistor. A control terminal of the fourth transistor is coupled to the junction point of the second and third transistors. A capacitor is arranged between the control terminal of the fourth transistor and a conduction terminal of the first transistor.

Abstract: An integrated circuit package includes a support plate having a mounting face. An electronic chip, having a rear face and a front face, is mounted on the mounting face with the front face electrically connected to the mounting face of the support plate. A deformable thermally conductive film covers at least one portion of the rear face of the electronic chip so that the film is in contact with the rear face.

Abstract: Composite material comprising a fluoropolymer matrix and a filler formed of nanoparticles of a ceramic of the BZT-?BXT type wherein X is selected from Ca, Sn, and Mn and a is a molar fraction selected in the range between 0.10-0.90 doped with at least one doping element selected from the group consisting of Nb, La, Mn, Nd and W, wherein when X is Mn, the doping element is not Mn, wherein said nanoparticles have an average diameter comprised between 10 and 25% by weight on the total weight of the composite. The composite material is used to form a thin film usable as a piezoelectric material with inductive properties in electronic components, for example acoustic sensors such as microphones, and energy harvesting transducers.

Abstract: Provided is a module for monitoring instructions of a microcontroller. The module is adapted to receive instructions that are received at an input terminal of the microcontroller or that are being processed by a code pointer of the microcontroller. The module verifies the instructions received on the input terminal of the microcontroller or that are being processed by the code pointer of the microcontroller.

Abstract: A system for managing a regulated network of network controls to maintain compliance with applicable regulations. The system may comprise instructions that, when executed, cause a processor to: monitor, a network data source, for new regulatory data that pertains to the regulated network; identify new regulatory data that has been obtained from the network data source; determine whether the new regulatory data requires changes to existing network controls from among the network controls; after determining that the new regulatory data requires the changes, implement the changes; determine whether the first set of new regulatory data requires modifying the network controls to include new network controls that pertain to the network; and after determining that the new regulatory data requires the modifying, add the new network controls to the network controls.

Abstract: In one example, a method for rotating security credentials includes instantiating an execution environment in which to execute instructions of a script. The method also includes executing the instructions of the script within the execution environment to cause the at least one processor to monitor a passage of time to identify an arrival of a time to coordinate a rotation of a security credential between an executable routine and a secrets management service. The at least one processor is also caused, in response to identifying the arrival of the time, perform operations including: providing a first request to the executable routine to communicate with the secrets management service of the processing device to request rotation of the security credential at the secrets management service, and providing a second request to the executable routine to rotate the security credential at the executable routine.

Abstract: A memory array includes a plurality of bit-cells arranged as a set of rows of bit-cells intersecting a plurality of columns. The memory array also includes a plurality of in-memory-compute (IMC) cells arranged as a set of rows of IMC cells intersecting the plurality of columns of the memory array. Each of the IMC cells of the memory array includes a first bit-cell having a latch, a write-bit line and a complementary write-bit line, and a second bit-cell having a latch, a write-bit line and a complementary write-bit line, wherein the write-bit line of the first bit-cell is coupled to the complementary write-bit line of the second bit-cell and the complementary write-bit line of the first bit-cell is coupled to the write-bit line of the second bit-cell.

Abstract: An amplification circuit includes an amplifier circuit (provided by an operational amplifier) that amplifies a signal to be demodulated. A feedback loop of the amplification circuit has a resistance value that is controlled to discretely vary according to a level of an output node of the amplifier circuit. A comparison of the output level with respect to one or a plurality of thresholds, which define out-of-saturation operating ranges of the amplifier circuit, drives selection of the resistance value.

Abstract: A structure including a base portion (e.g., made of a graphite-based or graphene-based material) with at least one surface that is coated with a homogenous coating layer (e.g., made of silicon-carbide (SiC)). The homogenous coating layer prevents contaminants (e.g., carbon) from being released by the base portion into a cavity of a processing tool when heated to process one or more workpieces (e.g., silicon substrate, silicon wafers, etc.) present within the cavity. The homogenous coating layer includes grains and grain boundaries that are relatively the same size and shape as each other, which further prevents propagation of defects (e.g., cracking, peeling, etc.) that could potentially cause exposure of a region of the first surface of the base portion to the cavity of the processing tool contaminating the one or more workpieces present within the cavity of the processing tool.

Abstract: Systems and methods for generating shared accounts and performing shared account transactions include a computing system which receives a request from a first user device of a first user to form a shared account accessible by a second user based on one or more rules, generates the shared account, links a first account with the shared account, identifies the second user, transmits a notification to a second user device of the second user indicating the second user has access to the shared account, receives an input to the second user device indicating acceptance of access to the shared account, links a second account with the shared account, receives a second input to the second user device indicating a selection to initiate an outbound transfer of resources and a category, determines that the category meets at least one rule, and initiates the outbound transfer of resources from the shared account.

Abstract: A computer-implemented method includes determining, by a provider computing system associated with a provider, a goal of a first customer. The computer-implemented method further includes identifying, by the provider computing system, one or more second customers similar to the first customer based on a characteristic of the first customer. The computer-implemented method further includes determining, by the provider computing system, one or more actions taken by the one or more second customers to achieve the goal. The computer-implemented method further includes generating, by the provider computing system, a graphical user interface including an indication of the one or more actions taken by the one or more second customers to achieve the goal. The computer-implemented method further includes transmitting, by the provider computing system, the graphical user interface to a customer device associated with the first customer.

Abstract: The present description relates to a vertical power component formed in and on a semiconductor substrate doped with a first conductivity type and coated, on the upper side thereof, with a semiconductor layer doped with the first conductivity type. The component includes: an active region (100A); and first and second groups of first concentric field limiting rings surrounding the active region. Each first ring includes a first semiconductor region doped with a second conductivity type, opposite to the first conductivity type, extending vertically into the thickness of the semiconductor layer from the upper side thereof; and a second field limiting ring laterally interposed between the first and second groups of first field limiting rings (GR). The second ring includes a second doped semiconductor region of the second conductivity type extending vertically into the thickness of the semiconductor layer from the upper face thereof.

Abstract: Sensor device with a microcontroller unit and a sensor including a transducer, which is coupleable to a device and generates a signal indicative of a physical quantity, and a processing circuit including: a conversion stage which generates samples of the physical quantity; a data generation stage which generates data vectors as a function of the samples, each data vector being formed by programmable quantity values; and a decision stage. The microcontroller unit programs the decision stage so that it classifies the data vectors by executing a decision tree having a structure and thresholds.

Abstract: A device includes a first MOS transistor connected between first and second nodes, a selectively activatable current source connected between the second node and a third node and a circuit configured to control the first transistor to regulate a voltage at the second node to a first set point value. The device further includes a second MOS transistor connected between the first node and a fourth node, and having its gate connected to the gate of the first MOS transistor, a third MOS transistor connected between the third and fourth nodes, a switch connected between the second and fourth nodes, and another circuit configured to control the third transistor to regulate a voltage at the fourth node to a second set point value.

Abstract: A time-of-flight (TOF) sensor includes a timing generator generating a timing reference, a first array of TOF-related components including rows of TOF-related components, with each row receiving the timing reference, and a dummy row of TOF-related components. The TOF sensor also includes a second array of TOF-related components including rows of TOF-related components, with each row receiving the timing reference, and a dummy row of TOF-related components. A first path delivers the timing reference to the rows of the first array, the first path passing from the timing generator, through the dummy row of TOF-related components in the second array, to the first array of TOF-related components. A second path delivers the timing reference to the rows of the second array, the second path passing from the timing generator, through the dummy row of TOF-related components in the first array, to the second array of TOF-related components.

Abstract: An in-memory computation circuit includes a memory array with memory cells arranged in a matrix in rows and columns. Groups of memory cells store computational weights for an in-memory compute (IMC) operation that is performed with a first multiply and accumulate (MAC) elaboration to produce a first analog signal and a second MAC elaboration to produce a second analog signal. An analog-to-digital converter circuit operates to: increment a count value in a counter circuit in response to the first analog signal; convert the count value in the counter circuit to a negated count value; and increment the count value in the counter circuit starting from the negated count value in response to the second analog signal.

Abstract: A method of operating an inertial sensor module includes receiving a stream of inertial sensor data representing activity of a user of an electronic device and generating a plurality of wavelet sub-bands by performing a wavelet transform on the inertial sensor data. The method includes identifying a wavelet sub-band of highest energy from the plurality of wavelet sub-bands, generating augmented inertial sensor data by combining the wavelet sub-band of highest energy to the inertial sensor data, and identifying a first transition in the activity of the user based on the augmented inertial sensor data.

Abstract: The present disclosure relates to an image sensor comprising an array of pixels arranged in first rows and in first columns. The pixels are arranged in groups of N*N pixels, with N an integer equal to or higher than 2. In each group, the pixels of the group are distributed into one or more sub-groups of a plurality of pixels. Each pixel comprises: a photosensitive element, a first node coupled to the photosensitive element, a second node common to all pixels of a same sub-group, and coupled to a first potential, a first transistor coupling the first and second nodes to each other, a second source-follower transistor having a gate connected to the first node, and a third transistor coupling the source of the third transistor to a reading line.

Abstract: Provided is a power converter including first, second, third and fourth nodes and a wire bonding test circuit. The wire bonding test circuit includes a multiplexer having a first terminal of a first side coupled to the first node and second and third terminals of a second side. The wire bonding test circuit includes a first switch having a first terminal coupled to the second terminal or the third terminal of the multiplexer and a second terminal coupled to the second node. The wire bonding test circuit includes a second switch having a first terminal coupled to the second terminal or the third terminal of the multiplexer and a second terminal coupled to the third node. The wire bonding test circuit includes a third switch having a first terminal coupled to the second terminal or the third terminal of the multiplexer and a second terminal coupled to the fourth node.