Patents Assigned to N/A
  • Publication number: 20240330898
    Abstract: A provider computing system comprises one or more processing circuits to determine that a personal identification number (PIN) has not been set for a new card to be provided to a customer, generate a card mailer to accompany the new card when the new card is provided to the customer where generating the card mailer comprises adding access information to the card mailer, cause the generated card mailer to be provided to the customer, receive a request from a customer device of the customer to enter a secure session where the request from the customer device to enter the secure session is received based on the customer device interacting with the access information provided with the generated card mailer, receive a desired PIN from the customer device within the secure session, and set the PIN for the new card as the desired PIN received from the customer device.
    Type: Application
    Filed: June 13, 2024
    Publication date: October 3, 2024
    Applicant: Wells Fargo Bank N.A.
    Inventor: Young M. Yang
  • Publication number: 20240333302
    Abstract: A delta-sigma modulator includes a loop filter circuit having a first input that receives an input signal and a second input that receives a feedback signal. The loop filter circuit generates a filtered signal. A quantizer circuit quantizes the integrated signal to generate an output signal. An anti-windup circuit detects instances where the integrated signal is outside an input signal input of the quantizer circuit and in response thereto generates a dead zone signal having a magnitude and sign corresponding to a difference between the filtered signal and the input signal range. The feedback signal is a sum of the output signal and the dead zone signal.
    Type: Application
    Filed: March 29, 2023
    Publication date: October 3, 2024
    Applicants: STMicroelectronics International N.V., Universita' Pavia, Politecnico Di Torino
    Inventors: Francesco STILGENBAUER, Edoardo BOTTI, Piero MALCOVATI, Paolo Stefano CROVETTI, Edoardo BONIZZONI, Matteo DE FERRARI
  • Publication number: 20240329125
    Abstract: A method and apparatus for aligning electrical contact formations, such as bumps or solder balls, at a first surface of a Wafer Level Chip Scale Package (WLCSP) semiconductor device with electrically conductive pins in an array of electrically conductive pins such as “pogo” pins is provided. The semiconductor device includes, opposite the first surface, a second surface protected by a protection layer. The method includes aligning the semiconductor device to a first alignment member by exposing the protected second surface of the semiconductor device to a chamfered surface in the first alignment member. A second alignment member is aligned to the array of electrically conductive pins. The electrical contact formations are aligned with respect to the array of electrically conductive pins as desired in response to the first and second alignment members being mutually aligned, in response to the semiconductor device being “landed” onto the array of electrically conductive pins.
    Type: Application
    Filed: March 26, 2024
    Publication date: October 3, 2024
    Applicant: STMicroelectronics International N.V.
    Inventors: Moise AVOCI UGWIRI, Giuliano FILPI, Fabrice COSTE, Alex GRIMA, Pedro Jr Santos PERALTA
  • Publication number: 20240332011
    Abstract: At least one embodiment of a method of manufacturing includes forming a first polycrystalline silicon carbide (SiC) substrate with a sintering process by sintering one or more powdered semiconductor materials. After the first polycrystalline SiC substrate is formed utilizing the sintering process, the first polycrystalline silicon carbide SiC substrate is utilized to form a second polycrystalline SiC substrate with a chemical vapor deposition (CVD) process. The second polycrystalline SiC substrate is formed on a surface of the first polycrystalline SiC substrate by depositing SiC on the surface of the first polycrystalline SiC substrate with the CVD process. As the first and second polycrystalline SiC substrates are made of the same or similar semiconductor material (e.g., SiC), a first coefficient of thermal expansion (CTE) for the first polycrystalline SiC substrate is the same or similar to the second CTE of the second polycrystalline SiC substrate.
    Type: Application
    Filed: March 22, 2024
    Publication date: October 3, 2024
    Applicant: STMicroelectronics International N.V.
    Inventors: Björn MAGNUSSON LINDGREN, Alexandre ELLISON, Carlo RIVA
  • Publication number: 20240329978
    Abstract: The present disclosure is directed to systems, methods, and non-transitory computer-readable media including adding first block to a blockchain in response to signing first code by a first system and adding second block to the blockchain in response to signing second code by second system, the second code is different from the first code. The first block includes a first time indicator. The second block includes a second time indicator.
    Type: Application
    Filed: March 30, 2023
    Publication date: October 3, 2024
    Applicant: Wells Fargo Bank, N.A.
    Inventor: Jeffrey J. Stapleton
  • Publication number: 20240331522
    Abstract: The present disclosure is directed to a device and method for human fall detection solution. Fall detection is performed by a low power inertial measurement unit (IMU) that is communicatively coupled between a pressure sensor and an application processor. The IMU includes one or more motions sensors, such as an accelerometer and gyroscope. The application processor is the main processor of the containing device. The IMU receives pressure sensor data from the pressure sensor, and executes the fall detection using both the pressure sensor data and accelerometer data.
    Type: Application
    Filed: March 28, 2023
    Publication date: October 3, 2024
    Applicant: STMicroelectronics International N.V.
    Inventors: Federico RIZZARDINI, Lorenzo BRACCO
  • Publication number: 20240330975
    Abstract: One or more embodiments of techniques or systems for intelligent data presentation are provided herein. Data can be presented on similar devices having different characteristics in different manners. For example, data may be rendered in a first manner on a first device having one monitor, the same data may be rendered in a second manner on a second device having two displays or a different display size. Financial information, sales data, banking information, etc. may be presented in a variety of ways based on capabilities or properties of a device accessing the information or data. Similarly, renderings may be selected based on interaction capabilities or interaction options a user may have with different renderings or presentations. In other embodiments, user interaction with an automated teller machine (ATM), call center, vehicle, or other interface can be based on device properties or device capabilities.
    Type: Application
    Filed: June 10, 2024
    Publication date: October 3, 2024
    Applicant: Wells Fargo Bank, N.A.
    Inventors: Stephen M. Ellis, Bipin Sahni, David Hatch, Shahid Razzaq
  • Publication number: 20240330677
    Abstract: A neural network is able to reconfigure hardware accelerators on-the-fly without stopping downstream hardware accelerators. The neural network inserts a reconfiguration tag into the stream of feature data. If the reconfiguration tag matches an identification of a hardware accelerator, a reconfiguration process is initiated. Upstream hardware accelerators are paused while downstream hardware accelerators continue to operate. An epoch controller reconfigures the hardware accelerator via a bus. Normal operation of the neural network then resumes.
    Type: Application
    Filed: March 29, 2023
    Publication date: October 3, 2024
    Applicant: STMicroelectronics International N.V.
    Inventors: Carmine CAPPETTA, Paolo Sergio ZAMBOTTI, Thomas BOESCH, Giuseppe DESOLI
  • Publication number: 20240329245
    Abstract: The present disclosure is directed to human presence detection with an infrared sensor. The human presence detection utilizes signal regularization and edge detection to minimize the effect of drift on the human presence detection. The human presence detection is accurate regardless of changes in ambient temperatures.
    Type: Application
    Filed: April 27, 2023
    Publication date: October 3, 2024
    Applicant: STMicroelectronics International N.V.
    Inventors: Piergiorgio ARRIGONI, Stefano Paolo RIVOLTA, Marco BIANCO
  • Publication number: 20240333477
    Abstract: The present disclosure is directed to systems, methods, and non-transitory computer-readable media including providing an attribute certificate to a Key Receiving Device (KRD). The attribute certificate indicates that the KRD is bound to a Key Dsitribution Host (KDH) for key distribution. A whitelist is provided to the KDH. The whitelist includes a list of at least one KRD bound to the KDH.
    Type: Application
    Filed: March 30, 2023
    Publication date: October 3, 2024
    Applicant: Wells Fargo Bank, N.A.
    Inventor: Jeffrey J. Stapleton
  • Publication number: 20240330518
    Abstract: A circuit is configured to perform an operation between a volatile memory and a cryptographic circuit in response to a write access request for writing one or more data values in the memory. The access request further includes a storage address in the memory. The operation includes steps for: writing the one or more data values; and for each of the one or more data values, generating a write access request, in the cryptographic circuit, for the data value, and generating a write access request, in the cryptographic circuit of the storage address. Additionally, a verification, in response to a read access request, from the processor, of a verification value is performed. The verification operation includes steps for: comparing the verification value with a reference value; and based on the comparing, authorizing access the volatile memory only for reading.
    Type: Application
    Filed: March 27, 2024
    Publication date: October 3, 2024
    Applicant: STMicroelectronics International N.V.
    Inventors: Nicolas ANQUET, Gilles PELISSIER, Ruggero SUSELLA, Julien MONTMASSON
  • Publication number: 20240329719
    Abstract: A method is for synchronizing power consumption data with trace data in a microcontroller debugging system. The method involves periodically sending synchronization requests from a host device to a synchronization manager within a debug probe. The synchronization manager retrieves the current power acquisition cycle number from a power acquisition circuit in response to each request, corresponding to a current sample of microcontroller power consumption. Each synchronization request, along with the retrieved cycle number, is sent to a protocol manager, which transmits the request to a microcontroller's debug-port. Upon receiving acknowledgment from the microcontroller, the protocol manager communicates these to the synchronization manager. The synchronization manager measures the latency between sending each synchronization request and receiving its acknowledgment, which is indicative of synchronization quality.
    Type: Application
    Filed: June 12, 2024
    Publication date: October 3, 2024
    Applicant: STMicroelectronics International N.V.
    Inventors: Sylvain CHAVAGNAT, Simon VALCIN
  • Publication number: 20240330818
    Abstract: Systems and methods are described for a three-tiered artificial intelligence architecture that synchronizes processing statement deployment across diverse computer networks. The system may receive, at a user interface, a first request for a first recommendation. The first recommendation includes a set of standardized processing statements for implementing on a function. The system may input the first request into a first network component. The first network component includes first, second, and third models. The first model is trained to generate a library of standardized processing statements. The second model is trained to generate a plurality of standardized processing characteristic values for each standardized processing statement in the library. The third model is trained to generate recommendations of sets of standardized processing statements to functions. The system receives an output from the first network component and generates for display the first recommendation based on the output.
    Type: Application
    Filed: July 28, 2023
    Publication date: October 3, 2024
    Applicant: Citibank, N.A.
    Inventors: Maneet SHARMA, Flora SAH, Adar Kiran DANAIT, Ashima GUPTA, James IACONA, Crystal Lynn MAGRUDER, Tracy L. YAGER
  • Publication number: 20240330907
    Abstract: A system and method for preventing the double-spending of digital currency that transfers between multiple DLT networks. The system and method includes creating a first digital currency of a first type on the first DLT network stored in a digital wallet, the first digital currency associated with a second digital currency of a second type on a second DLT network, configuring a monitoring agent on the node, the monitoring agent configured to intercept at least one of a function call, a message, or an event on the digital wallet, and locking, responsive to intercepting the at least one of the function call, the message, or the event, the first digital currency onto the first DLT network to prevent a transfer of the first digital currency from the digital wallet on the first DLT network to another DLT network responsive to a subsequent transaction request.
    Type: Application
    Filed: June 10, 2024
    Publication date: October 3, 2024
    Applicant: Wells Fargo Bank N.A.
    Inventors: Abhijit Shetti, Laura Marie Fontana, Rameshchandra B. Ketharaju, Andrew J. Garner, IV, Nikolai Stroke, Duc Trinh, Mabel Oza, Todd Biggs
  • Publication number: 20240330660
    Abstract: A neural network includes an internal storage unit. The internal storage unit stores feature data received from a memory external to the neural network. The internal storage unit reads the feature data to a hardware accelerator of the neural network. The internal storage unit adapts a storage pattern of the feature data and a read pattern of the feature data to enhance the efficiency of the hardware accelerator.
    Type: Application
    Filed: January 29, 2024
    Publication date: October 3, 2024
    Applicant: STMicroelectronics International N.V.
    Inventors: Carmine CAPPETTA, Surinder Pal SINGH, Giuseppe DESOLI, Thomas BOESCH, Michele ROSSI
  • Publication number: 20240333175
    Abstract: A converter circuit is configured to convert a DC voltage into an AC voltage using a first thyristor and second thyristor in series in a first branch, a third thyristor and fourth thyristor in series in a second branch in an antiparallel configuration to the first branch, and a first transistor and second transistor in series in a third branch. When the AC voltage is equal to zero, and when the first thyristor is conductive and the first and second transistors are non-conductive, a first positive current is applied to the gate of the antiparallel third thyristor to control turn on and ensure that the current circulating in the first thyristor falls below the holding current.
    Type: Application
    Filed: March 25, 2024
    Publication date: October 3, 2024
    Applicant: STMicroelectronics International N.V.
    Inventors: Yannick HAGUE, Guillaume THIENNOT, Romain LAUNOIS
  • Publication number: 20240332365
    Abstract: Various embodiments of wafers include a polycrystalline silicon carbide (SiC) layer or base substrate. The polycrystalline silicon carbide (SiC) layer may have a resistivity less than or equal to 2 mohm-cm (milliohm-centimeter) such that the polycrystalline silicon carbide layer is a low resistivity polycrystalline silicon carbide layer. The polycrystalline silicon carbide layer may have grains with a grain size less than or equal to 1 millimeter (mm), and may have a non-columnar structure. The polycrystalline silicon carbide layer may have a warpage less than or equal to 75 ?m (micrometers). A monocrystalline silicon carbide (SiC) layer may be coupled to the polycrystalline silicon carbide (SiC) layer by a bonding layer. The monocrystalline silicon carbide layer may be thinner than the polycrystalline silicon carbide layer.
    Type: Application
    Filed: March 22, 2024
    Publication date: October 3, 2024
    Applicant: STMicroelectronics International N.V.
    Inventors: Björn MAGNUSSON LINDGREN, Carlo RIVA
  • Publication number: 20240333753
    Abstract: A system includes a data channel configured to provide device connectivity data associated with an entity, a data channel communication network configured to communicate the device connectivity data from the data channel, and a processing circuit communicatively coupled to the data channel via the data channel communication network. The processing circuit is structured to identify a vulnerability associated with a property of the device connectivity data, generate a scanner uniform resource locator (URL) based on the property of the device connectivity data, the scanner URL including a parametrized scanner executable structured to accept as a parameter at least a part of the property of the device connectivity data, and transmit the scanner URL to a computing system.
    Type: Application
    Filed: June 13, 2024
    Publication date: October 3, 2024
    Applicant: Wells Fargo Bank, N.A.
    Inventors: Shane Cross, Daniel Fricano, Thomas Gilheany, Peter Anatole Makohon, Dale Miller, Charles Steven Edison, Kodzo Wegba, James Bonk
  • Publication number: 20240334080
    Abstract: An electronic circuit includes image acquisition cells, wherein each cell has a photodetector coupled to a first node of the cell, and an amplifying transistor having a gate connected to the first node, a conduction node coupled to an output of the cell, and a node for controlling a back gate voltage. The amplifying transistor is configured so that its threshold voltage varies according to the back gate voltage. A control circuit adjusts a voltage applied to the control node of the back gate voltage of the amplifying transistor of one of the cells according to a comparison of the voltage present at the cell output and a reference voltage.
    Type: Application
    Filed: March 26, 2024
    Publication date: October 3, 2024
    Applicant: STMicroelectronics International N.V.
    Inventor: Laurent SIMONY
  • Publication number: 20240327199
    Abstract: Microelectromechanical device comprising a supporting body, containing semiconductor material and a movable mass, constrained to the supporting body with a relative degree of freedom with respect to at least one motion direction, within a range of admissible positions. The device also comprises stopper elements, operable by the movable mass due to movements along the at least one motion direction and configured to apply stop forces to opposite sides of the movable mass, transversely to the at least one motion direction, when the movable mass reaches a respective endpoint of the range of admissible positions, so as to prevent the movable mass from exceeding the respective endpoint.
    Type: Application
    Filed: March 22, 2024
    Publication date: October 3, 2024
    Applicant: STMicroelectronics International N.V.
    Inventors: Paola CARULLI, Patrick FEDELI, Luca Giuseppe FALORNI, Federico MORELLI