Patents Assigned to Nagoya Industrial Science Research Institute
  • Publication number: 20030179226
    Abstract: When a machine body 3 of a machining center 2 is being used to machine a component based on CAM data, an in-process information processing module 1a transfers to a host computer 5 in-process information of the component which is obtained by integrally processing detection data output from a temperature sensor, a vibration sensor, etc. provided to the machine body 3, to cause the in-process information of the component to be displayed on a display of the host computer 5 in such a manner that the in-process information can be compared to CAD data. In such a manner, a person in charge of the machining center can obtain improvement information in a machining process of the component based on comparison between the in-process information and the CAD data, to thereby improve an efficiency of an experimental-production process, thus reducing a development period of a product.
    Type: Application
    Filed: March 10, 2003
    Publication date: September 25, 2003
    Applicants: Union Electronics Co., Ltd., Nagoya Industrial Science Research Institute, AG Co., Ltd., Renaissance of Technology Corporation
    Inventors: Tadao Kawai, Yasumasa Okamoto, Makoto Ohno, Takashi Kosugi
  • Patent number: 6496815
    Abstract: There is provided a neuron which is capable of expressing an excitative coupling and a suppressive coupling by one signal by devising signals processed in the neuron to reduce a circuit area of a neural network in constructing the neural network by a digital electronic circuit. A multiplying block calculates a numerical value following a normal distribution N(wx, 1) by using a corresponding link weight w under the supposition that delay time of each pulse of an input signal follows a normal distribution of N(x, 1). Next, an adding block adds the numerical values calculated by the respective multiplying blocks one after another and a non-linear operating block counts a number of positive values within the added value obtained by the adding block. A pulse delaying block delays output pulse following a normal distribution in which delay time is 0 in average generated by a basic pulse generating block based on the result of operation of the non-linear operating block to output as an output signal.
    Type: Grant
    Filed: May 24, 2000
    Date of Patent: December 17, 2002
    Assignees: Denso Corporation, Nagoya Industrial Science Research Institute
    Inventor: Takeshi Kawashima
  • Patent number: 6388597
    Abstract: A &Dgr;-&Sgr; converter comprises a &Dgr;-&Sgr; modulator and a digital filter. The &Dgr;-&Sgr; modulator has a comparator having two resonant tunnel diodes connected to each other in series between two terminals and a field effect transistor connected in parallel to one of the resonant tunnel diodes, a conversion input transistor for converting an input voltage into electric current, a capacitor provided so that charge amount thereof is decreased by flow of electric current through the conversion input transistor and an electric potential proportional to the charge amount is used for the input electric potential to the comparator, and a feedback transistor, to which an output of the comparator is inputted, operating in such a way as to increase the charge amount of the capacitance element when the output of the comparator becomes a high level.
    Type: Grant
    Filed: August 30, 2001
    Date of Patent: May 14, 2002
    Assignee: Nagoya Industrial Science Research Institute
    Inventors: Koichi Maezawa, Takashi Mizutani