Patents Assigned to Nanya Technology Corp.
  • Semiconductor memory device
    Patent number: 8063404
    Abstract: A semiconductor memory device positioned on an SOI substrate. A semiconductor memory device includes two transistors with three terminals which serve as a source, a reading drain and a writing drain, respectively. The writing drain is heavily-doped for high writing efficiency. A floating body region for storing charges is also heavily-doped to reach long data retention time.
    Type: Grant
    Filed: March 31, 2010
    Date of Patent: November 22, 2011
    Assignee: Nanya Technology Corp.
    Inventor: Shing-Hwa Renn
  • Method for modifying photomask layout
    Patent number: 8056024
    Abstract: A method for modifying a photomask layout includes the following steps. First, a photomask layout having at least an edge is provided. A plurality of evaluation points are positioned on the edge. Then, the photomask layout is interpreted to have an interpreted photomask layout and an interpreted edge pattern. The interpreted edge pattern is formed by interpreting the above-mentioned edge. After that, a shift between the edge and the interpreted edge and corresponding to each of the evaluation points is calculated. Afterwards, a shift gradient between two evaluation points can be derived from the shift. Finally, a number of segments between each two evaluation points can be estimated.
    Type: Grant
    Filed: December 24, 2008
    Date of Patent: November 8, 2011
    Assignee: Nanya Technology Corp.
    Inventors: Chia-Wei Lin, Kun-Yuan Chen
  • Phase change memory
    Patent number: 8045367
    Abstract: A phase change memory with a primary memory array, a reference memory array, and a comparison circuit is provided. The electrical characteristic curve of the recording layers of the primary memory units is different from the electrical characteristic curve of the recording layers of the reference memory units. The primary memory array includes at least one primary memory unit to generate at least one sensing signal, wherein each of the primary memory units includes at least one recording layer can be programmed to a first resistance and a second resistance. The reference memory array includes at least one reference memory unit to generate at least one reference signal, wherein each of the reference memory units includes at least one recording layer can be programmed to change its resistance. The comparison circuit compares the sensing signal and the reference signal to generate a comparison result.
    Type: Grant
    Filed: August 8, 2008
    Date of Patent: October 25, 2011
    Assignee: Nanya Technology Corp.
    Inventor: Te-Sheng Chao
  • Method for detecting minimum operational frequency
    Patent number: 8044691
    Abstract: A method of detecting a minimum operational frequency includes: generating a signal that becomes an oscillating signal at a first predetermined frequency; and generating a logic signal to provide a level transition when a frequency of the oscillating signal reaches a second predetermined frequency corresponding to the minimum operational frequency. The logic signal is generated by: providing a transistor that is activated at the second predetermined frequency; providing a capacitor; storing charges in the capacitor when the oscillating signal is below the second predetermined frequency; discharging the capacitor when the transistor is activated by the oscillating signal; and outputting the logic signal when the capacitor discharges.
    Type: Grant
    Filed: May 21, 2010
    Date of Patent: October 25, 2011
    Assignee: Nanya Technology Corp.
    Inventors: Ryan Andrew Jurasek, Bret Roberts Dale, Darin James Daudelin, Dave Eugene Chapmen
  • Data programming circuits and memory programming methods
    Patent number: 8031515
    Abstract: A data programming circuit for storing a writing data into a memory cell is provided. The data programming circuit includes a control circuit and a current generating circuit. The control circuit generates a control signal according to the writing data. The current generating circuit provides a writing current to the memory cell to change a crystalline state of the memory cell. The writing current has a pulse width corresponding to the writing data, and the crystalline state corresponds to the writing data.
    Type: Grant
    Filed: November 21, 2008
    Date of Patent: October 4, 2011
    Assignee: Nanya Technology Corp.
    Inventors: Shyh-Shyuan Sheu, Lieh-Chiu Lin, Pei-Chia Chiang, Wen-Pin Lin
  • Phase-change memory and method of making same
    Patent number: 8026503
    Abstract: A phase-change memory cell structure includes a bottom diode on a substrate; a heating stem on the bottom diode; a first dielectric layer surrounding the heating stem, wherein the first dielectric layer forms a recess around the heating stem; a phase-change storage cap capping the heating stem and the first dielectric layer; and a second dielectric layer covering the first dielectric layer and the phase-change storage cap wherein the second dielectric layer defines an air gap in the recess.
    Type: Grant
    Filed: June 23, 2009
    Date of Patent: September 27, 2011
    Assignee: Nanya Technology Corp.
    Inventor: Li-Shu Tu
  • MATCHING METHOD OF PATTERN LAYOUTS FROM INVERSE LITHOGRAPHY
    Publication number: 20110207034
    Abstract: The present invention relates to a matching method of pattern layouts from inverse lithography, which makes the pattern cells in the same groups identical to avoid a repeated verification and to improve the yield. The method comprises the step of: analyzing a target designed layout by hierarchy; categorizing the pattern cells with the same shape into a group; inversing the target designed layout by inverse lithography; inspecting the inversed pattern cells in the group with each other and replacing the variant ones to make all the inversed pattern cells identical.
    Type: Application
    Filed: May 4, 2011
    Publication date: August 25, 2011
    Applicant: NANYA TECHNOLOGY CORP.
    Inventor: Kuo-Kuei Fu
  • Semiconductor structure and method for making the same
    Patent number: 8003528
    Abstract: A method for forming a semiconductor structure is provided. The method includes providing a substrate; forming a dielectric layer on the substrate; forming a conductor pattern on a main surface of the dielectric layer, the conductor pattern having a top surface and sidewalls; and performing a selective atomic layer deposition (ALD) process to selectively deposit a conformal metal layer onto the top surface and sidewalls of the conductor pattern, but without depositing onto the main surface of the dielectric layer substantially.
    Type: Grant
    Filed: June 15, 2010
    Date of Patent: August 23, 2011
    Assignee: Nanya Technology Corp.
    Inventors: Yi-Jen Lo, Yu-Shan Chiu, Kuo-Hui Su, Chiang-Hung Lin
  • Exposure method
    Patent number: 7998660
    Abstract: An exposure method is disclosed. A wafer coated with a photoresist layer having an exposure threshold dose is provided. The wafer has at least a central region and a peripheral region. Then, a compensating light beam having a first dose directs on the photoresist layer within the peripheral region. Next, a patterned light beam having a second dose is then projected, in a step-and-scan manner, onto the photoresist layer, thereby exposing the photoresist layer. The total dose of the first energy and the second energy is above than the exposure threshold dose.
    Type: Grant
    Filed: October 16, 2008
    Date of Patent: August 16, 2011
    Assignee: Nanya Technology Corp.
    Inventors: Chiang-Lin Shih, Kuo-Yao Cho
  • Method for forming a semiconductor device with a single-sided buried strap
    Patent number: 7993985
    Abstract: A method for forming a semiconductor device with a single-sided buried strap is provided.
    Type: Grant
    Filed: February 22, 2008
    Date of Patent: August 9, 2011
    Assignee: Nanya Technology Corp.
    Inventors: Neng-Tai Shih, Ming-Cheng Chang
  • Recessed-gate transistor device having a dielectric layer with multi thicknesses and method of making the same
    Patent number: 7994559
    Abstract: A recessed-gate transistor device includes a gate electrode embedded in a gate trench formed in a semiconductor substrate, wherein the gate trench includes a vertical sidewall and a U-shaped bottom. A source region is provided at one side of the gate trench within the semiconductor substrate. A drain region is provided at the other side thereof. An asymmetric gate dielectric layer is formed between the gate electrode and the semiconductor substrate. The asymmetric gate dielectric layer has a first thickness between the gate electrode and the drain region and a second thickness between the gate electrode and the source region, wherein the first thickness is thicker than the second thickness.
    Type: Grant
    Filed: July 2, 2008
    Date of Patent: August 9, 2011
    Assignee: Nanya Technology Corp.
    Inventors: Jer-Chyi Wang, Tieh-Chiang Wu, Chung-Yuan Lee, Jeng-Ping Lin
  • Circuit and method for controlling DRAM column-command address
    Patent number: 7990800
    Abstract: The present invention provides a circuit for controlling a column-command address corresponding to a specific column of a DRAM array. The circuit includes a control unit and a FIFO register. The control unit determines a period number, and synchronously produces an input pointer and an output pointer, wherein the output pointer is lagged behind the input pointer by the period number. The FIFO register utilizes the input pointer to store the column-command address, and utilizes the output pointer to output the column-command address.
    Type: Grant
    Filed: April 2, 2009
    Date of Patent: August 2, 2011
    Assignee: Nanya Technology Corp.
    Inventor: Yu-Wen Huang
  • Trench-type semiconductor device structure
    Patent number: 7985998
    Abstract: A trench-type semiconductor device structure is disclosed. The structure includes a semiconductor substrate, a gate dielectric layer and a substrate channel structure. The semiconductor substrate includes a trench having an upper portion and a lower portion. The upper portion includes a conductive layer formed therein. The lower portion includes a trench capacitor formed therein. The gate dielectric layer is located between the semiconductor substrate and the conductive layer. The substrate channel structure with openings, adjacent to the trench, is electrically connected to the semiconductor substrate via the openings.
    Type: Grant
    Filed: July 22, 2008
    Date of Patent: July 26, 2011
    Assignee: Nanya Technology Corp.
    Inventors: Shian-Jyh Lin, Ming-Cheng Chang, Neng Tai Shih, Hung-Chang Liao
  • Method of fabricating a memory cell
    Patent number: 7981743
    Abstract: The memory cell of the present invention has two independent storage regions embedded into two opposite sidewalls of the control gate respectively. In this way, the data storage can be more reliable. Other features of the present invention are that the thickness of the dielectric layers is different, and the two independent storage regions are formed on opposite bottom sides of the opening by the etching process and form a shape like a spacer. The advantage of the aforementioned method is that the fabricating process is simplified and the difficulty of self-alignment is reduced.
    Type: Grant
    Filed: February 29, 2008
    Date of Patent: July 19, 2011
    Assignee: Nanya Technology Corp.
    Inventors: Mao-Quan Chen, Ching-Nan Hsiao, Chung-Lin Huang
  • Semiconductor structure and method of making the same
    Patent number: 7982315
    Abstract: A semiconductor device is provided. An amorphous silicon layer that acts as a UV blocking layer replaces a conventional silicon-rich oxide (SRO) layer or the super silicon-rich oxide (SSRO) layer. By doing this, the process window is increased. In addition, silicon nitride sidewall spacer is formed inside the contact hole to prevent charge loss.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: July 19, 2011
    Assignee: Nanya Technology Corp.
    Inventors: Yinan Chen, Hsien-Wen Liu, Tzu-Ching Tsai
  • Matching method for designing layout patterns on a photomask from inverse lithography
    Patent number: 7984392
    Abstract: The present invention relates to a matching method of pattern layouts from inverse lithography, which makes the pattern cells in the same groups identical to avoid a repeated verification and to improve the yield. The method comprises the step of: analyzing a target designed layout by hierarchy; categorizing the pattern cells with the same shape into a group; inversing the target designed layout by inverse lithography; inspecting the inversed pattern cells in the group with each other and replacing the variant ones to make all the inversed pattern cells identical.
    Type: Grant
    Filed: January 5, 2009
    Date of Patent: July 19, 2011
    Assignee: Nanya Technology Corp.
    Inventor: Kuo-Kuei Fu
  • Method for manufacturing a memory
    Patent number: 7972924
    Abstract: A method for manufacturing a memory includes first providing a substrate with a horizontally adjacent control gate region and floating gate region which includes a sacrificial layer and sacrificial sidewalls, removing the sacrificial layer and sacrificial sidewalls to expose the substrate, forming dielectric sidewalls adjacent to the control gate region, forming a floating gate dielectric layer on the exposed substrate and forming a floating gate layer adjacent to the dielectric sidewalls and on the floating gate dielectric layer.
    Type: Grant
    Filed: July 19, 2010
    Date of Patent: July 5, 2011
    Assignee: Nanya Technology Corp.
    Inventors: Hung-Mine Tsai, Ching-Nan Hsiao, Chung-Lin Huang
  • Charge pump and charging/discharging method capable of reducing leakage current
    Patent number: 7961016
    Abstract: A charge pump includes a first transistor, a second transistor, a first, a second and a third selectors. The first transistor includes a gate electrode, a first electrode, and a second electrode which serves as an output port of the charge pump. The second transistor includes a gate electrode, a first electrode and a second electrode, where the gate electrode of the first transistor is coupled to the gate electrode of the second transistor, and the gate electrode of the second transistor is coupled to the second electrode of the second transistor. The first selector is utilized for selectively connecting the first transistor to a first supply voltage. The second selector is utilized for selectively connecting the first transistor to a second supply voltage. The third selector is utilized for selectively connecting the second transistor to the second supply voltage.
    Type: Grant
    Filed: July 9, 2009
    Date of Patent: June 14, 2011
    Assignee: Nanya Technology Corp.
    Inventor: Wen-Chang Cheng
  • Storage node of stack capacitor and fabrication method thereof
    Patent number: 7952127
    Abstract: A storage node structure includes a substrate having thereon a conductive block region; an etching stop layer covering the conductive block region; a conductive layer penetrating the etching stop layer and electrically connecting the conductive block region; an annular shaped conductive spacer on sidewall of the conductive layer, wherein the annular shaped conductive spacer is disposed on the etching stop layer and wherein the annular shaped conductive spacer and the conductive layer constitute a storage node pedestal; and an upper node portion stacked on the storage node pedestal.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: May 31, 2011
    Assignee: Nanya Technology Corp.
    Inventor: Hsiao-Ting Wu
  • Embedded bit line structure, field effect transistor structure with the same and method of fabricating the same
    Patent number: 7948027
    Abstract: An embedded bit line structure, in which, a substrate includes an insulator layer having an original top surface and a semiconductor layer on the original top surface of the insulator layer, and a bit line is disposed within the lower portion of the trench along one side of an active area. The bit line includes a first portion and a second portion. The first portion is located within the insulator layer and below the original top surface of the insulator layer. The second portion is disposed on the first portion to electrically connect the semiconductor layer of the active area. An insulator liner is disposed on the first portion of the bit line and between the second portion of the bit line and the semiconductor layer of the substrate opposite the active area for isolation. An STI is disposed within the trench to surround the active area for isolation.
    Type: Grant
    Filed: December 10, 2009
    Date of Patent: May 24, 2011
    Assignee: Nanya Technology Corp.
    Inventors: Shing-Hwa Renn, Cheng-Chih Huang, Yung-Meng Huang