Patents Assigned to Nanya Technology Corp.
  • Alignment mark arrangement and alignment mark structure
    Patent number: 8164753
    Abstract: An alignment mark arrangement includes: a first alignment pattern comprising a plurality of parallel first stripes on a substrate, wherein each of the first stripes includes a first dimension; and a second alignment pattern positioned directly above and overlapping with the first alignment pattern, the second alignment pattern including a plurality of parallel second stripes, wherein each of the second stripes of the second alignment pattern has a second dimension that is larger than the first dimension of each of the first stripes of the first alignment pattern.
    Type: Grant
    Filed: June 5, 2009
    Date of Patent: April 24, 2012
    Assignee: Nanya Technology Corp.
    Inventors: An-Hsiung Liu, Chun-Yen Huang, Ming-Hung Hsieh
  • Testing apparatus and method for testing a semiconductor devices array
    Patent number: 8164356
    Abstract: A testing apparatus and a method for testing a semiconductor devices array, which includes a plurality of rows and a plurality of columns, are provided. The testing apparatus includes a first testing circuit and a second testing circuit. The first testing circuit connects and transmits a clock signal, an input command signal and a data signal to at least one of the rows of the semiconductor devices array. The second testing circuit connects and transmits a selecting signal to at least one of the columns of the semiconductor devices array. Between two devices in a row, a difference in arrival times of the clock signal, a difference in arrival times of the input command signal, and a difference in arrival times of the data signal are equal.
    Type: Grant
    Filed: June 22, 2009
    Date of Patent: April 24, 2012
    Assignee: Nanya Technology Corp.
    Inventor: Chih Hui Yeh
  • Wafer back side grinding process
    Patent number: 8157621
    Abstract: A wafer back side grinding process. A workpiece comprising a first assembly having a first semiconductor wafer and a second assembly having a second semiconductor wafer is provided. A first back side of the first semiconductor wafer is grinded by using the second assembly as a carrier. Thereafter, a second back side of the second semiconductor wafer is grinded.
    Type: Grant
    Filed: October 12, 2009
    Date of Patent: April 17, 2012
    Assignee: Nanya Technology Corp.
    Inventor: Jen-Chung Chen
  • Magnetoresistive random access memory element and fabrication method thereof
    Patent number: 8149614
    Abstract: A magnetoresistive random access memory (MRAM) element includes a bottom electrode embedded in a first insulating layer; an annular reference layer in a first via hole of a second insulating layer on the first insulating layer, the annular reference layer being situated above the bottom electrode; a first gap fill material layer filling the first via hole; a barrier layer covering the annular reference layer, the second insulating layer and the first gap fill material layer; an annular free layer in a second via hole of a third insulating layer on the second insulating layer, the annular free layer being situated above the annular reference layer; and a top electrode stacked on the annular free layer.
    Type: Grant
    Filed: March 31, 2010
    Date of Patent: April 3, 2012
    Assignee: Nanya Technology Corp.
    Inventors: Chun-I Hsieh, Chang-Rong Wu
  • Semiconductor device with through substrate via
    Patent number: 8148824
    Abstract: A through substrate via having a low stress is provided. The through substrate via is positioned in a substrate. The through substrate via includes: an outer tube penetrating the substrate; at least one inner tube disposed within the outer tube; a dielectric layer lining on a side wall of the outer tube, and a side wall of the inner tube; a strength-enhanced material filling the inner tube; and a conductive layer filling the outer tube.
    Type: Grant
    Filed: April 16, 2010
    Date of Patent: April 3, 2012
    Assignee: Nanya Technology Corp.
    Inventor: Shian-Jyh Lin
  • Nonvolatile memory cell
    Patent number: 8148766
    Abstract: A nonvolatile memory cell is provided. A semiconductor substrate is provided. A conducting layer and a spacer layer are sequentially disposed above the semiconductor substrate. At least a trench having a bottom and plural side surfaces is defined in the conducting layer and the spacer layer. A first oxide layer is formed at the bottom of the trench. A dielectric layer is formed on the first oxide layer, the spacer layer and the plural side surfaces of the trench. A first polysilicon layer is formed in the trench. And a first portion of the dielectric layer on the spacer layer is removed, so that a basic structure for the nonvolatile memory cell is formed.
    Type: Grant
    Filed: October 2, 2008
    Date of Patent: April 3, 2012
    Assignee: Nanya Technology Corp.
    Inventors: Shin-Bin Huang, Ching-Nan Hsiao, Chung-Lin Huang
  • Integrated alignment and overlay mark
    Patent number: 8143731
    Abstract: An integrated alignment and overlay mark includes a pre-layer pattern for reticle-to-wafer registration implemented in an exposure tool, and a current-layer pattern incorporated with the pre-layer pattern. The pre-layer pattern and the current-layer pattern constitute an overlay mark for determining registration accuracy between two patterned layers on a semiconductor wafer.
    Type: Grant
    Filed: July 14, 2009
    Date of Patent: March 27, 2012
    Assignee: Nanya Technology Corp.
    Inventor: Chui-Fu Chiu
  • Die package structure
    Patent number: 8143712
    Abstract: A die package structure, which comprises: a first die; a second die; a core material layer, provided between the first die and the second die; at least one via, penetrating through the first die, the second die and the core material layer; a metal material, stuffing into the via, such that the first die the second die, and the core material layer can be electrically contacted with each other; at least a signal contacting unit, contacting the metal material; and a dielectric layer, enclosing the first die, including at least one breach exposing the signal contacting unit.
    Type: Grant
    Filed: July 15, 2010
    Date of Patent: March 27, 2012
    Assignee: Nanya Technology Corp.
    Inventor: Jen-Chung Chen
  • DRAM cell with double-gate fin-FET, DRAM cell array and fabrication method thereof
    Patent number: 8143121
    Abstract: A transistor structure includes a semiconductor substrate having a top surface and sidewalls extending downward from the top surface, wherein each of the sidewall comprises a vertical upper sidewall surface and a lower sidewall recess laterally etched into the semiconductor substrate. A trench fill dielectric region is inlaid into the top surface of the semiconductor substrate. Two source/drain regions are formed into the top surface of the semiconductor substrate and are sandwiched about the trench fill region. A buried gate electrode is embedded in the lower sidewall recess. A gate dielectric layer is formed on surface of the lower sidewall recess between the semiconductor substrate and the buried gate electrode.
    Type: Grant
    Filed: October 1, 2009
    Date of Patent: March 27, 2012
    Assignee: Nanya Technology Corp.
    Inventor: Shian-Jyh Lin
  • Temperature detector and the method using the same
    Patent number: 8123404
    Abstract: A temperature detector comprises a first current mirror, a second current mirror, a first pulse generator, a second pulse generator, a phase detector and a controller. The current of the first current mirror is in variation with temperature, but the current of the second current mirror is not. If the output pulse of the first pulse generator appears earlier than that of the second pulse generator, the controller enhances the output current of the second current mirror. If the output pulse of the first pulse generator appears later than that of the second pulse generator, the controller decreases the output current of the second current mirror.
    Type: Grant
    Filed: July 10, 2008
    Date of Patent: February 28, 2012
    Assignee: Nanya Technology Corp.
    Inventor: Wen Ming Lee
  • Semiconductor lithography process
    Patent number: 8124319
    Abstract: A semiconductor lithography process. A photoresist film is coated on a substrate. The photoresist film is subjected to a flood exposure to blanket expose the photoresist film across the substrate to a first radiation with a relatively lower dosage. The photoresist film is then subjected to a main exposure using a photomask to expose the photoresist film in a step and scan manner to a second radiation with a relatively higher dosage. After baking, the photoresist film is developed.
    Type: Grant
    Filed: April 12, 2010
    Date of Patent: February 28, 2012
    Assignee: Nanya Technology Corp.
    Inventors: Pei-Lin Huang, Chun-Yen Huang, Yi-Ming Wang
  • Signal receiver and voltage compensation method
    Patent number: 8106685
    Abstract: A signal receiver includes a first input terminal, a second input terminal, a first transistor, a second transistor and a variable load. The first and the second transistors each include a gate electrode, a first electrode and a second electrode. The gate electrode of the first transistor is coupled to the first input signal terminal, the gate electrode of the second transistor is coupled to the second input signal terminal, and the variable load is coupled to the first electrode of the first transistor, where a resistance of the first variable load is adjusted to make a DC level at an output node of the signal receiver keep a constant value.
    Type: Grant
    Filed: August 10, 2009
    Date of Patent: January 31, 2012
    Assignee: Nanya Technology Corp.
    Inventor: Wen-Chang Cheng
  • Dynamic enabling pump for power control
    Patent number: 8106702
    Abstract: A voltage generation system that can dynamically calibrate a time period for enabling the system includes: a voltage generation circuit, for providing an output voltage; an oscillator, coupled to the voltage generation circuit, for driving the voltage generation circuit to generate the output voltage at a specific frequency according to an enable signal; a limiter, coupled to the oscillator and the output voltage fed back from the voltage generation circuit, for generating the enable signal to the oscillator according to the output voltage; and an enable controller, coupled to the limiter, the oscillator, the voltage generation circuit and the enable signal generated by the limiter, for enabling the limiter, the oscillator and the voltage generation circuit according to an estimated time between enable signals, wherein the estimated time is dynamically calibrated.
    Type: Grant
    Filed: October 21, 2009
    Date of Patent: January 31, 2012
    Assignee: Nanya Technology Corp.
    Inventor: Ryan Andrew Jurasek
  • Bank re-assignment in chip to reduce IR drop
    Patent number: 8102690
    Abstract: A chip system that has reduced power consumption under specific operational modes includes: a DDR3 chip that includes: a plurality of pads, disposed at the center of the DDR3 chip; and an array of banks, each bank having a specific logical address, surrounding the pads. The chip system further includes: a clock, coupled to the DDR3 chip, for controlling a rate of data transmission; and a memory controller, coupled to the clock, for coordinating transmitted data with relevant processes, and for selectively reassigning the bank logical addresses according to a specific operational mode.
    Type: Grant
    Filed: October 12, 2009
    Date of Patent: January 24, 2012
    Assignee: Nanya Technology Corp.
    Inventors: Richard Michael Parent, Ryan Andrew Jurasek, Dave Eugene Chapmen
  • Electrical alignment mark set and method for aligning wafer stack
    Patent number: 8102064
    Abstract: An electrical alignment mark set and the method for using the same is disclosed. The electrical alignment mark set includes at least a top mark and a bottom mark. The top mark includes multiple pads disposed on a top wafer and having first pads and second pads, and a monitoring via electrically connected to the first pads. The bottom mark includes a first bottom pad corresponding to the monitoring via and a second bottom pad corresponding to the second pads. Further the first bottom pad and the second bottom pad are electrically connected to each other so that the monitoring via may be electrically connected to the second pads by means of the first bottom pad when the top mark and the bottom mark are aligned with each other.
    Type: Grant
    Filed: April 8, 2010
    Date of Patent: January 24, 2012
    Assignee: Nanya Technology Corp.
    Inventor: Shing-Hwa Renn
  • Apparatus and method for controlling delay stage of off-chip driver
    Patent number: 8098083
    Abstract: A multiple-finger off-chip driver (OCD) uses delay between branches of the output stage. The delay between branches is controlled using bias circuitry which compensates for process, temperature, and voltage (PVT) variations, resulting in less variation of slew rate at the output of the OCD. The OCD includes a time domain delay stage; a pre-driver stage; a final driver stage; and a bias circuit, for providing bias voltages to the time domain stage that compensate for process, temperature and voltage (PVT) variations on the time domain stage.
    Type: Grant
    Filed: April 2, 2009
    Date of Patent: January 17, 2012
    Assignee: Nanya Technology Corp.
    Inventors: Phat Truong, Mosaddiq Saifuddin, Chia-Jen Chang
  • Non-volatile memory cell and fabrication method thereof
    Patent number: 8089060
    Abstract: A non-volatile memory cell and a fabrication method thereof are provided. The non-volatile memory cell includes an anode; a cathode having a surface facing the anode; a specific structure disposed on the surface; and an ion conductor disposed among the anode, the cathode and the specific structure, wherein the specific structure is one of a bulging area on the surface of the cathode and an insulating layer with an opening.
    Type: Grant
    Filed: July 22, 2009
    Date of Patent: January 3, 2012
    Assignee: Nanya Technology Corp.
    Inventors: Chun-I Hsieh, Shih-Shu Tsai, Chang-Rong Wu
  • Signal adjusting system and signal adjusting method
    Patent number: 8085608
    Abstract: A signal adjusting system includes: a signal generating apparatus for transmitting a first driving signal and a second driving signal, a plurality of signal transmitting paths coupled to the signal generating apparatus, and a controlling apparatus coupled to the plurality of signal transmitting paths for receiving a first transmitted signal corresponding to the first driving signal and a second transmitted signal corresponding to the second driving signal, and detecting a phase difference between the first transmitted signal and the second transmitted signal to generate a detected result for the signal generating apparatus, wherein the signal generating apparatus adjusts a first driving ability of the first driving signal and a second driving ability of the second driving signal according to the detected result.
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: December 27, 2011
    Assignee: Nanya Technology Corp.
    Inventor: Wen-Chang Cheng
  • Flash memory cell and method for operating the same
    Patent number: 8077512
    Abstract: A flash memory cell according to the present invention includes a first charge-trapping region and a second charge-trapping region disposed in a semiconductor substrate, a first doped region disposed in the semiconductor substrate at a first side of the first charge-trapping region, a second doped region disposed in the semiconductor substrate at a second side of the first charge-trapping region, a first dielectric layer separating the semiconductor substrate from the first charge-trapping region and the second charge-trapping region, a first conductor disposed above the first charge-trapping region, and a second dielectric layer separating the first charge-trapping region from the first conductor, wherein the second charge-trapping region is configured to influence the conduction behavior of a carrier channel in the semiconductor substrate under the first charge-trapping region.
    Type: Grant
    Filed: August 18, 2009
    Date of Patent: December 13, 2011
    Assignee: Nanya Technology Corp.
    Inventor: Shing Hwa Renn
  • Dynamic current supplying pump
    Patent number: 8067978
    Abstract: A pump system that can dynamically increase its current capability includes: a pump circuit, for producing an output voltage; an oscillator, for driving the pump circuit to pump at a particular frequency according to a pump enable signal; a limiter, coupled to both the oscillator and the output voltage fed back from the pump circuit, for generating the pump enable signal to the oscillator according to the output voltage feedback signal; and an edge timer, coupled to both the oscillator and the pump enable signal, for driving the oscillator to operate at an increased frequency according to a threshold parameter of the pump enable signal.
    Type: Grant
    Filed: October 13, 2009
    Date of Patent: November 29, 2011
    Assignee: Nanya Technology Corp.
    Inventor: Ryan Andrew Jurasek