Patents Assigned to Nanya Technology Corp.
  • Three-dimensional package
    Patent number: 7948073
    Abstract: A three-dimensional package includes a carrier, a first die mounted on a first surface of the carrier, and a second die stacked on the first die. The first die includes first bond pads and second bond pads juxtaposed in separate two rows within a central region of the first die. The package further includes first bond fingers disposed on the first surface along a first side of the carrier, and second bond fingers along a second side opposite to the first side. A first bond wire is bonded to one of the first bond pads and extends to one the first bond fingers. The first bond wire overlies the row of the second bond pads. A second bond wire is bonded to one of the second bond pads and extends to one the second bond fingers. The second bond wire overlies the row of the first bond pads.
    Type: Grant
    Filed: March 19, 2009
    Date of Patent: May 24, 2011
    Assignee: Nanya Technology Corp.
    Inventor: Jen-Chung Chen
  • DRAM device having a gate dielectric layer with multiple thicknesses
    Patent number: 7948028
    Abstract: A transistor device employed in a support circuit of a DRAM includes a semiconductor substrate having thereon a gate trench, a recessed gate embedded in the gate trench, a source doping region disposed at one side of the recessed gate, a drain doping region disposed at the other side of the recessed gate, and a gate dielectric layer between the recessed gate and the semiconductor substrate. The gate dielectric layer has at least two thicknesses that render the high-voltage transistor device asymmetric. The thicker gate dielectric layer is between the recessed gate and the drain doping region, while the thinner gate dielectric layer is between the recessed gate and the source doping region.
    Type: Grant
    Filed: March 17, 2008
    Date of Patent: May 24, 2011
    Assignee: Nanya Technology Corp.
    Inventor: Shing-Hwa Renn
  • Conductive through connection and forming method thereof
    Patent number: 7943513
    Abstract: A conductive through connection having a body layer and a metal layer is disposed on a semiconductor device, which the metal layer is on a top of body layer and includes a conductive body configured to penetrate the body layer and the metal layer. The width/diameter of one end of the conductive body is larger than that of another end thereof. The shape of these two ends of the body layer can be rectangular or circular.
    Type: Grant
    Filed: July 21, 2009
    Date of Patent: May 17, 2011
    Assignee: Nanya Technology Corp.
    Inventor: Shian-Jyh Lin
  • Non-volatile memory cell and fabrication method thereof
    Patent number: 7943917
    Abstract: A non-volatile memory cell and the fabrication method thereof are provided. The non-volatile memory cell comprises a top electrode, a bottom electrode and an oxide layer disposed between the top electrode and the bottom electrode. The oxide layer comprises a relatively low oxygen content layer adjacent to the bottom electrode, a relatively high oxygen content layer adjacent to the top electrode, and a transition layer disposed between the relatively high and the relatively low oxygen content layers. The transition layer has an oxygen concentration within a range between those of the relatively high and the relatively low oxygen content layers.
    Type: Grant
    Filed: April 8, 2009
    Date of Patent: May 17, 2011
    Assignee: Nanya Technology Corp.
    Inventors: Chun-I Hsieh, Chang-Rong Wu
  • Low power synchronous memory command address scheme
    Patent number: 7940543
    Abstract: A method for dynamically enabling address receivers in a synchronous memory array includes: controlling all address receivers to initially be in an off state; generating a command signal and generating an address signal; delaying the address signal so there is a latency between the command signal and the address signal; and selectively turning on an address receiver corresponding to the address signal when the command signal is received by the synchronous memory array.
    Type: Grant
    Filed: March 19, 2008
    Date of Patent: May 10, 2011
    Assignee: Nanya Technology Corp.
    Inventors: Chia-Jen Chang, Phat Truong
  • Method for fabricating integrated circuit structures
    Patent number: 7939421
    Abstract: A method for fabricating an integrated circuit structure includes the steps of forming a second dielectric layer on a substrate including a first conductive layer and a first dielectric layer, forming the second dielectric layer on the first conductive layer and the first dielectric layer, forming a hole exposing the first conductive layer in the second dielectric layer, forming a barrier layer inside the hole, and forming a second conductive layer on the barrier layer. In one embodiment of the present invention, the forming of the barrier layer comprises the steps of forming a metal layer in the hole, and performing a treating process in an atmosphere including a plasma formed from a gas including oxidant to form a metal oxide layer on the metal layer.
    Type: Grant
    Filed: July 8, 2009
    Date of Patent: May 10, 2011
    Assignee: Nanya Technology Corp.
    Inventor: Chiang Hung Lin
  • DRAM positive wordline voltage compensation device for array device threshold voltage and voltage compensating method thereof
    Patent number: 7940549
    Abstract: The configurations of a DRAM positive wordline voltage compensation device and a voltage compensating method thereof are provided in the present invention. The proposed device includes a comparator having a first input terminal receiving a positive wordline voltage feedback signal, a second input terminal receiving a compensating reference of array device threshold voltage and an output terminal generating a first enable signal, an oscillator receiving the first enable signal and generating an oscillating signal when the first enable signal is active and a charge pump having a first input terminal receiving a second enable signal, a second input terminal receiving the oscillating signal and an output terminal generating a positive wordline voltage being a sum of a bitline high voltage, an array device threshold voltage and a voltage margin.
    Type: Grant
    Filed: October 5, 2009
    Date of Patent: May 10, 2011
    Assignee: Nanya Technology Corp.
    Inventors: Benjamin James Stembridge, Ryan Andrew Jurasek, Richard Michael Parent
  • Transistor structure and method of making the same
    Patent number: 7932555
    Abstract: A transistor structure includes a gate trench. The gate trench includes a bottle-shape bottom. The bottle-shape bottom includes a first conductive material wider than its top. The top includes a second material in a substrate, a gate structure on the gate trench and electrically connected to the first conductive material, a source/drain doping region adjacent to the gate trench and a gate channel between the source/drain doping region.
    Type: Grant
    Filed: December 4, 2007
    Date of Patent: April 26, 2011
    Assignee: Nanya Technology Corp.
    Inventors: Pei-Ing Lee, Shian-Jyh Lin
  • Mark for alignment and overlay, mask having the same, and method of using the same
    Patent number: 7933015
    Abstract: A mark for alignment and overlay, a mask having the same, and a method of using the same are provided. The mark includes a first mark pattern and a second mark pattern. The first mark pattern includes a first pattern and a second pattern, and the second mark pattern includes a third pattern and a fourth pattern. The first pattern includes a plurality of rectangular regions arranged in a first direction, and for each rectangular region, a sideline in a second direction is longer than a sideline in the first direction, wherein the first direction is perpendicular to the second direction. The second pattern is disposed on both sides of the first pattern in the second direction and includes a plurality of rectangular regions arranged in the second direction, and for each rectangular region, the sideline in the first direction is longer than a sideline in the second direction.
    Type: Grant
    Filed: February 22, 2008
    Date of Patent: April 26, 2011
    Assignee: Nanya Technology Corp.
    Inventors: Chui-Fu Chiu, Jung-Chih Kuo
  • METHOD FOR WRITING DATA TO MEMORY ARRAY
    Publication number: 20110085392
    Abstract: A method is provided for writing data to a memory array operating in synchronization with a clock signal having a transition edge. A data strobe signal having a transition edge corresponding to the transition edge of the clock signal is provided. The transition edge of the clock signal is used to relay the data corresponding to the transition edge of the data strobe signal if the transition edge of the data strobe signal is coming in earlier than the transition edge of the clock signal, wherein the clock signal has a rising edge and a falling edge, the data strobe signal has a rising edge and a falling edge respectively corresponding to the rising and the falling edges of the clock signal, and the transition edge of the clock signal is one of the rising and the falling edges of the clock signal.
    Type: Application
    Filed: October 14, 2009
    Publication date: April 14, 2011
    Applicant: NANYA TECHNOLOGY CORP.
    Inventors: Phat TRUONG, Tien Dinh LE
  • Semiconductor package structure with protection bar
    Patent number: 7923852
    Abstract: A semiconductor package structure includes a carrier, a chip or multi-chips mounted on a top surface of the carrier, a molding compound encapsulating the top surface and the chips, a plurality of solder balls distributed on a bottom surface of the carrier, and a protection bar formed of thermosetting plastic material formed on the bottom surface.
    Type: Grant
    Filed: February 3, 2009
    Date of Patent: April 12, 2011
    Assignee: Nanya Technology Corp.
    Inventor: Jen-Chung Chen
  • DRAM POSITIVE WORDLINE VOLTAGE COMPENSATION DEVICE FOR ARRAY DEVICE THRESHOLD VOLTAGE AND VOLTAGE COMPENSATING METHOD THEREOF
    Publication number: 20110080771
    Abstract: The configurations of a DRAM positive wordline voltage compensation device and a voltage compensating method thereof are provided in the present invention. The proposed device includes a comparator having a first input terminal receiving a positive wordline voltage feedback signal, a second input terminal receiving a compensating reference of array device threshold voltage and an output terminal generating a first enable signal, an oscillator receiving the first enable signal and generating an oscillating signal when the first enable signal is active and a charge pump having a first input terminal receiving a second enable signal, a second input terminal receiving the oscillating signal and an output terminal generating a positive wordline voltage being a sum of a bitline high voltage, an array device threshold voltage and a voltage margin.
    Type: Application
    Filed: October 5, 2009
    Publication date: April 7, 2011
    Applicant: NANYA TECHNOLOGY CORP.
    Inventors: Benjamin James STEMBRIDGE, Ryan Andrew JURASEK, Richard Michael PARENT
  • Mask and design method thereof
    Patent number: 7919216
    Abstract: A mask and the design method thereof are provided. The mask includes a light-shielding area shielding off a light, wherein the light-shielding area includes a photonic crystal having a lattice constant, and a ratio of the lattice constant to a wavelength of the light is a specific value within a band gap of the photonic crystal.
    Type: Grant
    Filed: November 13, 2008
    Date of Patent: April 5, 2011
    Assignee: Nanya Technology Corp.
    Inventors: Chia-Wei Lin, Teng-Yen Huang
  • Method of forming a trench capacitor
    Patent number: 7915133
    Abstract: A method of forming a ring-type capacitor is provided. The method includes providing a substrate; forming a patterned mask layer on the substrate, the patterned mask layer defining a ring pattern; removing the substrate by using the patterned mask layer as a mask to form a ring-type trench in the substrate; the ring-type trench including an inner wall and an outer wall; and forming a capacitor structure on the inner wall and the outer wall of the ring-type trench.
    Type: Grant
    Filed: December 10, 2007
    Date of Patent: March 29, 2011
    Assignee: Nanya Technology Corp.
    Inventors: Kuo-Yao Cho, Wen-Bin Wu, Chiang-Lin Shih, Jen-Jui Huang
  • Locally calibrated current source
    Patent number: 7915951
    Abstract: A microchip that can calibrate a plurality of circuits on the microchip with a current reference includes: at least a first circuit disposed on the microchip; at least a first local bias generation circuit, for generating a bias current that is input to the first circuit; an external current reference, coupled to the first local bias generation circuit, for updating the bias current; and a calibration logic, coupled to the first local bias generation circuit, for enabling the external current reference to update the bias current according to a valid calibration signal.
    Type: Grant
    Filed: November 2, 2009
    Date of Patent: March 29, 2011
    Assignee: Nanya Technology Corp.
    Inventor: Ryan Andrew Jurasek
  • Semiconductor device and method of manufacturing the same
    Patent number: 7911028
    Abstract: A semiconductor device including a metallic compound Hfx1Moy1Nz1 as an electrode. The work function of the electrode can be modulated by doping the metallic compound with dopants including nitrogen, silicon or germanium. The metallic compound of the present invention is applicable to PMOS, NMOS, CMOS transistors and capacitors.
    Type: Grant
    Filed: July 31, 2008
    Date of Patent: March 22, 2011
    Assignee: Nanya Technology Corp.
    Inventors: Shian-Jyh Lin, Chih-Wei Huang, Chao-Sung Lai, Hsing-Kan Peng
  • Delay line and memory control circuit utilizing the delay line
    Patent number: 7911859
    Abstract: A delay line includes at least one delay cell, wherein the delay line utilizes at least one of the at least one delay cell to delay an input signal for generating an output signal, and the at least one delay cell is implemented by a Pseudo NMOS transistor. In addition, a memory control circuit includes a delay locked loop (DLL) having at least one delay cell. The delay locked loop utilizes at least one of the at least one delay cell to delay an input signal for generating an output signal, and the at least one delay cell is implemented by a Pseudo NMOS transistor.
    Type: Grant
    Filed: March 24, 2009
    Date of Patent: March 22, 2011
    Assignee: Nanya Technology Corp.
    Inventor: Wei-Li Liu
  • External compensation for input current source
    Patent number: 7911262
    Abstract: An integrated circuit includes: a pre-driver stage, coupled to an external supply voltage, for controlling the final driver stage; a final driver stage, coupled to the pre-driver stage and the external supply voltage, for providing an output voltage; a compensation circuit, coupled to the pre-driver stage, for providing a bias voltage to the pre-driver stage that compensates for variation in the external supply voltage, to control current through the pre-driver stage; and a bias circuit, coupled to the external supply voltage and the compensation circuit, for providing a bias voltage as an input to the compensation circuit.
    Type: Grant
    Filed: March 29, 2009
    Date of Patent: March 22, 2011
    Assignee: Nanya Technology Corp.
    Inventors: Phat Truong, Pauline Mai, Chia-Jen Chang
  • FLASH MEMORY CELL AND METHOD FOR OPERATING THE SAME
    Publication number: 20110044100
    Abstract: A flash memory cell according to the present invention includes a first charge-trapping region and a second charge-trapping region disposed in a semiconductor substrate, a first doped region disposed in the semiconductor substrate at a first side of the first charge-trapping region, a second doped region disposed in the semiconductor substrate at a second side of the first charge-trapping region, a first dielectric layer separating the semiconductor substrate from the first charge-trapping region and the second charge-trapping region, a first conductor disposed above the first charge-trapping region, and a second dielectric layer separating the first charge-trapping region from the first conductor, wherein the second charge-trapping region is configured to influence the conduction behavior of a carrier channel in the semiconductor substrate under the first charge-trapping region.
    Type: Application
    Filed: August 18, 2009
    Publication date: February 24, 2011
    Applicant: NANYA TECHNOLOGY CORP.
    Inventor: Shing Hwa Renn
  • INTEGRATED CIRCUIT STRUCTURE AND MEMORY ARRAY
    Publication number: 20110042722
    Abstract: An integrated circuit structure includes a plurality of first doped regions disposed in a substrate in a matrix having odd columns and even columns each immediately adjacent to a corresponding one of the odd columns, a plurality of buried bit lines disposed in the substrate to electrically connect to the plurality of first doped regions of the same odd column in the matrix, and a plurality of surface bit lines disposed above an uppermost surface of the substrate, wherein each of the surface bit lines electrically connects to the first doped regions of the same even column in the matrix.
    Type: Application
    Filed: August 21, 2009
    Publication date: February 24, 2011
    Applicant: NANYA TECHNOLOGY CORP.
    Inventors: Shing Hwa Renn, Shian Jyh Lin