Abstract: A residual current (e.g. common-mode current) may be present in an isolated subsystem. The isolated subsystem may include the secondary winding of a transformer while a first subsystem may include the primary winding of the transformer. The first subsystem may also include a compensation circuit. A driver circuit may generate drive signals provided to the primary winding of the transformer and also to the compensation circuit. The compensation circuit may include a variable capacitor network (e.g. a variable capacitor diode network) that receives the drive signals and also receives a bias voltage, and generates a cancellation signal according to the drive signals and the bias voltage. The compensation circuit may provide the cancellation signal to the ground plane of the isolated subsystem through a capacitor that couples the variable capacitor diode network to the ground plane, in order to reduce or cancel the residual current present in the isolation subsystem.

Abstract: A method and system for scheduling a time critical task. The system may include a processing unit, a hardware assist scheduler, and a memory coupled to both the processing unit and the hardware assist scheduler. The method may include receiving timing information for executing the time critical task, the time critical task executing program instructions via a thread on a core of a processing unit and scheduling the time critical task based on the received timing information. The method may further include programming a lateness timer, waiting for a wakeup time to obtain and notifying the processing unit of the scheduling. Additionally, the method may include executing, on the core of the processing unit, the time critical task in accordance with the scheduling, monitoring the lateness timer, and asserting a thread execution interrupt in response to the lateness timer expiring, thereby suspending execution of the time critical task.

Abstract: System and method for validating a program under a specified model of computation. The model of computation may be related to the synchronous statechart model of computation. A program may be received that specifies a plurality of operations using a variable within a logical tick such that the variable has multiple values within the logical tick. The program may be statically analyzed according to a specified model of computation that specifies program execution based on logical ticks, which may include determining that the program has deterministic semantics that specify deterministic results for each logical tick during execution of the program, including specifying deterministic results of the plurality of operations performed within the logical tick. The program may be validated in accordance with the specified model of computation in response to the determining. Such techniques may allow validation of a larger set of programs than conventional models while maintaining deterministic results.

Abstract: Input terminal of a thermocouple (TC) instrument. The input terminal may include a printed circuit board (PCB), including an input portion configured to receive signals from a thermocouple, and an output portion configured to communicatively connect to the instrument. The input terminal may further include a sensor mounted on the PCB, configured to measure temperature at or near a cold junction of the input terminal. The PCB may include first traces connecting the input portion of the PCB to the output portion of the PCB, and configured to send TC signals to the TC instrument and second traces connecting the sensor to the output portion of the PCB, and configured to send temperature signals to the instrument. The traces may be configured to provide the TC signals and the temperature signals to the TC instrument without using metal pins.

Abstract: A system may include a processing unit executing program instructions (SW), a data acquisition (DAQ) hardware device for acquiring sample data and/or generating control signals, and host memory configured to store data samples and various data associated with the DAQ and processor operations. The DAQ device may push HW status information to host memory upon being triggered by predetermined events taking place in the DAQ device, e.g. timing events or interrupts, to avoid or reduce SW reads to the DAQ device. The DAQ device may update dedicated buffers in host memory with status data on any of these events. The status information pushed to memory may be read in a manner that allows detection of race conditions. Interrupts generated by the DAQ device may be similarly handled. Upon generating an interrupt, the DAQ device may gather information required to handle the interrupt, and push the information into system memory, along with information identifying the interrupt.

Abstract: Techniques are disclosed relating to implementation of LDPC encoding circuitry on a single integrated circuit (IC). In some embodiments, circuitry on a single IC includes message circuitry configured to receive or generate a message to be encoded, encode circuitry configured to perform low density parity check (LDPC) encoding on the message, noise circuitry configured to apply noise to the encoded message, and decode circuitry configured to perform LDPC decoding of the message. In some embodiments, the disclosed techniques may reduce production costs (e.g., by reducing overall chip area), facilitate LDPC testing, and/or provide multiple different functions relating to message transmission on a single chip.

Abstract: A wireless cellular base station includes M antennas and one or more processing devices. For each antenna, the antenna transmits a calibration pilot symbol over the air and the other M?1 antennas receive the calibration pilot symbol over the air. The processing devices select one of the M antennas as a reference antenna and for each antenna of the M antennas, the processing devices calculate channel reciprocity calibration coefficients of the antenna with respect to the reference antenna based on the received calibration pilot symbols.

Abstract: Techniques are disclosed relating to signaling and frame structure for massive MIMO communication systems. In some embodiments, an apparatus is configured to receive an uplink pilot symbol from a mobile device over a first channel and receive uplink data from the mobile device over the first channel, where the uplink data is included in one or more orthogonal frequency division multiplexing (OFDM) symbols at a symbol rate. In these embodiments, the apparatus is configured to, determine channel information based on the pilot symbol, precode downlink data based on the channel information, and transmit the precoded downlink data to the mobile device. In these embodiments, a transition interval between receiving the uplink pilot symbol and beginning to transmit the precoded downlink data corresponds to less than five OFDM symbols at the symbol rate. This may facilitate reciprocity-based precoding for fast-moving mobile devices, in some embodiments.

Abstract: Techniques for specifying and implementing programs. A graphical program is created in a graphical specification and constraint language that allows specification of a model of computation and explicit declaration of constraints in response to user input. The graphical program includes a specified model of computation, a plurality of interconnected functional blocks that visually indicate functionality of the graphical program in accordance with the specified model of computation, and specifications or constraints for the graphical program or at least one of the functional blocks in the graphical program. The specified model of computation and specifications or constraints are useable to analyze the graphical program or generate a program or simulation.

Abstract: Various embodiments are described of devices and associated methods for processing a signal using a plurality of vector signal analyzers (VSAs). An input signal may be split and provided to a plurality of VSAs, each of which may process a respective frequency band of the signal, where the respective frequency bands have regions of overlap. Each VSA may adjust the gain and phase of its respective signal such that continuity of phase and magnitude is preserved through the regions of overlap. The correction of gain and phase may be accomplished by a complex multiply with a complex calibration constant. A complex calibration constant may be determined for each VSA by comparing the gain and phase of one or more calibration tones generated with each region of overlap, as measured by each of the VSAs.

Abstract: System and method for editing a graphical diagram. A graphical diagram, such as a graphical program, is displayed on a display device. User input may be received editing the graphical diagram, thereby generating an edited graphical diagram. Placement of one or more elements in the graphical diagram may be adjusted in response to the editing based on determined forces applied to the one or more elements in the edited graphical diagram based on the said editing, resulting in an adjusted edited graphical diagram. The adjusted edited graphical diagram may be displayed on the display device, which may include displaying an animation illustrating the movement of the elements to an equilibrium state in which the forces balance and movement ceases. The editing, adjusting, and displaying may be performed sequentially and/or concurrently, as desired.

Abstract: System and method for editing a graphical diagram. A graphical diagram, such as a graphical program, is displayed on a display device. User input may be received editing the graphical diagram, thereby generating an edited graphical diagram. Placement of one or more elements in the graphical diagram may be adjusted in response to the editing based on determined forces applied to the one or more elements in the edited graphical diagram based on the said editing, resulting in an adjusted edited graphical diagram. The adjusted edited graphical diagram may be displayed on the display device, which may include displaying an animation illustrating the movement of the elements to an equilibrium state in which the forces balance and movement ceases. The editing, adjusting, and displaying may be performed sequentially and/or concurrently, as desired.

Abstract: Systems and methods for scheduling data egress from a network switch. Systems may include switch circuitry, a plurality of ports, and a plurality of queues. Each port may be associated with a respective set of routing information for network packets and each port may be configured with a respective set of egress periods. Each network packet may have respective routing information and a type that specifies a respective egress period. Each queue may be associated with a respective network packet type and a port of the plurality of ports.

Abstract: System and method for determining and conveying connectivity of cabled computer peripherals to a user. Characteristic information regarding each of multiple devices connected to a computer system in a system hierarchy of a bus networked system may be stored, including a device hierarchy associated with each device that identifies respective hardware nodes included in the device, and one or more visual attributes of the device. Respective system positions may be automatically determined for at least some of the devices based on the device hierarchy. A respective point of reference of at least one device may be determined based on the characteristic information of one or more of the devices. The computer system may generate information that indicates the respective system position of the at least one device relative to the respective point of reference of the device, which is useable to visually identify the device in the bus networked system.

Abstract: A design environment for FPGA applications enables configuration of an FPGA platform to include a user design and one or more interface units, which the user design can use to access one or more external modules/devices without needing any particular knowledge of the structure and operation of such modules/devices. The interface unit corresponding to an external device/module, under the control of an operating environment, can establish a communication between the user design and the external module/device. An external processing module can use an interface unit to monitor and/or control a user design.

Abstract: Techniques are disclosed relating to channel quality reporting for full-duplex (FD) wireless communications. In some embodiments an apparatus (e.g., a mobile device) is configured to receive a reference signal in a wireless communication and determine an effective signal to interference plus noise ratio (SINR) for FD communications based on a measured SINR of the reference signal and one or more self-interference cancelation levels. The apparatus may determine the one or more self-interference cancelation levels based on the transmit power of signals transmitted by the apparatus and residual power after SIC. The SIC levels may include both analog and digital SIC levels, which may be separately determined. One or more modulation and coding schemes may be determined based on the effective SINR. In some embodiments, multiple effective SINRs are determined for multiple different transmission modulation orders used by the apparatus.

Abstract: System and method for convergence analysis. One or more state variables of a first program may be determined based on dependencies of variables in a first program. A second program corresponding to the first program is created based on the state variables and their dependencies, and executed multiple times. Each execution may include recording values of the state variables, determining an execution count, comparing the values to corresponding values from previous executions of the second program, and terminating the executing in response to the values matching corresponding values from at least one previous execution of the second program. A convergence property for the first program is determined based on the execution count, and indicating a number of executions of the first program required to generate all possible values of the one or more variables. The convergence property is stored, and may be useable to optimize the first program.

Abstract: Embodiments are described of devices and methods for processing a signal using a plurality of vector signal generators (VSGs). A digital signal may be provided to a plurality of signal paths, each of which may process a respective frequency band of the signal, the respective frequency bands having regions of overlap. The gain and phase of each signal path may be adjusted such that continuity of phase and magnitude are preserved through the regions of overlap. The adjustment of gain and phase may be accomplished by a complex multiply with a complex calibration constant. The calibration constant may be determined for each signal path by comparing the gain and phase of one or more calibration tones generated within each region of overlap. Each signal path may comprise a VSG to convert the respective signal to an analog signal, which may be combined to obtain a composite signal.

Abstract: Techniques are disclosed related to determining delay in a radio frequency (RF) communications device configured to perform envelope tracking. The RF communications device may comprise a power amplifier and an envelope tracker. First and second input stimuli signals may be transmitted to each of the power amplifier and envelope tracker, respectively. The RF communications device may output, by the power amplifier, an output signal to a vector signal analyzer (VSA). The VSA may determine a first delay offset by cross-correlating the output signal with a reference signal, and the VSA may determine a second delay offset based on an amplitude distortion of the output signal. A relative delay between the first and second input stimuli signals may be determined based on a difference between the first and second delay offsets.

Abstract: An improved measurement system may include a source measure unit (SMU) capable of performing accurate low-level current measurements. Based on an SMU design that provides a controlled DC voltage source with precision current limiting and a controlled 0V (zero Volt) DC at the measurement terminal, an AC design may be implemented to establish the same (or very similar) conditions over a specified frequency range. Instead of controlling each digital-to-analog converter (DAC) at respective source terminals of the SMU as a respective DC output, each DAC may be controlled as a respective function generator with programmable frequency and continuously variable phase and amplitude. Off-the-shelf pipelined analog-to-digital converters (ADCs) may be used to monitor voltage, current and the voltage at the measurement terminal, and a Fourier transform may be used to obtain both the amplitude and relative phase measurements to be provided to respective control loops.