Abstract: System and method for configuring a system of heterogeneous hardware components, including at least one: programmable hardware element (PHE), digital signal processor (DSP) core, and programmable communication element (PCE). A program, e.g., a graphical program (GP), which includes floating point math functionality and which is targeted for distributed deployment on the system is created. Respective portions of the program for deployment to respective ones of the hardware components are automatically determined. Program code implementing communication functionality between the at least one PHE and the at least one DSP core and targeted for deployment to the at least one PCE is automatically generated. At least one hardware configuration program (HCP) is generated from the program and the code, including compiling the respective portions of the program and the program code for deployment to respective hardware components. The HCP is deployable to the system for concurrent execution of the program.

Abstract: System and method for performing correlation analysis. A program that includes multiple program structures and one or more data objects is stored. Each data object is shared by at least two of the program structures. For each program structure, decomposition effects on each of the data objects shared by the program structure resulting from each of a respective one or more optimizing transforms applied to the program structure are analyzed. One or more groups of correlated structures are determined based on the analyzing. Each group includes two or more program structures that share at least one data object, and at least one optimizing transform that is compatible with respect to the two or more program structures and the shared data object. For at least one group, the at least one optimizing transform is usable to transform the two or more program structures to meet a specified optimization objective.

Abstract: System and method for extending programmable device functionality while preserving functionality of the device driver and driver IP. User input may be received specifying functionality of custom IP for a programmable measurement device with standard driver IP. The custom IP may be generated accordingly, and may be deployable to the programmable measurement device. During operation the custom IP may communicate directly with the standard driver IP and may provide custom functionality of the programmable measurement device while preserving functionality of the standard driver IP on the programmable measurement device and the standard device driver.

Abstract: System and method for creating a graphical program. A first replication structure may be included in a graphical program, where the first replication structure specifies replication of any graphical program code inside the first replication structure. First graphical program code may be included inside the first replication structure. An implementation of the graphical program may be automatically generated, including generating multiple instances of an implementation of the first graphical program code within the implementation of the graphical program. Executing the graphical program may include executing the multiple instances, e.g., concurrently and/or serially.

Abstract: System and method for subsample time resolution signal alignment. First and second signals may be aligned by iteratively performing the following until a termination condition is met: current samples of the first and second signals may be acquired, a delayed copy of the current samples of the first signal may be generated and subtracted from the current samples of the first signal to generate a third signal, a delayed copy of the current samples of the second signal may be generated with a current subsample delay and subtracted from the current samples of the first signal to generate a fourth signal, and an alignment error may be generated based on the third and fourth signals and the current subsample may be delay adjusted accordingly. The iteratively adjusting may generate a subsample resolution delay aligning the second signal to the first signal. Subsequent samples the first signal and the second signal may be aligned and output per the subsample resolution delay.

Abstract: Techniques are disclosed relating to use of digital predistortion in the context of full-duplex radio. In some embodiments, an apparatus includes one or more antennas and is configured to simultaneously transmit and receive wireless signals via at least partially overlapping frequency resources using the one or more antennas. In some embodiments, the apparatus includes receive chain circuitry that is configured to process both wireless signals transmitted by the apparatus via the one or more antennas and over-the-air wireless signals from one or more other computing devices. In some embodiments, the apparatus includes one or more processing elements configured to determine one or more digital predistortion parameters based on the wireless signals transmitted by the apparatus via the one or more antennas and processed by the receive chain circuitry and apply predistortion to transmitted wireless signals based on the one or more digital predistortion parameters.

Abstract: A novel diagnostics and verifiable input/output (DVIO) channel may reduce fixed diagnostic circuitry and allow standard input/output channels to be repurposed as diagnostics for specific deployments. The DVIO channel may include a digital input sub-channel and a digital output sub-channel, with each sub-channel including basic protection and diagnostic circuitry for performing basic diagnostics. The two sub-channels may be used independently of each other, and they may also be coupled together to create an enhanced digital input or digital output channel, which is capable of performing more advanced diagnostics such as output readback or test pulse generation, for example. Multiple DVIO channels may be coupled together to create a multiple-channel digital input or digital output with redundant signal paths. In this way the input/output resources may be configured to meet the specific needs of a given application, and minimize the test and diagnostic circuitry required in traditional implementations.

Abstract: Techniques are disclosed relating to detection of wireless signals. In some embodiments, a method includes generating an autocorrelation result for a training field in a received wireless message, generating differentiation information based on the autocorrelation result, and determining that one or more signal recognition criteria are met. In some embodiments, the signal recognition criteria include a first criterion that a first peak in the differentiation information satisfies a first threshold for at least a first time interval. In some embodiments, the signal recognition criteria include one or more additional criteria, including a second criterion that a second peak in the differentiation information satisfies a second threshold for at least a second time interval, wherein the first and second peaks have different polarities and/or a third criterion that the first peak corresponds to an autocorrelation result value that is below a particular autocorrelation threshold.

Abstract: Systems and methods for mapping a time-based data acquisition (DAQ) to an isochronous data transfer channel of a network. A buffer associated with the isochronous data transfer channel of the network may be configured. A clock and a local buffer may be configured. A functional unit may be configured to initiate continuous performance of the time-based DAQ, transfer data to the local buffer, initiate transfer of the data between the local buffer and the buffer at a configured start time, and repeat the transferring and initiating transfer in an iterative manner, thereby transferring data between the local buffer and the buffer. The buffer may be configured to communicate data over the isochronous data transfer channel of the network, thereby mapping the time-based DAQ to the isochronous data transfer channel of the network.

Abstract: An improved counter may implement dynamic frequency measurement while also remaining fully backwards compatible with traditional frequency measurement methods. The counter may operate according to low-frequency, large range, and/or high frequency modes of operation. It may be programmable with a divisor value associated with the large range operating mode, and a measurement time associated with the high frequency mode of operation. The divisor and measurement time settings may be enabled or disabled, and when either setting is disabled, the counter becomes backwards compatible with traditional frequency measurement methods. The counter may also be provided with inputs representative of the desired type of measurement and the minimum and maximum expected values for the signal to be measured. The counter may perform the frequency measurement according to any one or more of the operating modes, and return a measurement result obtained in the operating mode that completes the measurement first.

Abstract: Provided is a method for processing data samples from a plurality of data channels. The method may include obtaining a plurality of data samples from the plurality of data channels. Obtaining the plurality of data samples may involve successively obtaining a data sample from each data channel of the plurality of data channels. Successively obtaining a data sample from each data channel may be performed a plurality of times during a specified time period. Each data sample of the plurality of data samples may be associated with a respective sample time, and each respective sample time may be relative to a single specified reference point in time. The method may further include, for each data sample of the plurality of data samples, determining a time-dependent coefficient value that may correspond to the sample time associated with the data sample, and applying the determined time-dependent coefficient value to the data sample.

Abstract: A fan noise suppression circuit may be coupled between a power source and a power input to at least one fan. The fan noise suppression circuit may include an adjustable current source coupled to the power source. The adjustable current source may provide a voltage output and a current output based on a power output of the power source. The fan noise suppression circuit may include a feedback controller coupled to an output of the adjustable current source. The feedback controller may be configured to compare the voltage output to a reference voltage and provide an error value to the adjustable current source, wherein the adjustable current source may adjust the current output based on the error value.

Abstract: System and method for controlling a custom modular measurement system. An editor may receive user input specifying one or more system definitions, each mapping message based commands, parameters, variables and/or metadata (“information”) accordant with a control protocol for standalone instruments to functions and data in a programming language, and generates the definitions accordingly, each being useable by a client application to interface with a custom modular measurement system that includes multiple logical instruments via the message based information. At least one of the definitions may be deployed onto the measurement system. A run-time engine of the measurement system may accept a message based command from the application, and call a corresponding function, which may invoke operation of at least one of the logical instruments. The logical instruments may be operated concurrently, including sharing use of a single physical measurement device by at least two of the logical instruments.

Abstract: Techniques relating to LDPC encoding. A set of operations is produced that is usable to generate an encoded message based on an input message. The set of operations corresponds to operations for entries in a smaller matrix representation that specifies locations of non-zero entries in an LDPC encoding matrix. A mobile device is configured with the set of operations to perform LDPC encoding. Circuitry configured with the set of operations performs LDPC encoding with high performance, relatively small area and/or low power consumption.

Abstract: Various embodiments are described of devices and associated methods for processing a signal using a plurality of vector signal analyzers (VSAs). An input signal may be split and provided to a plurality of VSAs, each of which may process a respective frequency band of the signal, where the respective frequency bands have regions of overlap. Each VSA may adjust the gain and phase of its respective signal such that continuity of phase and magnitude is preserved through the regions of overlap. The correction of gain and phase may be accomplished by a complex multiply with a complex calibration constant. A complex calibration constant may be determined for each VSA by comparing the gain and phase of one or more calibration tones generated with each region of overlap, as measured by each of the VSAs.

Abstract: A computing platform includes an array of interconnected field programmable gate arrays (FPGAs), memory, and external input/output interfaces. The platform is in the form of a blade conforming to the Advanced Telecommunications Computing Architecture (ATCA) standard. The platform is especially useful for telecommunications and networking applications.

Abstract: Right angle transition to circuit. A system includes a conductive plate, coaxial transmission line, a circuit, parallel to the conductive plate, and a right angle transition from the coaxial transmission line to the circuit. The transmission line includes a center pin protruding through a hole in the plate, an outer conductor formed by a conductive surface of the hole, and air dielectric between. The circuit includes a top conducting layer (TCL), ground plane with cutout, and an insulating substrate between the TCL and ground plane that abuts the pin. The transition includes the pin, a conductive element connecting the center pin to the TCL, the outer conductor, the air dielectric, the abutment of the substrate against the pin, and the cutout. The abutment and cutout minimize manufacturing variations regarding distance between the pin and the ground plane. The transition tunes out inductance introduced by bonding the pin to the TCL.

Abstract: A front-end converter circuit may allow devices, e.g. oscilloscopes and digitizers, to receive input signals having a wide range of possible amplitudes while maintaining a high standardized input impedance. The converter may selectively couple, using low-voltage switches, a selected input network of two or more input networks to a virtual ground node, and a selected feedback network of two or more feedback networks to a transconductance stage input. The selected input network and selected feedback network together define a respective input signal amplitude range. The converter may also controllably adjust an AC gain of the converter to match a DC gain of the converter, and selectively couple non-selected input networks to signal ground. Output referred integrated resistor thermal noise may be reduced to a desired value by lowering the value of the transconductance stage coupled across the input of the converter (through an input resistance) and the virtual ground node.

Abstract: System and method for debugging a graphical program. A graphical program may be received, e.g., from storage, from another process or device, etc. The program includes parallel graphical program portions, each portion including a graphical program structure and/or an execution path in the graphical program. A first graphical program portion of the parallel graphical program portions may be single step debugged, including executing the single step in the first graphical program portion, and executing, in the background, code in each of the other graphical program portions that is scheduled to execute between start and end of the single step in the first graphical program portion.

Abstract: Techniques are disclosed relating to configuring an interlock memory system. In one embodiment, a method includes determining a sequence of memory access requests for a program and generating information specifying memory access constraints based on the sequence of memory accesses, where the information is usable to avoid memory access hazards for the sequence of memory accesses. In this embodiment, the method further includes configuring first circuitry using the information, where the first circuitry is included in or coupled to a memory. In this embodiment, after the configuring, the first circuitry is operable to perform memory access requests to the memory corresponding to the sequence of memory accesses while avoiding the memory access hazards, without receiving other information indicating the memory access hazards.