Patents Assigned to National Taiwan University
  • Publication number: 20250151353
    Abstract: A method of forming a semiconductor device includes the following steps. A 2D material layer is formed over a bottom metal layer. A top metal layer is formed over the 2D material layer. An oxidation treatment is performed to the 2D material layer to form an oxide region interfacing both the 2D material layer and the top metal layer.
    Type: Application
    Filed: November 3, 2023
    Publication date: May 8, 2025
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Chao-Hsin Wu, Yu Ting Chao, Yu-Hsuan Lu, Ying-Chuan Chen
  • Patent number: 12291868
    Abstract: A retrofitting method for a beam with an opening is disclosed. The retrofitting method provides a hoop cooperated with an inclined stirrup to form a reinforcement set. The hoop is used to enclose the opening; and the reinforcement set may be selectively adjusted according to the distance between the edge of opening and a column face. The retrofitting method and reinforcement set are not only suitable for openings located in the non-plastic hinge zone of the beam, but also suitable for the openings located in the plastic hinge zone.
    Type: Grant
    Filed: August 31, 2022
    Date of Patent: May 6, 2025
    Assignee: NATIONAL TAIWAN UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Chien-Kuo Chiu, Min-Yuan Cheng, Chieh-Tzu Chou
  • Publication number: 20250142919
    Abstract: A semiconductor device includes a channel structure, source region, a drain region, metal gate structure, and a self-assembled layer. The source region and the drain region are on opposite sides of the channel structure. A bottom surface of the source region is lower than a bottom surface of the channel structure, and a top surface of the source region is higher than a top surface of the channel structure. The metal gate structure covers the channel structure and between the source region and the drain region. The self-assembled layer is between the source region and the metal gate structure. The self-assembled layer is in contact with the bottom surface of the channel structure but spaced apart from the top surface of the channel structure.
    Type: Application
    Filed: January 3, 2025
    Publication date: May 1, 2025
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY, NATIONAL TAIWAN NORMAL UNIVERSITY
    Inventors: Tung-Ying LEE, Tse-An CHEN, Tzu-Chung WANG, Miin-Jang CHEN, Yu-Tung YIN, Meng-Chien YANG
  • Publication number: 20250130211
    Abstract: A method of screening new psychoactive substance is provided, including providing a sample; placing the sample on chromatographic paper; ionizing the sample on the chromatographic paper by a direct analysis in real time (DART); performing a mass spectrometry analysis on the ionized sample to obtain a sample mass spectrum; and comparing a known standard mass spectrum with the sample mass spectrum, in which when a profile of the known standard mass spectrum is the same as a profile of the sample mass spectrum and the known standard mass spectrum is not exactly the same as the sample mass spectrum, the sample is determined to be the new psychoactive substance. A platform for screening new psychoactive substance is also provided to quickly screen out the new psychoactive substance.
    Type: Application
    Filed: February 8, 2024
    Publication date: April 24, 2025
    Applicant: National Taiwan University
    Inventors: Cheng-Chih Hsu, Wei-Hsin Hsu, Kai-Wen Cheng, Hsin-Bai Zou, Tzu-Hsuan Feng
  • Publication number: 20250131967
    Abstract: A method for forming a memory device is provided. The method includes forming first and second metal-insulator-semiconductor (MIS) structures, wherein each of the first and second MIS structures comprises a semiconductor layer, an insulating layer over the semiconductor layer, and a metal electrode layer over the insulating layer; performing a first breakdown process to the first MIS structure; performing a second breakdown process to the second MIS structure; performing a first read operation by supplying a reading voltage pulse to the metal electrode layer of the first MIS structure and detecting a first read current flowing through the first MIS structure; and performing a second read operation by supplying the reading voltage pulse to the metal electrode layer of the second MIS structure and detecting a second read current flowing through the second MIS structure, wherein the second read current is greater than the first read current.
    Type: Application
    Filed: October 19, 2023
    Publication date: April 24, 2025
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Jenn-Gwo HWU, Sung-Wei HUANG
  • Patent number: 12276029
    Abstract: Present invention is related to a metallic particle-deposition substrate having a metal substrate and multiple metallic particles attached thereon. The metallic particles are nano-particles with at least 90% of these nano-particles as single layer being evenly dispersed on the metal substrate. Each of the metallic particle is isolated without toughing or overlapping. The metal substrate has different material than the metallic particles in each preferred embodiment in the present invention. More preferably, at least 80% of the metallic particles have the distance between each metallic particle is at a range of 2-6 nm for better generation of hotspot effects. The present invention provides a fast production method for producing the substrate with heterogeneous interface. The metallic particles are evenly attached to the surface of the metal substrate to obtain better surface enhanced Raman effect as to apply for sensors in all kinds of field.
    Type: Grant
    Filed: May 11, 2022
    Date of Patent: April 15, 2025
    Assignee: National Taiwan University of Science and Technology
    Inventors: Bing-Joe Hwang, Wei-Nien Su, Meng-Che Tsai, Sheng-Chiang Yang
  • Patent number: 12272734
    Abstract: A semiconductor device includes a substrate, a semiconductor strip, an isolation dielectric, a plurality of channel layers, a gate structure, a plurality of source/drain structures, and an isolation layer. The semiconductor strip extends upwardly from the substrate and has a length extending along a first direction. The isolation dielectric laterally surrounds the semiconductor strip. The channel layers extend in the first direction above the semiconductor strip and arrange in a second direction substantially perpendicular to the substrate. The gate structure surrounds each of the channel layers. The source/drain structures are above the semiconductor strip and on either side of the channel layers. The isolation layer is interposed between the semiconductor strip and the gate structure and further interposed between the semiconductor strip and each of the plurality of source/drain structures.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: April 8, 2025
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., National Taiwan University
    Inventors: Yu-Shiang Huang, Chee-Wee Liu
  • Patent number: 12274078
    Abstract: A memory device includes a semiconductor substrate and a memory cell at a memory region of the semiconductor substrate. A memory cell includes a memory portion of the semiconductor substrate, a tunneling layer, a storage layer, a first electrode, and a second electrode. The tunneling layer is over the memory portion of the semiconductor substrate. The storage layer is over and in contact with the tunneling layer. The first electrode is over the storage layer. The second electrode is over and in contact with the tunneling layer but is spaced apart from the storage layer.
    Type: Grant
    Filed: February 2, 2023
    Date of Patent: April 8, 2025
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Jenn-Gwo Hwu, Bo-Jyun Chen, Kuan-Wun Lin
  • Publication number: 20250110133
    Abstract: Provided is a method for predicting drug efficacy of lung cancer, including providing a biological sample of a subject with lung cancer; analyzing an expression level of Leucine Zipper Down-regulated in Cancer 1; and predicting the drug efficacy based on the expression level of the Leucine Zipper Down-regulated in Cancer 1. Also provided is kit for predicting drug efficacy of lung cancer in a subject in need thereof, including an antibody against Leucine Zipper Down-regulated in Cancer 1 or a Leucine Zipper Down-regulated in Cancer 1-specific primer. Further provided is a method for treating lung cancer, including enhancing expression of Leucine Zipper Down-regulated in Cancer 1 encoded by Ldoc1 gene in a subject in need thereof.
    Type: Application
    Filed: September 26, 2024
    Publication date: April 3, 2025
    Applicants: National Health Research Institutes, National Taiwan University Hospital Hsin-Chu Branch
    Inventors: Chia-Huei Lee, Hsien-Neng Huang
  • Patent number: 12266602
    Abstract: A method includes forming an interlayer dielectric (ILD) layer over a transistor; forming a first inter-metal dielectric (IMD) layer over the ILD layer; etching a via opening extending through the first IMD layer; forming a first 2-D material layer lining along sides and a bottom of the via opening; depositing a first metal in the via opening and over the first 2-D material layer; performing a chemical mechanism polishing (CMP) process to the first metal until the first IMD layer is exposed; forming a second IMD layer over the first IMD layer; etching a trench in the second IMD layer; forming a second 2-D material layer lining along sides and a bottom of the trench; and depositing a second metal over the second 2-D material layer at a temperature lower than a temperature of depositing the first metal over the first 2-D material layer.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: April 1, 2025
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Shih-Yen Lin, Yu-Wei Zhang, Kuan-Chao Chen, Si-Chen Lee, Chi Chen
  • Patent number: 12257812
    Abstract: The metallic crystal structures inspired edge-to-edge tessellations and a tessellation based lattice structures are disclosed. In accordance with an exemplary embodiment of the invention, basic unit lattice cells are stacked and connected to constitute a three-dimensional tessellations, wherein each of the basic unit lattice cells comprises a multiple flat connecting portions formed on a surface of the basic unit lattice cell and intersecting with a multiple of axes intersecting in a center of the basic unit lattice cell, and the flat connecting portions of one of the basic unit lattice cell is connected to the flat connecting portions of the adjacent basic unit lattice cell to constitute a connection structure of edge-to-edge tessellation. The formed tessellations are periodically tessellated in a design domain to form different tessellated lattice structures. The Functionally Tessellated (FT) lattice structures composed of different tessellations by interlocking into each other are also disclosed.
    Type: Grant
    Filed: February 18, 2022
    Date of Patent: March 25, 2025
    Assignee: National Taiwan University of Science and Technology
    Inventors: Chinmai Bhat, Ajeet Kumar, Jeng-Ywan Jeng
  • Patent number: 12260320
    Abstract: A method is disclosed to dynamically design acceleration units of neural networks. The method comprises steps of generating plural circuit description files through a neural network model; reading a model weight of the neural network model to determine a model data format of the neural network model; selecting one circuit description file from the plural circuit description files according to the model data format, so that the chip is reconfigured according to the selected circuit description file to form an acceleration unit adapted to the model data format. The acceleration unit is suitable for running a data segmentation algorithm, which may accelerate the inference process of the neural network model. Through this method the chip may be dynamically reconfigured into an efficient acceleration unit for the different model data format, thereby speeding up the inference process of the neural network model.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: March 25, 2025
    Assignee: NATIONAL TAIWAN UNIVERSITY OF SCIENCE & TECHNOLOGY
    Inventors: Shun-Feng Su, Meng-Wei Chang
  • Publication number: 20250098279
    Abstract: A method includes forming a semiconductive channel structure over a substrate. A semiconductive layer is deposited over the semiconductive channel structure. The semiconductive layer and the semiconductive channel structure includes different materials. An oxidation process is performed to the semiconductive layer to form an oxidation layer over a remaining portion of the semiconductive layer. The oxidation layer is heated after the oxidation process is performed. A gate structure is formed over the oxidation layer.
    Type: Application
    Filed: November 27, 2024
    Publication date: March 20, 2025
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Minghwei HONG, Juei-Nai KWO, Tun-Wen PI, Hsien-Wen WAN, Yi-Ting CHENG, Yu-Jie HONG
  • Publication number: 20250089575
    Abstract: A method includes epitaxially growing a Ge1-xSnx channel layer over a substrate. The Ge1-xSnx channel layer is in a metastable state. A Ge1-ySny barrier layer is epitaxially grown over the Ge1-xSnx channel layer to form a two-dimensional hole gas in the Ge1-xSnx channel layer. The Ge1-xSnx channel layer and the Ge1-ySny barrier layer are etched to form a first opening and a second opening in the Ge1-xSnx channel layer and the Ge1-ySny barrier layer. A first source/drain electrode and a second source/drain electrode are deposited in the first opening and the second opening, respectively. A gate electrode is formed over the Ge1-ySny barrier layer.
    Type: Application
    Filed: September 11, 2023
    Publication date: March 13, 2025
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Jiun-Yun LI, Yu-Jui WU, Chia-You LIU, Chia-Tse TAI, Tsung-Ying LI
  • Publication number: 20250087486
    Abstract: A method of forming a semiconductor device includes forming a semiconductor strip extending above a semiconductor substrate, forming shallow trench isolation (STI) regions on opposite sides of the semiconductor strip, recessing a portion of the semiconductor strip, etching the STI regions to form a recess in the STI regions, forming a first thermal conductive layer in the recess, forming a source/drain epitaxy structure on the first thermal conductive layer, and forming a gate stack across the semiconductor strip and extending over the STI regions.
    Type: Application
    Filed: November 22, 2024
    Publication date: March 13, 2025
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Chia-Che CHUNG, Chia-Jung TSEN, Chee-Wee LIU
  • Publication number: 20250087482
    Abstract: A device includes gate spacers, a gate dielectric layer, and one or more gate metals. The gate spacers are over a substrate. The gate dielectric layer is between the gate spacers. The gate dielectric layer includes a horizontal portion extending parallel to a top surface of the substrate, and vertical portions extending upwards from the horizontal portion. A first one of the vertical portions has a thickness less than a thickness of the horizontal portion.
    Type: Application
    Filed: November 22, 2024
    Publication date: March 13, 2025
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY, NATIONAL TAIWAN NORMAL UNIVERSITY
    Inventors: Chun-Yi CHOU, Po-Hsien CHENG, Tse-An CHEN, Miin-Jang CHEN
  • Patent number: 12246753
    Abstract: Various embodiments for systems and methods for cooperative driving of connected autonomous vehicles using responsibility-sensitive safety (RSS) rules are disclosed herein. The CAV system integrates proposed RSS rules with CAV's motion planning algorithm to enable cooperative driving of CAVs. The CAV system further integrates a deadlock detection and resolution system for resolving traffic deadlocks between CAVs. The CAV system reduces redundant calculation of dependency graphs.
    Type: Grant
    Filed: March 16, 2022
    Date of Patent: March 11, 2025
    Assignees: Arizona Board of Regents on Behalf of Arizona State University, National Taiwan University
    Inventors: Mohammad Khayatian, Mohammadreza Mehrabian, Harshith Allamsetti, Kai-Wei Liu, Po-Yu Huang, Chung-Wei Lin, Aviral Shrivastava
  • Patent number: 12249367
    Abstract: A device is provided. The device includes a memory cell and a first write assist circuit. The memory cell operates with a first supply voltage and a second supply voltage different from the first supply voltage. The first write assist circuit includes a first write assist switch and a second write assist switch that are coupled to the memory cell through a first data line. In a write operation of a data, having a first logic value, to the memory cell, the first write assist switch transmits the first supply voltage to the first data line in response to a first control signal, received at a control terminal of the first write assist switch and having a voltage level of the second supply voltage, when the second write assist switch is configured to be turned off.
    Type: Grant
    Filed: April 13, 2022
    Date of Patent: March 11, 2025
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Chia-Che Chung, Hsin-Cheng Lin, Chee-Wee Liu
  • Patent number: 12247916
    Abstract: Provided is an identification method of plastic microparticles, including: performing an infrared analysis on plastic microparticles to identify whether the plastic microparticles include polyethylene terephthalate, polyethylene, polypropylene, or nylon 66, wherein the identification is to determine whether the plastic microparticles have a characteristic peak of each plastic, and the characteristic peak is selected from signals that do not overlap and interfere with each other in the infrared spectrum signals of each plastic.
    Type: Grant
    Filed: June 7, 2022
    Date of Patent: March 11, 2025
    Assignee: National Taiwan University
    Inventors: Chihhao Fan, Jhen-Nan Lin, Jun-Wei Li, Ya-Zhen Huang
  • Patent number: 12247908
    Abstract: A detection device and a detection method for distinguishing types of particles in an aqueous solution are provided. The detection device includes a detection chip, a signal source and a processing device. The detection chip includes a substrate, a coplanar waveguide transmission line and a super-hydrophobic film mask. When a to-be-detected aqueous solution that contains to-be-detected particles is provided on the detection chip, the super-hydrophobic film mask of the detection chip can confine the to-be-detected aqueous solution in a detection area. The processing device controls the signal source to provide detection microwave signals with different detection frequencies, simultaneously measures a first output signal and a second output signal at the different detection frequencies to generate a to-be-detected absorption spectrum, and compares the to-be-detected absorption spectrum with historical absorption spectra, so as to determine types of the to-be-detected particles.
    Type: Grant
    Filed: June 1, 2022
    Date of Patent: March 11, 2025
    Assignee: NATIONAL TAIWAN UNIVERSITY
    Inventors: Chi-Kuang Sun, Peng-Jui Wang