Patents Assigned to National Taiwan University
  • Publication number: 20250030162
    Abstract: The present invention is a reconfigurable antenna, which includes a total reflection part, a partial reflection part, a partial transmission part, and a radiation part stacked in sequence. A resonant cavity is formed between the partial reflection part and the total reflection part. The radiation part is arranged in the resonant cavity. So that the electromagnetic wave radiated by the radiation part is reflected in the resonant cavity. The electromagnetic wave forms constructive interference during the reflection of the resonant cavity. The resonant cavity makes the electromagnetic wave form the same phase electromagnetic wave and radiation penetrating the reflection part. The partial transmission part is regulated to form beam reconstruction conditions, and the same-phase electromagnetic waves are formed into beams and radiated into space by the beam control conditions.
    Type: Application
    Filed: July 19, 2023
    Publication date: January 23, 2025
    Applicant: National Taiwan University
    Inventors: Yi-Cheng LIN, Ching-Mei WANG, Chang-Kai LAI
  • Patent number: 12206148
    Abstract: The invention discloses a filter device. The filter device comprises a substrate, at least one transmission conductor, and a reference conductor having a slotted structure. The substrate is provided at a first surface thereof with the transmission conductor, and provided at a second surface thereof with the reference conductor. The slotted structure comprises a frame portion, a slotted portion, and a hollow portion. The slotted portion surrounds the frame portion, and the hollow portion is formed in the frame portion. At least one impedance unit is configured on the frame portion. The equivalent filter circuit of the filter device is formed between the transmission conductor, the slotted structure, the reference conductor, and the impedance unit. Thereby, the equivalent filter circuit absorbs at least one noise at at least one specific frequency by the impedance unit to avoid the noise reflected to affect the transmission quality of signal.
    Type: Grant
    Filed: December 10, 2021
    Date of Patent: January 21, 2025
    Assignee: National Taiwan University
    Inventors: Tzong-Lin Wu, Hsu-Wei Liu, Chi-Hsuan Cheng, Po-Jui Li
  • Patent number: 12198340
    Abstract: Provided are a system and a method for cardiovascular risk prediction, where artificial intelligence is utilized to perform segmentation on non-contrast or contrast medical images to identify precise regions of the heart, pericardium, and aorta of a subject, such that the adipose tissue volume and calcium score can be derived from the medical images to assist in cardiovascular risk prediction. Also provided is a computer readable medium for storing a computer executable code to implement the method.
    Type: Grant
    Filed: May 31, 2022
    Date of Patent: January 14, 2025
    Assignee: NATIONAL TAIWAN UNIVERSITY
    Inventors: Tzung-Dau Wang, Wen-Jeng Lee, Yu-Cheng Huang, Chiu-Wang Tseng, Cheng-Kuang Lee, Wei-Chung Wang, Cheng-Ying Chou
  • Patent number: 12198305
    Abstract: The present disclosure relates to a data processing method, and more specifically, to a digital image processing method to enable a rapid noise-suppressed contrast enhancement in an optical linear or nonlinear microscopy imaging application. The disclosed method digitally mimics a hardware-based feedback-driven adaptive or controlled illumination technique by means of digitally resembling selective laser-on and laser-off states so as to selectively optimize the signal strength and hence the visibility of the weak-intensity morphologies while mostly preventing saturation of the brightest structures.
    Type: Grant
    Filed: May 30, 2022
    Date of Patent: January 14, 2025
    Assignee: National Taiwan University
    Inventors: Chi-Kuang Sun, Bhaskar Jyoti Borah
  • Publication number: 20250015141
    Abstract: A semiconductor device includes a substrate, a first dielectric layer, a channel layer and source/drain electrodes. The first dielectric layer is over the substrate. The channel layer is over the first dielectric layer. Source/drain electrodes are over the channel layer. The source/drain electrodes comprise a 2D semimetal material. The channel layer comprises a 2D semiconductor material interfacing the 2D semimetal material of the source/drain electrodes.
    Type: Application
    Filed: July 7, 2023
    Publication date: January 9, 2025
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Jian-Zhi HUANG, Yu-Tung LIN, En-Cheng CHANG, Ting-Ying CHIU, I-Chih NI, Chih-I WU
  • Patent number: 12191144
    Abstract: A method includes forming a mask layer above a substrate. The substrate is patterned by using the mask layer as a mask to form a trench in the substrate. An isolation structure is formed in the trench, including feeding first precursors to the substrate. A bias is applied to the substrate after feeding the first precursors. With the bias turned on, second precursors are fed to the substrate. Feeding the first precursors, applying the bias, and feeding the second precursors are repeated.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: January 7, 2025
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY, NATIONAL TAIWAN NORMAL UNIVERSITY
    Inventors: Chun-Yi Chou, Po-Hsien Cheng, Tse-An Chen, Miin-Jang Chen
  • Patent number: 12191145
    Abstract: A method of forming a semiconductor device includes forming a semiconductor strip extending above a semiconductor substrate, forming shallow trench isolation (STI) regions on opposite sides of the semiconductor strip, recessing a portion of the semiconductor strip, etching the STI regions to form a recess in the STI regions, forming a first thermal conductive layer in the recess, forming a source/drain epitaxy structure on the first thermal conductive layer, and forming a gate stack across the semiconductor strip and extending over the STI regions.
    Type: Grant
    Filed: June 7, 2022
    Date of Patent: January 7, 2025
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Chia-Che Chung, Chia-Jung Tsen, Chee-Wee Liu
  • Patent number: 12191205
    Abstract: A method includes forming a semiconductive channel layer on a substrate. A dummy gate is formed on the semiconductive channel layer. Gate spacers are formed on opposite sides of the dummy gate. The dummy gate is removed to form a gate trench between the gate spacers, resulting in the semiconductive channel layer exposed in the gate trench. A semiconductive protection layer is deposited in the gate trench and on the exposed semiconductive channel layer. A top portion of the semiconductive protection layer is oxidized to form an oxidation layer over a remaining portion of the semiconductive protection layer. The oxidation layer is annealed after the top portion of the semiconductive protection layer is oxidized. A gate structure is formed over the semiconductive protection layer and in the gate trench after the oxidation layer is annealed.
    Type: Grant
    Filed: March 3, 2022
    Date of Patent: January 7, 2025
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Minghwei Hong, Juei-Nai Kwo, Tun-Wen Pi, Hsien-Wen Wan, Yi-Ting Cheng, Yu-Jie Hong
  • Patent number: 12191143
    Abstract: A plasma enhanced chemical vapor deposition (PECVD) method includes loading a wafer having a magnetic layer thereon into a processing chamber equipped with a radio frequency (RF) system, introducing an aromatic hydrocarbon precursor into the processing chamber, and turning on an RF source of the RF system to decompose the aromatic hydrocarbon precursor into active radicals at a frequency greater than about 1000 Hz to form a graphene layer over the magnetic layer.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: January 7, 2025
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Jian-Zhi Huang, Yun-Hsuan Hsu, I-Chih Ni, Chih-I Wu
  • Patent number: 12188862
    Abstract: A microscope is provided to measure HbA1c fraction. The microscope measures the HbA1c fraction of a single red blood cell (RBC) in a trace blood sample. The HbA1c fraction can be measured through a non-invasive way while the RBC flows in a human epidermal microvessel, too. The microscope comprises a laser device, an upright microscope, a light splitter, a light detector, and a mainframe. Unlike traditional methods, the HbA1c fraction can be measured in vitro or in vivo at the level of a single RBC. Accurate measurement is achieved. Misdiagnosis rate is reduced. The microscope provides HbA1c fractions from hundreds of RBCs, instead of averaging HbA1c fractions obtained from a large number of blood samples. Hence, the present invention is a method of detecting a HbA1c fraction of a single RBC, and is a microscope supporting blood-drawing measurement and non-invasive measurement simultaneously.
    Type: Grant
    Filed: February 24, 2023
    Date of Patent: January 7, 2025
    Assignee: National Taiwan University
    Inventors: Chi-Kuang Sun, Xu-hao Ye
  • Patent number: 12191226
    Abstract: A semiconductor device and method for forming same. According to an embodiment. The method provides a base substrate, forms a heat dissipation substrate on the base substrate, wherein a thermal conductivity of the heat dissipation substrate is between 200 Wm?1K?1 and 1200 Wm?1K?1. This method further forms a device layer on the heat dissipation substrate, wherein the device layer comprises a transistor. The method further removes the base substrate.
    Type: Grant
    Filed: January 17, 2023
    Date of Patent: January 7, 2025
    Assignees: MEDIATEK INC., NATIONAL TAIWAN UNIVERSITY
    Inventors: Ming-Tzong Yang, Hsien-Hsin Lin, Wen-Kai Wan, Chia-Che Chung, Chee-Wee Liu
  • Publication number: 20250006639
    Abstract: A method includes loading a wafer having a dielectric layer thereon into a processing chamber; introducing a hydrocarbon precursor into the processing chamber; pyrolyzing the hydrocarbon precursor; introducing the pyrolyzed hydrocarbon precursor to the dielectric layer to form a graphene layer on the dielectric layer at a temperature lower than about 400° C.
    Type: Application
    Filed: July 1, 2023
    Publication date: January 2, 2025
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Chi-Yuan KUO, Jia-Heng ZHU, I-Chih NI, Chih-I WU
  • Publication number: 20250007179
    Abstract: Disclosed are a dual-polarization cavity-backed antenna, a package module and an array package module. The antenna includes a substrate, a magnetic current feeding structure, an electric current feeding structure, and a cavity-backed structure that is arranged between two surfaces of the substrate. The magnetic current feeding structure and the electric current feeding structure transfer energy into the cavity-backed structure, respectively radiating the orthogonally polarized electromagnetic wave. The electric field direction of the first electromagnetic wave and the magnetic field direction of the second electromagnetic wave occur on the same plane. The package module includes the dual-polarization cavity-backed antenna, a radio frequency control chip, and a control circuit unit. The array package module includes a plurality of the dual-polarization cavity-backed antennas, a radio frequency control unit including a single RF chip or chip set, and a control circuit unit.
    Type: Application
    Filed: June 29, 2023
    Publication date: January 2, 2025
    Applicant: National Taiwan University
    Inventors: Yi-Cheng LIN, Tzu-Ming HUANG
  • Patent number: 12170227
    Abstract: A device includes a bottom transistor, a top transistor, and an epitaxial isolation structure. The bottom transistor includes a first channel layer, first source/drain epitaxial structures, and a first gate structure. The first source/drain epitaxial structures are on opposite sides of the first channel layer. The first gate structure is around the first channel layer. The top transistor is over the bottom transistor and includes a second channel layer, second source/drain epitaxial structures, and a second gate structure. The second source/drain epitaxial structures are on opposite sides of the second channel layer. The second gate structure is around the second channel layer. The epitaxial isolation structure is between and in contact with one of the first source/drain epitaxial structures and one of the second source/drain epitaxial structures, such that the one of the first source/drain epitaxial structures is electrically isolated from the one of the second source/drain epitaxial structures.
    Type: Grant
    Filed: September 26, 2023
    Date of Patent: December 17, 2024
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Chien-Te Tu, Hsin-Cheng Lin, Chee-Wee Liu
  • Publication number: 20240404951
    Abstract: A method includes forming a semiconductor device over a front-side of a substrate, the semiconductor device comprising a channel region, a gate structure across the channel region, and source/drain regions on the channel region and at opposite sides of the gate structure; forming a first source/drain contact on a first one of the source/drain regions; forming a front-side interconnect structure over the first source/drain contact; forming a first dielectric through-silicon via extending through the substrate from a cross-sectional view, the first dielectric through-silicon via overlapping the first source/drain contact from a top view; forming a back-side interconnect structure over a back-side of the substrate, wherein the first dielectric through-silicon via has a back-side surface in contact with the back-side interconnect structure.
    Type: Application
    Filed: June 1, 2023
    Publication date: December 5, 2024
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Chia-Che CHUNG, Chia-Jung TSEN, Chee-Wee LIU
  • Patent number: 12160998
    Abstract: The disclosure is directed to spin-orbit torque MRAM structures and methods. A SOT channel of the SOT-MRAM includes multiple heavy metal layers and one or more dielectric dusting layers each sandwiched between two adjacent heavy metal layers. The dielectric dusting layers each include discrete molecules or discrete molecule clusters of a dielectric material scattered in or adjacent to an interface between two adjacent heavy metal layers.
    Type: Grant
    Filed: July 22, 2022
    Date of Patent: December 3, 2024
    Assignees: Taiwan Semiconductor Manufacturing Co., Ltd., National Taiwan University
    Inventors: Zong-You Luo, Ya-Jui Tsou, I-Cheng Tung, CheeWee Liu
  • Patent number: 12157267
    Abstract: A large area deposition type additive manufacturing equipment is disclosed. The large area deposition type additive manufacturing equipment includes a light source module, a dynamic photomask module, a raw material tank and a deposition module. The light source module includes a plurality of light emitting members, a light diffusion member, a light enhancement member and a light emitting angle limiter. Light emitted from the light emitting members passes through the light diffusion member, the light enhancement member and the light emitting angle limiter to become a collimated curing light. The collimated curing light travels through a transparent member of the raw material tank and a dynamic photomask module to reach liquid photocurable material in the raw material tank, thereby curing the liquid photocurable material. The angle of emitted light ranges within ±30° with respect to a normal line of an incident plane of the light source module.
    Type: Grant
    Filed: May 29, 2022
    Date of Patent: December 3, 2024
    Assignee: National Taiwan University of Science and Technology
    Inventors: Jeng-Ywan Jeng, Ding-Zheng Lin, Ping-Hung Yu, Yu-Cheng Chen
  • Publication number: 20240395892
    Abstract: A semiconductor device includes a substrate, a semiconductor strip, an isolation dielectric, a plurality of channel layers, a gate structure, a plurality of source/drain structures, and an isolation layer. The semiconductor strip extends upwardly from the substrate and has a length extending along a first direction. The isolation dielectric laterally surrounds the semiconductor strip. The channel layers extend in the first direction above the semiconductor strip and arrange in a second direction substantially perpendicular to the substrate. The gate structure surrounds each of the channel layers. The source/drain structures are above the semiconductor strip and on either side of the channel layers. The isolation layer is interposed between the semiconductor strip and the gate structure and further interposed between the semiconductor strip and each of the plurality of source/drain structures.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 28, 2024
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Yu-Shiang HUANG, Chee-Wee LIU
  • Publication number: 20240395936
    Abstract: A semiconductor device includes a first layer that includes a first semiconductor material disposed on a semiconductor substrate, and a second layer of a second semiconductor material disposed on the first layer. The semiconductor substrate includes Si. The first semiconductor material and the second semiconductor material are different. The second semiconductor material is formed of an alloy including a first element and Sn. A surface region of an end portion of the second layer at both ends of the second layer has a higher concentration of Sn than an internal region of the end portion of the second layer. The surface region surrounds the internal region.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 28, 2024
    Applicants: Taiwan Semiconductor Manufacturing Company, Ltd., NATIONAL TAIWAN UNIVERSITY
    Inventors: Fang-Liang LU, I-Hsieh WONG, Shih-Ya LIN, CheeWee LIU, Samuel C. PAN
  • Publication number: 20240397836
    Abstract: A method includes following steps. A bottom electrode layer is formed over a substrate. A first deposition sequence is performed over the bottom electrode layer. The first deposition sequence comprises pulsing a first precursor over the bottom electrode layer such that the first precursor comprises a first plurality of precursor molecules adsorbing on the bottom electrode layer, performing a first purge after pulsing the first precursor, performing a first plasma treating step using a first treatment gas, wherein the first treatment gas reacts with the first plurality of precursor molecules to form a first monolayer of a film, the film has an Al—N bond with a first intensity, pulsing the first treatment gas, and after pulsing the first treatment gas, performing a second plasma treating step using a second treatment gas such that the film has an Al—N bond with a second intensity.
    Type: Application
    Filed: September 25, 2023
    Publication date: November 28, 2024
    Applicants: Taiwan Semiconductor Manufacturing Company, Ltd., NATIONAL TAIWAN UNIVERSITY
    Inventors: Chen-Hsiang LING, Miin-Jang CHEN