Abstract: Delay-independent cycle-based logic simulation of synchronous digital circuits with levelized compiled code simulation has substantially increased speed. Sweep, eliminate, and factor reduce the number of literals. The use of cofactoring, a register allocation and spill scheme, an inverter minimization scheme, and retiming further reduce the simulation time for two and four valued simulation. A shift minimization scheme reduces time in four-valued simulation. The faster simulation is embodied in a method, a computer system, and a computer program product.

Abstract: A power management method and system targeted toward high-level synthesis of data-dominated behavioral descriptions. The method of the present invention is founded on the observation that variable assignment can significantly affect power management opportunities in the synthesized architecture. Based on this observation, a procedure for constraining variable assignment is provided so that the functional units in the synthesized architecture do not execute any spurious operations.

Abstract: A method and apparatus for verifying a query to provide feedback to users for query reformulation. By utilizing selectivity statistics for semantic and visual characteristics of image objects, query verification “examines” user queries and allows users to reformulate queries through system feedback. Feedback information provided to the user includes (1) the maximum and minimum number of matches for the query; (2) alternatives for both semantic and visual-based query elements; and (3) estimated numbers of matching images. Additional types of feedback information may also be provided. With this feedback, the users know if the query criteria is too tight (i.e. too few matches will be retrieved) or too loose (i.e. too many matches will be retrieved) so that they can relax, refine, or reformulate queries or leave queries unchanged accordingly. Only after queries are verified to have a high possibility of meaningful results, are the queries processed.

Abstract: A complete procedure for verifying register-transfer logic against its scheduled behavior in a high-level synthesis environment is provided. A new method that is both complete and practical for verification is provided. Hardware verification is known to be a hard problem and the proposed verification technique leverages off the fact that high-level synthesis--performed manually or by means of high-level synthesis software--proceeds from the algorithmic description of the design to structural RTL through a sequence of very well defined steps, each limited in its scope. Equivalence checking task is partitioned into two simpler subtasks, verifying the validity of register sharing, and verifying correct synthesis of the RYL interconnect and control. While state space traversal is unavoidable for verifying validity of the register sharing, irrelevant portions of the design are automatically abstracted out, significantly simplifying the task that must be performed by a back-end model checker.

Abstract: A scanner has an optical-electric module, an incoherent fiber bundle, and a scanner head. The incoherent fiber bundle has illumination fibers and pickup fibers. The illumination fibers carry only illumination light from a light source in the O/E module toward the scanner head. The pickup fibers carry sensed light from the scanner head to a CCD array in the O/E module. The scanner head has a light guide that receives the illumination light from the illumination fibers. The light guide is in contact with the pickup fibers in an arrangement which permits the illumination light to enter the side of the illumination fibers near the end. Illumination light reflected back into the pickup fibers is guided to the CCD array.

Abstract: A method for fast static compaction in sequential circuits with finite output states by removing subsequences of test vectors from a vector test set. The method has the following steps: (1) relaxing the output states of the sequential circuits; (2) identifying a candidate subsequence of test vectors from the vector test set for removal; (3) temporarily removing the candidate subsequence of test vectors from the vector test set; (4) performing fault simulation on remaining test vectors from the vector test set; (5) examining fault simulation results against a set of removal criteria; (6) permanently removing the temporarily removed candidate subsequence if said set of removal criteria are met; (7) replacing the temporarily removed candidate subsequence if said set of removal criteria are not met; and (8) repeating steps (1) through (7) until all candidate subsequences of test vectors have been identified.

Abstract: Alternative routing schemes in high-speed networks ensure fault tolerance in the event of a link failure. An heuristic algorithm, based on maximal-flow algorithm, is first used to partition the network into parts: one part carries regular or primary traffic and another part is reserved to carry re-routed traffic in the event of a link failure. The result of applying the algorithm is used to find alternative routes for a given call at the time of call setup. The scheme can be modified to accommodate hop-court limitations and loop avoidance.

Abstract: A method, system and a computer product for a new partial scan technique that incurs significantly less overhead than the full-scan technique and yet achieves very high test coverage in short CPU times are provided. Scan memory elements are selected so that the scanned circuit satisfies two key properties in the test mode. First, the scanned circuit has partitions that are peripherally interacting finite state machines (peripheral partitions). Second, the memory element dependency graph (S-graph) of each peripheral partition of the scanned circuit has a tree structure. An efficient for algorithm peripheral partitioning and tree decomposition is provided. The scan memory element selection algorithm iteratively partitions the S-graph into disjoint sub-graphs with the tree structure.

Abstract: A low-overhead controller-based power management technique that re-specifies control signals to reconfigure existing multiplexer networks and functional units to minimize unnecessary activity. Though the control signals in an RT-level implementation are fully specified, they can be re-specified under certain states/conditions when the data path components that they control need not be active. Another aspect of this invention is an algorithm to perform power management through controller re-specification, that consist of constructing an activity graph for each data path component, identifying conditions under which the component need not be active, and re-labeling the activity graph resulting in re-specification of the corresponding control expressions. The algorithm avoids the above negative effects of controller re-specification.

Abstract: A hand-held optical scanner for reading color images formed on a document. The scanner head is all-optical and contains no electronics. Optical fiber bundles couple the scanner head to a remote opto-electronic module containing a linear or a 2D sensor array for converting optical signals, reflected from the document, to electrical signals for transmission to a computer display, etc. By using side coupling, the transmitted and reflected light for each pixel travels through the same optical fiber without the need for a beam splitter. The optical fibers are used for the functions of image scanning, position encoding, and signaling a computer which assigns each one of incoherently arranged optical fibers to one of the functions.

Abstract: Disclosed is a weighted longest queue first (WLQF) service discipline for ATM networks. The sources are classified so that sources in one class have the same cell loss probability requirement. For N classes of traffic the WLQF system has N buffers to store the traffic, wherein buffer i is assigned a positive number w.sub.i for the weight of buffer i. The scheduler transmits a cell from that buffer whose index maximizes w.sub.i Q.sub.i for i=1, 2, . . . ,N, where Q.sub.i is the queue length of buffer i at the moment when the scheduler makes a decision about which buffer to serve. Accordingly, the inventive system always serves the most congested buffer relative to the weighted queue lengths, and can adapt to temporary overload quickly. This feature ensures that in temporary overloads of one of the buffers, the overloaded buffer, receives almost all the service and therefore, losses due to buffer overflows and cell delay variation (CDV) are much small.

Abstract: A Network Interface Card (NIC) for integrating computers and other electronic equipment to a Wireless Asynchronous Transfer Mode (WATM) network is constructed so as to efficiently exchange data between a host and the wireless network. In addition to providing both ATM and AAL layer transfer protocols, the NIC also provides Data Link Control (DLC), Media Access Control (MAC), and Radio Physical (RPhy) layers as well.

Abstract: There is disclosed a decentralized flow control technique based on microeconomics. In this framework, there are three important entities: switches, network brokers and users. Switches independently price their resources to provide flow control and to encourage high utilization. A network broker, located at the entrance of the network, works as an agent for a user, monitoring the budget, prices and needs. Using this information the network broker may purchase resources to maximize the user's quality of service. This approach has several advantages such as: decentralized control, minimal signaling, Pareto-optimal resource distribution, price stability and high network utilization.

Abstract: A multi-class connection admission control (CAC) method that supports cell loss and delay requirements. In this model-based CAC, the source traffic is described in terms of the usage parameter control (UPC) parameters. Through analysis and approximations, simple closed-form methods to calculate the bandwidth required to meet guarantees on quality of service (QoS) are used. In addition to being robust, the CAC achieves a high level of resource utilization and can be easily implemented for real-time admission control.

Abstract: A Boolean SAT solver uses reconfigurable hardware to solve a specific input problem. Each of the plurality of ordered variables has a corresponding one of a plurality of state machines. Each state machine has an implication circuit for its respective variable, and operates in parallel according to an identical state machine. One state machine implements the Davis-Putnam method in hardware and provides improved performance over software by virtue of the parallel checking of direct and transitive implications. Another state machine implements a novel non-chronological backtracking method that takes advantage of the parallel implication checking and avoids the need to maintain or to traverse a GRASP type implication graph in the event of backtracking. The novel non-chronological backtracking provides for setting a blocking variable as a leaf variable and for changing only the value of the leaf variable, but possibly changing both the value and identity of a backtracking variable.

Abstract: The Complete-1-Distinguishability (C-1-D) property is used for simplifying FSM verification. This property eliminates the need for a traversal of the product machine for the implementation machine and the specification machine. Instead, a much simpler check suffices. This check consists of first obtaining a 1-equivalence mapping between the states of the two machines, and then checking that it is a bisimulation relation. The C-1-D property can be used directly on specifications for which it naturally holds. This property can be enforced on arbitrary FSMs by exposing some of the latch outputs as pseudo-primary outputs during synthesis and verification. In this sense, the synthesis/verification methodology provides another point in the tradeoff curve between constraints-on-synthesis versus complexity-of-verification.

Abstract: A data bypass system diverts data calls to a central office based modem bank and a data network at the subscriber's discretion. The data call diversion is based on a data service prefix in the user's dialing string. The data bypass device translates a subsequent telephone address of a data service supplier into a data network address. The data bypass system is either analog or digital and has a line card with a switch that selectively connects the subscriber line to the voice switch or to a data switch or router through two respective concentrators. The line card includes a data call prefix detector that controls the switch in response to a data call prefix that precedes a data call telephone number.

Abstract: A computer system, computer program product, and method for solving a combinational logic verification problem with respect to two combinational circuits includes Boolean SAT checking integrated with binary decision diagrams (BDD) use. A fanout partition of a miter circuit formed from the two combinational circuits is reduced to BDD form, while the fanin partition is represented by SAT clauses. As SAT solutions are evaluated, variables in the cutset between the fanout and fanin partitions are assigned values. In a preferred embodiment, each assignment to a cutset variable is checked against an onset of the BDD prior to continuing with SAT solution seeking.

Abstract: A handoff control process in a wireless ATM network replaces an old communications connection with a new communication connection. In order to guarantee that no data is lost during the replacement process, an ATM cell level mechanism is used to re-schedule the buffering and transmitting of data streams of the virtual channels (VCs) to be handed-off. In addition, this mechanism is transparent to user applications. The present invention performs three fundamental cell level scheduling functions. The first function is to mark and redirect cell transmission with operation and maintenance (OAM) cells. The second function is to disable and buffer cell transmission until the new path is connected. The third function is to enable cell transmission, starting with the buffered cells across the connected new path.

Abstract: A method to identify and test primitive faults in combinational circuits described as multi-level or two-level netlists. A primitive fault is a multiple path delay for which none of the single paths contained in the fault is robustly or non-robustly testable while the presence of the fault will degrade the circuit performance. Identification and testing of primitive faults is important for at least two reasons: (1) a large percentage of paths in production circuits remain untestable under the single-path delay fault model, (2) distributed manufacturing defects usually adversely affect more than one path and these defects can be detected only by analyzing multiple affected paths. The single-path delay faults contained in a primitive fault have to merge at some gate(s). The methodology for identifying primitive faults can quickly (1) rule out a large number of gates as possible merging points for primitive faults, and (2) reduce or prune the combination of paths that can never belong to any primitive fault.