Abstract: A technique for static compaction of test sequences is described. The method for static compaction according to the present invention includes two key features: (1) two-phase vector restoration, and (2) identification, pruning, and re-ordering of segments. Segments partition the compaction problem into sub-problems. Segments are identified, dynamically pruned and re-ordered to achieve further compaction and speed up.

Abstract: Methods of compacting sequential circuit test vector set by partitioning of faults into hard and easy faults, re-ordering vectors in a test set by moving sequences that detect hard faults to the beginning of the test set, and a combination of partitioning and re-ordering.

Abstract: Mobility in a wireless ATM network is accomplished by use of hand-off control protocols. A mobile terminal signals a first base station that a hand-off is to occur. In a first preferred embodiment the first base station signals a second base station requesting a hand-off. After the second base station signals the first base station that a datapath link is available from a hand-off switch to the second base station, the hand-off switch causes the datapath to change from the first base station to the second base station and the first base station signals the mobile terminal to commence communication with the second base station. In a second preferred embodiment, the mobile terminal signals a first base station that a hand-off is to occur. The first base station signals a second base station requesting a hand-off. At the same time a datapath link is established between the first and second base stations.

Abstract: A synchronous test model (STM) and corresponding method capture the essential behavior of an asynchronous circuit under test. During operation of the method, (1) An STM for the asynchronous circuit is constructed assuming either a user-specified cycle length or an estimated cycle length; (2) a target fault list is created containing only faults in the asynchronous circuit, (3) test patterns are generated from the STM using a synchronous test generator; (4) the test patterns are translated into test sequences for the asynchronous circuit; and (5) the translated patterns are validated by fault simulation on the asynchronous circuit.

Abstract: In compiled code simulation, a circuit to be simulated is converted or compiled into an executable so that running the executable produces the same output response as the circuit itself. In a binary decision diagram (BDD)-based compiled code simulator, the simulation executable for the circuit is derived from a BDD-based characteristic function representation of the circuit rather than by the heretofore used translation of Boolean operations in the original circuit into machine instructions.

Abstract: A computer implemented method for searching and retrieving images contained within a database of images in which both semantic and cognitive methodologies are utilized. The method accepts a semantic and cognitive description of an image to be searched from a user, and successively refines the search utilizing semantic and cognitive methodologies and then ranking the results for presentation to the user.

Abstract: An optical fiber that controllably taps and distributes light propagating through an the optical fiber that comprises an optical fiber having multiple regions each having a different index of refraction from one another such that when light traverses the optical fiber along a length it travels from a region of one index of refraction to another region having a different index of refraction the light is sufficiently deflected such that it is distributed out a side of the optical fiber along its length. In a preferred embodiment, at point in the length of the fiber where a change in index of refraction occurs, light traversing the fiber is efficiently diverted out of the optical fiber through the side of the fiber. The light so diverted alternatively is refracted by one or more refractive regions, and alternatively focused by prism films applied to the exit side of the fiber where it may then be put to an advantageous use.

Abstract: A method for transporting Internet Protocols (IP's) over an Asynchronous Transfer Mode (ATM) network that exhibits the strengths of ATM, namely packet interleaving (using cell-based transport) with Quality of Service support for connection-oriented traffic (such as multiclass native ATM traffic and flows-based IP traffic using RSVP), while optimizing the connectionless requirements of existing IP traffic. Advantageously, both the IP protocol stack and ATM protocol stack operate as peers over ATM cell transport hardware. The method exploits an "implicit" signaling/control phase characteristic of IP traffic/protocols thereby minimizing setup. The implicit signaling phase is used to map a flow from a routed path to a switched path immediately upon transmission of a first packet. Similarly, particular packets may be immediately transported over the routed path even after establishment of the switched path.

Abstract: A queue management method for a wireless asynchronous transfer mode Network Interface Card (NIC) for integrating computers and other electronic equipment to a Wireless Asynchronous Transfer Mode (WATM) network is constructed so as to efficiently exchange data between a host and the wireless network. In addition to providing both ATM and AAL layer transfer protocols, the NIC also provides Data Link Control (DLC), Media Access Control (MAC), and Radio Physical (RPhy) layers as well.

Abstract: A method to significantly accelerate sequential test generation algorithms by accurately computing signal constraints for large sequential circuits and using these constraints effectively during deterministic sequential test generation. The signal constraint computation technique is based on three key ideas: (1) unlike prior techniques (which compute line probabilities assuming only a 0 or 1 value for any signal), line probabilities are computed by allowing signals to assume values other than 0 or 1, (2) line justification techniques are employed to update line probabilities, and (3) symbolic simulation is iteratively used in conjunction with line probability computation and line justification to refine the set of values that a signal can assume. The method results in a significant reduction (more than 50%) in test generation time which is achieved without comprising the fault coverage than can be obtained.

Abstract: Low power linear digital signal processing circuits are fabricated based on a design synthesis process using activity metrics. The average activity value .theta..sub.i of all the input nodes of the circuit is determined. Architectural transformations of the circuit are performed in order to minimize the average activity value over all the nodes. The transformation resulting in the minimum activity value is the synthesized design used as the basis for fabricating a low power linear digital signal processing circuit.

Abstract: TES (Transform-Expand-Sample) is a versatile class of stationary stochastic processes which can model arbitrary marginals, a wide variety of autocorrelation functions, and a broad range of sample path behaviors. An algorithmic method replaces the previously relied upon heuristic search, thereby automating TES modeling for simulation analysis. The algorithm is solved in a nonlinear programming setting, which takes advantage of fast and accurate computation of TES autocorrelation functions and their partial derivatives to implement a steepest-descent technique, preferably based on Zoutendijk's Feasible Direction Method. The method has particular application to data compression and specifically compressed video.

Abstract: An alternative method for testing circuits (H-SCAN) which retains the main advantage of full scan testing, namely, the ability to use combinational automatic test pattern generation (ATPG), while eliminating the high area overhead the long test application time associated with full, scan test methods. The method provides a practical test methodology that can be easily applied to any RT-level specification. The method uses existing connections of registers and other structures available in a high-level specification of a circuit without necessitating the use of scan flip-flops. Test application time is reduced by using the parallelism inherent in the circuit design to load multiple flip-flops in a single clock cycle, without having to add parallel scan chains as done in traditional parallel scan approaches.

Abstract: A breadth-first manipulation of reduced, ordered binary decision diagram representation of a logic circuit eliminates page access time bottlenecks encountered when obtaining nodes from secondary memory to primary memory by providing an orderly page access arrangement. The pointer to a node is the address at which the node is located in memory, from which address the memory block at which the node is located is determined. A look-up table is used to convert the memory block information into a variable index indicative of the level at which the node is located. The queue of ITE (if.sub.-- then.sub.-- else) requests is maintained on a per level basis.

Abstract: A rate based feedback congestion control at an ATM switch for ABR vservice is based upon the state of the switch queue fill. Individual ABR virtual channels are informed of an explicit rate at which the virtual channels are allowed to transmit cells.

Abstract: A method of circuit synthesis which considers all circuit configurations that can be designed utilizing a retiming with logic duplication (RLD) methodology. These circuit configurations (RLD configurations) each have significantly different area, performance and testability characteristics and are represented as a set of feasible solutions to an integer linear program (ILP). The ILP permits the evaluation of different design and testability metrics for each of the configurations. An approach to solve several useful special cases of the ILP in polynomial time and an application of RLD transformation to partial scan is shown. Using this method, a desired RLD configuration is produced having a minimal number of duplicated logic nodes.

Abstract: A new dynamic process for test sequence compaction and test cycle reduction that identifies bottlenecks that prevent vector compaction and test cycle reduction for test sequences generated initially and generates subsequent test sequences with the aim of eliminating bottlenecks of the initially generated test sequences. To apply the process to sequential circuits, a sliding anchor frame technique is used that involves specifying the unspecified bits of a partially specified test sequence to detect other faults.

Abstract: A multimedia communications and computer platform that can serve as a network interface card combined with an internal distribution network for a full range of user terminal devices. It includes an interconnection network module that serves to route all incoming and outgoing information by way of high speed buses with value added features for communication protocol acceleration. In particular, attached to the different ports of the network are an ATM module, a communications processor, a media processor and a variety of terminal devices. By migrating processing intensive functions of network protocol termination, media stream distribution and media stream adaptation into the network interface card, there are avoided the bottlenecks of the traditional CPU centric approach to ATM systems.

Abstract: A data link control procedure for wireless ATM access channels based on a dynamic TDMA/TDD framework provides integrated ATM services including available bit-rate (ABR) data and constant/variable bit-rate (CBR/VBR) voice or video through the addition of wireless-specific medium access control and data link control protocol layers between the physical and ATM network layers. Generally, a data link control is used to insulate the ATM network layer from wireless channel impairments by selective retransmission of erroneous or lost cells before they are released to the ATM layer. The data link control methods disclosed use the on-demand ABR burst transmission capability of the dynamic TDMA channel to retransmit unacknowledged cells in available slots not allocated to service data. Specific error recovery procedures for both (asynchronous) ABR and (isochronous) CBR services are provided.

Abstract: A system for variable bit-rate video coding in which encoding bandwidth as characterized by a usage parameter control (UPC) parameters is renegotiated between a video encoder and an asynchronous transfer mode network in order to maintain quality-of-service and save bandwidth. The coding system includes adjusting the video source quantization in a manner for controlling the occupancy level of a buffer while new UPC parameters are requested from an ATM network.