Abstract: A semiconductor device in which surge breakdown of interlayer-insulating film does not occur even when effectively suppressing variations in etching and proximity effects. The semiconductor comprises dummy patterns 7b that are made from a gate layer and shaped to be disposed within the surface shape of the insulating material of element-isolation areas 3a and are located on the insulating material of the element-isolation areas 3a; wherein dummy patterns 7b are located on an underlayer that includes area directly under wiring layers 10a that are located on layers above the gate layer.

Abstract: Method for searching services, resources and/or functionalities in a network wherein the network comprises a multitude of nodes to which routable network addresses are assigned, and wherein the services, resources and/or functionalities which are to be searched, are specified by a source node (Q) that is characterized in that a corresponding direction is specified within the network by at least one destination node (Z) and/or nodes near to the destination node (Z), by which a routing path is defined between the source node (Q) and the corresponding destination node (Z), and characterized in that only pre-configurable nodes near to the routing path between source node (Q) and destination node (Z) are included in the search.

Abstract: A lower electrode projects outward from a common end face of an upper electrode and a capacitor film. A protective film, which is made of a different material from the capacitor film, is deposited on top of a part of the lower electrode outside the end face. The protective film also extends to the position at a certain distance inward from the end face, so that it is placed between the capacitor film and the lower electrode. The capacitor film thereby has a stepped surface near the end face due to the presence of the protective film, which suppresses the progress of damage during etching of the upper electrode and the capacitor film. Further, the protective film prevents the occurrence of damage in the lower electrode.

Abstract: A printed circuit board includes a source interconnect and a ground interconnect, and the circuit board has a two-dimensional geometry having a corner. Protruding portions are provided in circumferences of the source interconnect and the ground interconnect in regions except the corner in plan view, and the source interconnect and the ground interconnect are connected to a common first decoupling capacitor in each of the protruding portions.

Abstract: A semiconductor device 1 includes an interconnect 12, a conductive layer 14 (first conductive layer), an insulating layer 20 (first insulating layer), another conductive layer 30 (second conductive layer), another insulating layer 40 (second insulating layer), a via plug 52 (first via plug), and another via plug 54 (second via plug). In the semiconductor device 1, the conductive layer 14, the insulating layer 20 and the conductive layer 30 constitute a MIM capacitor (capacitor element). To be more detailed, the conductive layer 14, the insulating layer 20 and the conductive layer 30 serve as a lower electrode, an insulating capacitor film and an upper electrode, respectively. The insulating layer 40 covers both the conductive layer 30 and the interconnect 12. The insulating layer 40 works as the etching stopper for the via plugs 52, 54.

Abstract: An object of the present invention is to provide a filter circuit which improves NF of a Gm-C filter. The filter circuit comprises a filter comprising at least one first operational transconductance amplifier whose mutual conductance varies depending on a first control signal and a first capacitor, a second operational transconductance amplifier whose mutual conductance is controlled by the first control signal, a third operational transconductance amplifier whose mutual conductance is controlled by a second control signal, and a second capacitor connected to output terminals of the first and second operational transconductance amplifiers and input terminals of the filter.

Abstract: An image sensor includes a reset transistor, reset gate electrodes and a potential shift circuit. The reset transistor includes a reset gate and a reset drain, and resets charges detected by a charge detection device. The reset gate electrodes control a potential of the reset gate. The potential shift circuit initializes output signals in response to a shift pulse, and outputs the output signals to the reset gate electrodes in response to a reset pulse.

Abstract: According to the present invention, high-k film can be etched to provide a desired geometry without damaging the silicon underlying material. A silicon oxide film 52 is formed on a silicon substrate 50 by thermal oxidation, and a high dielectric constant insulating film 54 comprising HfSiOx is formed thereon. Thereafter, polycrystalline silicon layer 56 and high dielectric constant insulating film 54 are selectively removed in stages by a dry etching through a mask of the resist layer 58, and subsequently, the residual portion of the high dielectric constant insulating film 54 and the silicon oxide film 52 are selectively removed by wet etching through a mask of polycrystalline silicon layer 56. A liquid mixture of phosphoric acid and sulfuric acid is employed for the etchant solution. The temperature of the etchant solution is preferably equal to or lower than 200 degree C., and more preferably equal to or less than 180 degree C.

Abstract: The present invention provides a delay analysis system which makes it possible to make delay analysis considering circuit logical information in order to give more accurate delay times. In addition to circuit connection information and delay time information on the rises and falls of the input and output terminals of the circuits which are stored in a delay analysis library, the delay analysis system according to the present invention contains, in the library, logical operation information which represents correspondence between the logical values of each input terminal and their output logical values of the circuits.

Abstract: To reduce EMI and current consumption in internal wiring after display data have been input to a data driver. Display data DN/DP constituted by RSDS signals input to a data driver in a first stage are converted to display data DA constituted by CMOS signals, subjected to primary inversion control according to a data inversion signal INV generated inside, and transferred into internal wiring 31 in a data capturing circuit 30. Then, the display data are subjected to secondary inversion control by a secondary data inversion circuit 33 disposed immediately before data registers 34 according to the data inversion signal INV, and then captured by the data registers 34. Further, chip-to-chip transfer of the display data DA and the data inversion signal INV to the data drivers in second and subsequent stages is performed through the internal wiring 31 and internal wiring 32. Then, as in the data driver in the first stage, the display data DA are captured by the data registers 34.

Abstract: An LSI (Large-Scale Integrated) circuit system capable of preventing antenna damage occurring in MOS (Metal Oxide Semiconductor) transistors due to an erroneous operation of a wiring formed during manufacturing processes of LSIs or like as an antenna. Layout data after installation of wirings is read by layout reading processing and up-sizing candidate table is created by sizing candidate table creating processing using various libraries so that candidate values are arranged for every function cell in ascending order of gate areas. By antenna error net detecting processing, a net having wiring layers causing an antenna error is detected. A gate pin, its instance, type of a cell connected to the net is recognized by gate pin/cell recognizing processing and a cell enabling prevention of an antenna error is up-sized by cell sizing processing by referring to a gate area stored in an up-sizing candidate table.

Abstract: The present invention relates to a semiconductor device including a Fin type field effect transistor (FET) having a protrusive semiconductor layer protruding from a substrate plane, a gate electrode formed so as to straddle the protrusive semiconductor layer, a gate insulating film between the gate electrode and the protrusive semiconductor layer, and source and drain regions provided in the protrusive semiconductor layer, wherein the semiconductor device has on a semiconductor substrate an element forming region having a Fin type FET, a trench provided on the semiconductor substrate for separating the element forming region from another element forming region, and an element isolation insulating film in the trench; the element forming region has a shallow substrate flat surface formed by digging to a depth shallower than the bottom surface of the trench and deeper than the upper surface of the semiconductor substrate, a semiconductor raised portion protruding from the substrate flat surface and formed of a p

Abstract: A delay apparatus includes a DLL circuit including a delay element, the DLL circuit generating a first control signal for controlling the delay element in order that the delay element delays a reference clock inputted into the delay element by one cycle, and a strobe delay element having a configuration identical to a configuration of the delay element, the strobe delay element delaying the strobe signal inputted from an outside by an amount of delay corresponding to a second control signal. The delay apparatus further includes a strobe delay controlling circuit obtaining the second control signal, from the first control signal and an expectation value for the amount of delay to be made by the strobe delay element, and a clock supplying circuit supplying the DLL circuit with the reference clock having a frequency higher than a frequency of the strobe signal.

Abstract: The present invention provides a semiconductor device that shows excellent manufacturing stability and has lower contact resistance, and a method for manufacturing the semiconductor device. The semiconductor device includes an upper interconnect, a lower interconnect, insulating layers interposed between the upper interconnect and the lower interconnect, a connecting portion that is formed in the insulating layers and connects the upper interconnect and the lower interconnect, and an element that is placed in one of the insulating layers and has a conductive layer connected to the connecting portion. The connecting portion is formed over the lower interconnect and the end portions of the conductive layer of the element, and is in contact with the upper face of the lower interconnect and the upper faces and side faces of the end portions of the conductive layer of the element.

Abstract: There is already disclosed a technique for an MB-OFDM communication system whereby an orthogonal demodulation section removes a DC offset generated in a received signal in a region where the received signal is an analog signal, but the removal of the DC offset in the analog region cannot prevent the DC offset from remaining, and therefore the DC offset needs to be effectively removed in a digital region. An offset canceling section 26 calculates an average value of amplitude of a signal which should have an average of amplitude within a predetermined time range of 0, subtracts the average value from the signal and thereby removes an offset included in the signal.

Abstract: A noise reducing apparatus includes a flat area detecting section, a noise component analyzing section and a noise component suppressing section. The flat area detecting section detects a flat area from an image. The noise component analyzing section analyzes a noise component from the flat area. The noise component suppressing section suppresses a noise component of the image based on the noise analysis result. This noise reducing apparatus reduces the noise of the image without damaging subjective image quality.

Abstract: Methods and systems for reusing macro cell resources in femto cell base stations or relay stations in a non-collaborative manner are disclosed. In addition, orthogonal resource allocation between a macro cell base station and femto cell base stations/relay stations may be dynamically adjusted by considering user-population variance. Moreover, an additional level of spatial reuse by femto cell base stations or relay stations can be provided by employing macro cell user location information.

Abstract: In a method of providing scheduling information for use at the mobile radio communications network device for UL resource allocation at the mobile radio communications device between a plurality of Radio Bearers, wherein each Radio Bearer has a Prioritized Bit Rate and at least one Radio Bearer comprises a Guaranteed Bit Rate Radio Bearer.

Abstract: A regulator circuit includes a direct-current voltage conversion circuit which receives a first power supply voltage, and generates a second power supply voltage by stepping down a first power supply voltage, and an error amplifier that operates based on the first power supply voltage, and outputs an output control signal by comparing a feedback voltage that varies depending on an output voltage outputted from an output terminal and a reference voltage. The regulator circuit includes an N-type MOS transistor including a drain supplied with the second power supply voltage, a source connected to the output terminal, and a gate receiving the output control signal.

Abstract: According to exemplary methods and systems of the present principles, the location of defective field repairable units (FRUS) of a circuit that have varying sizes or varying numbers of scan cells may be identified by employing tiles including scan cells from different FRUS. A set of test patterns may be scanned through the scan cells such that cells belonging to FRUs within a tile may be concealed while analyzing the response of scan cells in the tile contributed by a different FRU. Further, defective tiles are discoverable at any tile location and in any quantity within a maximal capacity using a compressed signature. In addition, signature registers that process data at a rate that is faster than the scan shift rate of the circuit may be employed during compression to multiply a circuit response by a plurality of components of a compression matrix during one scan shift cycle.