Abstract: A nonvolatile semiconductor memory includes a memory cell, a first gate control circuit that is coupled to the memory cell, and a second gate control circuit that is coupled to the memory cell. The memory cell includes a first gate electrode that is formed above a channel region in a semiconductor substrate, a second gate electrode that is formed beside the first gate electrode, and that is capacitively coupled with the first gate electrode through a first insulating layer, and a charge trapping layer that is formed between the channel region and the second gate electrode, and that includes a second insulating layer for trapping a charge. Data stored in a memory cell transistor including the second gate electrode changes depending on an amount of the charge trapped in the charge trapping layer. The first gate control circuit applies a potential to the first gate electrode, when reading the data stored in the memory cell transistor.

Abstract: A debugging system according to an exemplary embodiment of the present invention includes: a plurality of arithmetic processing units (51, 52) that perform arithmetic processing; a comparison unit (53) that compares outputs from the plurality of arithmetic processing units (51, 52); and a debug processing unit (54) that outputs a stop instruction for stopping operation of the comparison unit (53), to the comparison unit 53, when debug processing is performed on a predetermined arithmetic processing unit among the plurality of arithmetic processing units (51, 52).

Abstract: A semiconductor device has an element interconnection 2, a top-layer element interconnection 4, a super-connect interconnection 10 and a bump 7. The element interconnection 2 is provided on a semiconductor substrate 1 through a plurality of insulating layers 50. The top-layer element interconnection 4 is formed above the element interconnection 2 by using a substantially equivalent process equipment. The super-connect interconnection 10 is provided on the top-layer element interconnection 4 through a super-connect insulating layer 9 having a thickness five or more times larger than that of the insulating layer 5, and has a thickness three or more times larger than that of each the element interconnection 2 and the top-layer element interconnection 4. The bump 7 is formed on the super-connect interconnection 10. The top-layer element interconnection 4 has a signal pad 4s, a power source pad 4v and a ground pad 4g.

Abstract: Methods and systems for reusing macro cell resources in femto cell base stations or relay stations in a non-collaborative manner are disclosed. In addition, orthogonal resource allocation between a macro cell base station and femto cell base stations/relay stations may be dynamically adjusted by considering user-population variance. Moreover, an additional level of spatial reuse by femto cell base stations or relay stations can be provided by employing macro cell user location information.

Abstract: To provide a technique for structuralizing ontology in a prescribed form to a structure to which features of data are reflected. An ontology processing device has a structuralizing device for structuralizing properties of the ontology in the prescribed form generated from a set of instance data containing a combination of a subject, a property, and an object expressed with a character string according to the features of the object, and has a ontology storage device which stores the ontology structuralized by the structuralizing device. With this structure, the properties of the ontology in the prescribed form are corrected or expressed as an ontology structure by reflecting the characteristics of a set of the objects obtained from the data.

Abstract: A semiconductor device including: a substrate formed with a concave portion at one surface thereof; and a first semiconductor chip provided in the concave portion of the substrate and is adhered to the substrate by an underfill in the concave portion, wherein the concave portion includes a chip arrangement region in which the first semiconductor chip is arranged, and an adjustment region which protrudes from at least a portion of the periphery of the chip arrangement region when seen in a plan view at a height of at least a portion of a region where the first semiconductor chip is placed in a stacked direction of the substrate, and has different shapes from the chip arrangement region is provided.

Abstract: A plurality of delay paths are connected in parallel between two synchronous operation circuits operating in synchronism with a clock signal CLK, and enable transmission of a signal. A delay detection unit detects the respective delay times of the plurality of delay paths, and a control unit selects one delay path from among the plurality of delay paths based on the detection results from the delay detection unit, and controls the blocking of signal transmission in the delay paths other than the selected one delay path.

Abstract: Systems and methods are disclosed to probe a network includes generating a set of probing pairs from a network topology for unicast network delay tomography; probing the network using monitoring hosts in the network; and determining network performance from the probing results.

Abstract: The present invention provides a method and apparatus for generating index as well as a search method and a search apparatus. Index entry comprises at least a search item identifier corresponding to a search item, one or a plurality of index items generated from one or plural pieces of search information, and an accumulator for the search information. The accumulator is generated by accumulating the search information, or accumulating ciphertext of information containing the search information, or accumulating data mapped from information containing the search information. At the time of searching, the index items and the accumulator are provided to a searcher. The searcher extracts search information from the index items and checks whether the extracted search information is complete by using the accumulator. In one embodiment, the accumulator is incorporated in an encrypted inverted index.

Abstract: Polarization multiplexing, optical communications systems can suffer from chromatic dispersion and polarization mode dispersion, resulting in channel delay spread. These errors can be compensated quickly and simply in the frequency domain. By obviating the need for a cyclic prefix, the complexity of the equalization can be reduced by more than a factor of twenty.

Abstract: An RF tag system includes a first reader/writer unit and a second reader/writer unit. A first reader/writer control unit is configured to control the first reader/writer unit to read a first data from a first RF tag, and to detect a trouble state of the first reader/writer unit. A second reader/writer control unit is configured to control the second reader/writer unit to read a second data from a second RF tag, and to detect a trouble state of the second reader/writer unit. A monitoring section is configured to issue a selection instruction and to monitor the first reader/writer unit through the first reader/writer control unit, and the second reader/writer unit through the second reader/writer control unit. A switching section is configured to select one of the first reader/writer control unit and the second reader/writer control unit in response to the selection instruction from the monitoring section.

Abstract: A layout density verification system has: a model generation unit configured to generate a macro model for use in metal density check, with respect to a macro included in a layout data; and a metal density check unit configured to perform the metal density check of the layout data by using the macro model. The macro model includes: an inner region; and an outer region surrounding the inner region and located between the inner region and an outer boundary of the macro. The inner region is masked by metal while a metal layout within the outer region is maintained. A width of the outer region inward from the outer boundary of the macro is equal to or larger than a width of one side of a window as a check unit at a time of the metal density check.

Abstract: A technology is disclosed for providing an additional function control system which permits a carrier to select whether or not an additional function possessed by a communications terminal can be made available. A communications network is connected to a communications terminal when using a communications function of the communications terminal which is subscribed to a communication service. An additional function controller manages the additional function of the communications terminal, and provides the communications terminal with additional function control information for controlling the operation of the additional function. The communications terminal comprises an additional function unit for providing the additional function, and limits the operation of the additional function unit based on the additional function control information from the additional function controller.

Abstract: An input signal detecting circuit includes a plurality of comparators configured to output a plurality of differential output signals in response to a differential input signal, respectively; and a differential exclusive OR circuit configured to output an exclusive OR resultant signal from the plurality of differential output signals outputted from the plurality of comparators. In at least one of the plurality of comparators, a DC operation voltage is changed in response to a control signal supplied to the comparator.

Abstract: An inductance device comprises a magnetic core, a coil a conductor and a dielectric member. The coil is made of turns of insulated conductive wire. The conductor is distinct from the coil and is insulated from the magnetic core. The dielectric member is disposed between the conductor and the coil. The dielectric member, the conductor and the coil constitute a capacitor. The inductance device is used in, for example, a filter device or a noise filter.

Abstract: There are provided a three-dimensional data input means (10) for input the three-dimensional data of an object, a reference image storing unit (30) for storing a reference image of at least one object, a pose candidate deciding means (20) for generating a pose candidate that is a candidate for the pose of the object, a comparison image generating means (40) for generating a comparison image close to the reference image while projecting the three-dimensional data onto a two-dimensional image in accordance with the pose candidate, and an image comparing means (55) for performing comparison based on either a distance value or similarity degree between the reference image and the comparison image. This allows comparison or search to be performed with high accuracy even when the reference image of the object is captured under different conditions such as pose and illumination, even when no three-dimensional object model of the object can be obtained in advance, or even when only one or few reference images exist.

Abstract: In a mobile phone of the present invention, de-spread circuits execute de-spread processing for receiving signals, and rake combines compose a plurality of information in the outputs of the de-spread circuits in correspondence to base stations, and calculate receiving levels of power control signals in individual channels in correspondence to the base stations to output the power control signals each having receiving level information to a comparator. The comparator outputs only the power control signal having the receiving level lying within a predetermined range from a maximum receiving level of the receiving levels of the power control signals from among the plurality of base stations to a decision circuit. The decision circuit decides based on the power control signal from the comparator whether a transmission power from the mobile phone should be increased or decreased to control the transmission power of a transmitter circuit, thereby preventing misrecognition of the power control signal.

Abstract: A clock and data recovery circuit that tracks the frequency and phase fluctuation of serial data includes a feedback controller for monitoring tracking speed of an extraction clock with respect to the frequency and phase fluctuation of the serial data and applying feedback control to an integrator adaptively and moment to moment, thereby raising the tracking speed of the recovered clock and improving the jitter tolerance characteristic.

Abstract: A method for manufacturing a semiconductor device includes preparing two substrates having a first and a second surface and having first and second pads and a second testing-dedicated pad, the first pads in the first surface, the second pads in the second surface and arranged with an inter-pad distance that is larger than that for the first pad, and the second testing-dedicated pad being in the second surface; coupling a wafer with a apparatus, and inspecting the wafer with a probe card, the wafer having a LSI, which is an object of an inspection, the apparatus applicable signal to the LSI formed in the wafer, and measurable electrical characteristics of the LSI formed in the wafer, and the probe card having one of the two substrates; dicing the wafer into semiconductor elements containing the LSI; and packaging the semiconductor element over the other of the two substrates.

Abstract: A communication system, which performs communication using a transmission packet encrypted by an IP-SEC encrypting method, includes a first encrypting circuit that encrypts a transmission packet by an IP-SEC encrypting method, a second encrypting circuit that encrypt header data to be used to decode the transmission packet encrypted by the first encrypting circuit, and a transmitting circuit that transmit the transmission packet whose header is encrypted by the second encrypting circuit. The communication system further includes a first decoding circuit that decode the authentication data of the reception packet using information to be used to decode the authentication data recorded in the IP-SEC header of the transmission packet and a second decoding circuit that decodes the reception packet using the authentication data decoded by the first decoding circuit.