Patents Assigned to NEC
  • Patent number: 7696061
    Abstract: A semiconductor device comprises a drift region of a first conduction type, a base region of a second conduction type, a source region of the first conduction type, a contact hole, a column region of the second conduction type, a plug and wiring. The drift region formed on a semiconductor substrate of the first conduction type. The base region of a second is formed in a prescribed region of the surface of the drift region. The source region is formed in a prescribed region of the surface of the base region. The contact hole extends from the source region surface side to the base region. The column region is formed in the drift region below the contact hole. The plug comprises a first conductive material and fills the contact hole. The wiring comprises a second conductive material and is electrically connected to the plug.
    Type: Grant
    Filed: September 26, 2007
    Date of Patent: April 13, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Hitoshi Ninomiya
  • Patent number: 7698308
    Abstract: As in a normal storage system, an application run on a host issues a data write command or a data read command. A monitor unit monitors the host and a command issued by the host to detect a re-startable point to issue the re-startable point notification to a source storage system. Using the re-startable point as a momentum, the source storage system converts a command stored in a buffering unit into a command for transfer in which redundant data transfer has been curtailed to transfer the command for transfer to a destination storage system. The destination storage system applies the received command to a storage unit. At this time, the command for transfer is restored to an ordinary command which is applied.
    Type: Grant
    Filed: November 17, 2005
    Date of Patent: April 13, 2010
    Assignee: NEC Corporation
    Inventors: Masaki Kan, Jun-ichi Yamato
  • Patent number: 7698620
    Abstract: A calculation is facilitated for y[i]=q[i]×mod(p?1) which is required as an intermediate value when calculating intra-row permutation pattern U[i][j], which is a parameter for use by an interleaver for on a turbo code defined in a standard 3GPP TS25.212 of IMT 2000, from prime number p, base sequence s[j], inter-row permutation pattern T[i], and prime number sequence q[i]. First, index i and variable div are initialized to zero. When q[i]?div+p?1, p?1 is added to the value of div. When q[i]<div+p?1, y[i] is calculated in accordance with y[i]=q[i]?div. Index i is incremented and the foregoing processing is repeated until i reaches R.
    Type: Grant
    Filed: February 24, 2005
    Date of Patent: April 13, 2010
    Assignee: NEC Corporation
    Inventor: Kazuhiro Ishida
  • Patent number: 7694880
    Abstract: A voting server transmits a list of plaintext and encrypted voting data obtained by encrypting the plaintext to a voter terminal, and the voter terminal a selected encrypted candidate name corresponding to the plaintext elected by the voter to an encryption server. The encryption server returns encrypted voting data obtained by re-encrypting the encrypted candidate name to the voter terminal, and the voter terminal transmits the encrypted voting data received from the encryption server for voting. Decryption of the encrypted voting data is performed by an anonymous decryption system. The voter terminal certifies the voter to an authentication server, and affixes a digital signature to the encrypted voting data based on a common-key authentication base, transmitting the same to the voting server.
    Type: Grant
    Filed: January 18, 2005
    Date of Patent: April 13, 2010
    Assignee: NEC Corporation
    Inventors: Kengo Mori, Kazue Sako
  • Patent number: 7696789
    Abstract: Disclosed is a high-frequency signal detector circuit including a diode detector circuit for detecting an input signal by diode detection; a differential-input/differential output amplifier with a common mode feedback circuit, the amplifier including a differential amplifying circuit for differentially receiving outputs of the diode detector circuit and outputting a differential output signal, and a common mode feedback circuit for controlling the differential amplifying circuit in such a manner that a voltage corresponding to a mid-point of the differential output signal from the differential amplifying circuit will take on a voltage identical with a prescribed voltage; and a differential-input/single-ended output amplifier for receiving the differential output signal of the differential amplifying circuit and outputting a single-ended output signal.
    Type: Grant
    Filed: May 23, 2008
    Date of Patent: April 13, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Naohiro Matsui
  • Patent number: 7696793
    Abstract: A differential signal driver circuit is provided with a driver circuit and a common feedback circuit. The driver circuit is responsive to differential input signals for generating differential output signals from operation currents generated by two current sources. The common feedback circuit controls the current sources to regulate the current levels of the operation currents in response to the differential output signals.
    Type: Grant
    Filed: May 31, 2007
    Date of Patent: April 13, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Souji Sunairi
  • Patent number: 7696911
    Abstract: Disclosed is a digital-to-analog conversion circuit in which first and second serial DACs and an amplifier circuit for driving a data line are provided. In a first data period, the first serial DAC converts a first digital signal received in the first data period to a first signal, the second serial DAC holds a signal obtained by converting a digital signal received in a data period one period before the first data period, and the amplifier circuit amplifies and outputs the signal held in the second serial DAC, to the data line. In a second data period following after the first data period, the second serial DAC converts the second digital signal received in a second data period, the first serial DAC holds the first signal converted in the first data period, and an amplifier circuit amplifies and outputs the first signal held in the first serial DAC, to the data line.
    Type: Grant
    Filed: June 6, 2008
    Date of Patent: April 13, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Hiroshi Tsuchi
  • Patent number: 7697753
    Abstract: An apparatus is disclosed for generating image feature data from an image having an arbitrary shape for use in image search. The apparatus includes rectangular area generating unit (2); rectangular image generating unit (3); padded-pixel value selecting unit (5); and image feature data generating unit (4). First, rectangular image generating unit (2) draws a rectangular area around input image (1) such that input image (1) is included therein. Rectangular image generating unit (3) pads a pixel value in an area of the rectangular area generated by rectangular area generating unit (2) which does not include pixels associated with input image (1) to generate a rectangular image. Image feature data generating unit (4) generates feature data from the image generated by rectangular image generating unit (3).
    Type: Grant
    Filed: February 19, 2002
    Date of Patent: April 13, 2010
    Assignee: NEC Corporation
    Inventor: Eiji Kasutani
  • Patent number: 7697044
    Abstract: The image processing apparatus includes an RGB-YUV converter for converting a color image into a luminance signal and a color difference signal and a YUV false color remover for removing false color based on the luminance signal Y and the color difference signals U, V. The false color remover includes an edge intensity calculator for calculating edge intensity based on the luminance signal Y, a modulation coefficient calculator for calculating a modulation coefficient so that a degree of modulation is greater as the edge intensity is higher, and a UV modulator for modulating a color difference signal having a value smaller than a prescribed threshold based on the degree of modulation.
    Type: Grant
    Filed: August 30, 2006
    Date of Patent: April 13, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Kazuki Mishina
  • Patent number: 7698494
    Abstract: An access control device controls access to a first device and a second device. The first device is connected with a first bus conforming to a first standard and conforms to the first standard. The second device is connected with the first bus and conforms to a second standard. The access control device includes a first signal generator and a second signal generator. The first signal generator generates a first transaction start signal indicating start of a transaction for the first device. The second signal generator generates a second transaction start signal for the second device based on the first transaction start signal.
    Type: Grant
    Filed: October 22, 2007
    Date of Patent: April 13, 2010
    Assignee: NEC Access Technica, Ltd.
    Inventor: Tetsuya Kato
  • Patent number: 7696838
    Abstract: In an equalizing filter circuit having an input terminal 101, an output terminal 102, delay devices 104 connected in multi-stage to the input terminal 101, and a plurality of weighting circuits 105 which are branched from and connected to the plurality of delay devices to thereby combine respective output signals of the weighting circuits, gain adjustment of the weighting circuits is performed to determine a coefficient of the equalizing filter circuit without depending on a load connected to the output terminal. Thus, an amount of compensation for a distorted waveform may be enhanced. To this end, an impedance converting circuit 108 is connected between at least one weighting circuit and the output terminal.
    Type: Grant
    Filed: September 9, 2005
    Date of Patent: April 13, 2010
    Assignee: NEC Corporation
    Inventors: Shigeki Wada, Yasuyuki Suzuki
  • Patent number: 7697356
    Abstract: A method of testing a semiconductor apparatus performs a function test of reading data from memory cells in SRAM by applying a potential lower than a GND potential to a backgate of an n-type MOS transistor with a drain connected with a storage node and a source connected with the GND potential. Then, the method performs a function test of reading data from memory cells by applying a potential higher than the GND potential to the backgate.
    Type: Grant
    Filed: November 27, 2007
    Date of Patent: April 13, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Naoto Akiyama
  • Patent number: 7696045
    Abstract: A method of manufacturing a semiconductor device according to an embodiment of the present invention includes: forming a first insulating film on a semiconductor substrate; forming a mask with an opening of a predetermined pattern in the first insulating film; performing anisotropic etching on the semiconductor substrate with the mask used as an etching mask to form a trench; forming a second insulating film on a surface of an inner wall of the trench with the mask used as a selective oxidation mask; removing the mask; forming a conductive film on the semiconductor substrate to fill the trench with the conductive film; and etching back the conductive film until at least a surface of the semiconductor substrate is exposed.
    Type: Grant
    Filed: August 18, 2007
    Date of Patent: April 13, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Minoru Kawahara
  • Patent number: 7698013
    Abstract: A parts production management system includes: a first table in which a line cycle number representing a line cycle that is a process unit for processing a group of parts and a parent lot number of a part input for being processed in a line cycle represented by the line cycle number are stored while being linked together; a second table in which the line cycle number and a child lot number of a part processed in the line cycle represented by the line cycle number are stored while being linked together; and a lot linking unit that stores a line cycle number of a line cycle for processing a parent lot and a parent lot number in the first table while being linked together when the parent lot is input to a production line and stores a line cycle number of a line cycle that has processed a child lot and the child lot number while being linked together when a process in the production line is completed and the child lot is output from the production line.
    Type: Grant
    Filed: July 25, 2007
    Date of Patent: April 13, 2010
    Assignees: Honda Motor Co., Ltd., NEC Corporation
    Inventors: Hajime Honda, Yoshiro Yamagami, Seitaro Ikeda
  • Patent number: 7696007
    Abstract: A semiconductor package board for mounting thereon a semiconductor chip includes a metal base having an opening for receiving therein the semiconductor chip and a multilayer wiring film layered onto the metal base. The semiconductor chip is flip-chip bonded onto the metal pads disposed on the multilayer wiring film within the opening. The surface of the metal base is flush with the top surface of the semiconductor chip received in the opening. The resultant semiconductor device has a larger number of external pins and a smaller deformation without using a stiffener.
    Type: Grant
    Filed: February 23, 2009
    Date of Patent: April 13, 2010
    Assignee: NEC Corporation
    Inventors: Katsumi Kikuchi, Tadanori Shimoto, Koji Matsui, Kazuhiro Baba
  • Patent number: 7698670
    Abstract: In a method for designing a semiconductor integrated device, there are prepared a first power supply cell having a first decoupling capacitance and a second power supply cell having a second decoupling capacitance larger than the first decoupling capacitance. One of the first and second power supply cells is arranged in each of power supply cell areas of an input/output circuit area of the semiconductor integrated device in accordance with frequency-to-impedance characteristics at a predetermined point of input/output buffers of the input/output circuit area between first and second power supply lines thereof and frequency-to-noise current characteristics of the input/output buffers of the input/output circuit area between the first and second power supply lines.
    Type: Grant
    Filed: September 6, 2007
    Date of Patent: April 13, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Yoshihiro Masumura
  • Patent number: 7697578
    Abstract: The present invention provides a directly modulatable wavelength variable laser that enables long distance and large volume communication with a simple and compact configuration. The wavelength variable laser includes a semiconductor optical amplifier, an optical filter, and a frequency-amplitude converter. The semiconductor optical amplifier produces optical gain of the light signal. The optical filter configured by multi-stage connected waveguide ring resonators performs frequency modulation on the light signal. The frequency-amplitude converter performs amplitude modulation on the light signal frequency modulated in the optical filter.
    Type: Grant
    Filed: August 29, 2007
    Date of Patent: April 13, 2010
    Assignee: NEC Corporation
    Inventor: Hiroyuki Yamazaki
  • Patent number: 7697064
    Abstract: To provide a video signal processing apparatus capable of generating video signals that enable displaying and recording of a high-quality picture. A video signal processing apparatus according to an embodiment of the present invention includes a decoder decoding an input TS to generate a video signal having a field frequency fv of 60 Hz or a video signal having a field frequency fv of 59.94 Hz, and a converter converting the respective video signals into NTSC video signals having a color subcarrier the phase of which is inverted for each frame.
    Type: Grant
    Filed: December 12, 2005
    Date of Patent: April 13, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Yoshikazu Komatsu
  • Patent number: 7696970
    Abstract: A driving circuit according to an embodiment of the invention includes: a switching unit for sequentially switching between a first operation of applying a positive gray-scale voltage to odd-numbered data lines and applying a negative gray-scale voltage to even-numbered data lines and a second operation of applying a negative gray-scale voltage to odd-numbered data lines and applying a positive gray-scale voltage to the even-numbered data lines; a plurality of short-circuit switches for short-circuiting a pair of adjacent odd-numbered data lines and a pair of adjacent even-numbered data lines to produce a plurality of pairs of short-circuited data lines in a switching period between the first operation and the second operation; and a plurality of common node-connected switches corresponding to the plurality of data line pairs and short-circuiting a corresponding one of the data line pairs to a common node.
    Type: Grant
    Filed: June 29, 2006
    Date of Patent: April 13, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Junya Yokota
  • Patent number: 7697567
    Abstract: In a packet repeater of a wireless base station, a packet analyzer receives uplink packets from mobile terminals and stores data indicating quality of each wireless link between the base station and each mobile terminal in a memory. A packet sorter receives downlink packets from a network and stores the received packets into buffers according to the destinations of downlink packets and their service classes. According to the data stored in the memory, packets in the buffers are into a first group of queues in which quality of service is not satisfied and a second group of queues in which quality of service is satisfied. A packet scheduler sequentially transmits all packets from the first-group queues to mobile terminals, and reorders the second-group queues in a descending order of their qualities of wireless links and sequentially transmits all packets from the reordered queues to the mobile terminals.
    Type: Grant
    Filed: January 16, 2003
    Date of Patent: April 13, 2010
    Assignee: NEC Corporation
    Inventors: Masahiro Ono, Yasuhiko Matsunaga