Abstract: A plurality of sets of position code books indicating the pulse position are provided in a multi-set position code book storing circuit (450). In accordance with a pitch prediction signal obtained in an adaptive code book circuit (500), one type of position code book is selected from the plurality of position code books in a position code book selecting circuit (510). From the selected position code book, a position is selected by a sound source quantization circuit (350) so as to minimize distortion of a sound signal. An output of the adaptive code book circuit (500) and an output of the sound source quantization circuit (350) are transferred. Thus, a sound signal can be encoded while suppressing deterioration of the sound quality with a small amount of calculations even when the encoding bit rate is low.

Abstract: In a formation method for forming a fine structure in a workpiece (30) containing an etching control component, using an isotropic etching process, a mask (32, 34) having an opening (36) is applied to the workpiece, and the workpiece is etched with an etching solution (38) to thereby form a recess (40), corresponding to a shape of the opening, in a surface of the workpiece. The etching of the workpiece is stopped due to the etching control component eluted out of the workpiece in the etching solution within the recess during the isotropic etching process.

Abstract: A user data management apparatus for connection to a terminal data processor used by a user through a network, registers data that is dependent on a user ID peculiar to the user. The user data management apparatus has a first unit for generating a first data registration screen, when data of the user is to be initially registered, which differs from user ID to user ID, and a second unit for displaying, on the terminal data processor, a second data registration screen based on the first data registration screen generated by the first unit, when the data of the user is to be registered.

Abstract: A relay circuit that includes: a light emitting element that outputs an optical signal in accordance with an input electric signal; a photoelectric conversion element that converts the optical signal into an electric signal and generates a potential difference between its opposite ends; a switching element that has a prescribed threshold value and that determines an output state in accordance with the potential difference that is generated by the photoelectric conversion element and that exceeds the prescribed value; first and second paths that are respectively connected to the opposite ends of the photoelectric conversion element and that transmit the potential difference generated by the photoelectric conversion element to the switching element; a discharge circuit that electrically connects the first path and the second path to each other when the potential difference generated by the photoelectric conversion element drops to a prescribed value; and a first resistor element that is arranged between the dis

Abstract: The present invention is aimed at realizing an amplifying circuit whose chip size is prevented from being significantly increased even if the number of compatible frequencies increases, and which has a wide dynamic range when it operates under a low voltage.

Abstract: [PROBLEMS] To provide a data processing device such as a text mining device capable of extracting characteristic structures properly even in case a plurality of words indicating identical contents or a plurality of words semantically associated are contained in input data. [MEANS FOR SOLVING PROBLEMS] Association node extraction unit (22) of a text mining device (10) extracts association nodes containing semantically associated words from a graph obtained as a result of syntax analysis. Association node joint unit (23) transforms the graph by joint of a part of or a whole of the association nodes. Characteristic structure extraction unit (24) extracts a characteristic structure from the graph transformed by the association node joint unit.

Abstract: Semiconductor lasers emit lights having wavelengths of about 400 nm, 650 nm, and 780 nm, respectively. A transmittance adjustment element is provided in an optical path of the light reflected from a disk. The transmittance adjustment element includes a first optical thin film that changes transmittance of a 650-nm-wavelength light relatively to transmittance of 400-nm- and 780-nm-wavelength lights, and a second optical thin film that changes transmittance of a 780-nm-wavelength light relatively to transmittance of 400-nm- and 650-nm-wavelength lights. The transmittance adjustment element has the function of maintaining constant the intensity of light incident onto a photodetector irrespective of the type of medium.

Abstract: In a layout design method of a semiconductor integrated circuit, an IR drop data is calculated to indicate a voltage drop for every local area, and a virtual arrangement library is generated which stores data of a circuit cell to be arranged based on the IR drop data for every circuit module. A virtual arrangement net list is generated by converting the circuit cell contained in a net list into a virtual arrangement cell which is registered on the virtual arrangement library. The circuit module is automatically arranged based on the virtual arrangement net list; and the virtual arrangement cell contained in the automatically arranged circuit module is replaced with the circuit cell contained in the net list.

Abstract: A test circuit with which the cost for checking the duty ratio of a clock signal is restrained. A sampling timing generating circuit, to which the measurement-target clock signal MCK is input, outputs first and second sampling trigger signals to A sample-and-hold circuit 102 respective prescribed timings before and after a timing that is one-half period of the measurement-target clock signal after a first edge of the measurement-target clock signal. The sample-and-hold circuit samples and holds the measurement-target clock signal in correspondence with respective ones of the first and second sampling trigger signals. The sample-and-hold circuit forms all or part of a scan path and outputs a signal, which is being held for checking the duty ratio, from a scan output terminal in response to a scan clock signal.

Abstract: A semiconductor device design support apparatus for generating a substrate netlist so as to be able to perform substrate noise analysis with high accuracy in a short time. The semiconductor device design support apparatus comprises a unit that divides a semiconductor device layout into a plurality of segments and generates a macro-model of the segments by using a current waveform of an instance included in the divided segments; a unit that replaces a pattern (termed as “substrate interface”) that is designed to be an interface with a substrate with respect to the segments, by a prescribed substrate interface diagram; and a unit that generates a substrate netlist, based on the substrate interface diagram of the plurality of segments.

Abstract: A semiconductor device is proposed in which signal delay due to compensation capacitance elements in peripheral circuit element regions is eliminated. The semiconductor device includes: a first region including memory cells; a second region 10 including a functional circuit; cell capacitors formed in the first region; and compensation capacitance elements 36 to 38 formed in the second region 10, wherein the compensation capacitance elements 36 to 38 each include a lower electrode 36, a capacitance insulating film 37, and an upper electrode 38, the lower electrode 36, capacitance insulating film 37, and upper electrode 38 being the same as those of the cell capacitors, and wherein the compensation capacitance elements are formed over an upper layer of the second region 10 excluding upper layer portions of drain diffusion layers 44, 46 or gate electrodes 32 of transistors in the functional circuit.

Abstract: An exemplary aspect of the present invention is a data processing system, including a function block that operates based on a clock, a clock supply control circuit that controls supply of the clock based on an enable signal, a storing part that stores a command table in which a debug command and a number of clocks needed to process the debug command by the function block are made correspondent to each other, and a debug system part that executes debug processing based on an input debug command, in which the debug system part refers to the command table and outputs the enable signal in accordance with the number of clocks corresponding to the input debug command.

Abstract: [Problems] To eliminate flicker when a normal image is presented to user employing an optical shutter from two types or more of image under intermittent illumination of such as fluorescent lamp. [Means for Solving Problems] In a display system (10) including a display panel (11A) which can display two types or more of image sequentially and repeatedly, and an optical shutter (13) which opens with the display cycle of a specific image among the images displayed on the screen of the display panel (11A), display cycle of the specific image on the display panel (11A) is set equal to an integer multiple of the flashing cycle of intermittent illumination (15) under intermittent illumination (15) flashing periodically.

Abstract: A language model learning system for learning a language model on an identifiable basis relating to a word error rate used in speech recognition. The language model learning system (10) includes a recognizing device (101) for recognizing an input speech by using a sound model and a language model and outputting the recognized word sequence as the recognition result, a reliability degree computing device (103) for computing the degree of reliability of the word sequence, and a language model parameter updating device (104) for updating the parameters of the language model by using the degree of reliability. The language model parameter updating device updates the parameters of the language model to heighten the degree of reliability of the word sequence the computed degree of reliability of which is low when the recognizing device recognizes by using the updated language model and the reliability degree computing device computes the degree of reliability.

Abstract: Ground via provided in an end portion of a multi-layer printed circuit board so as to suppress a leakage of magnetic field from the end portion of the board causes a problem that a digital circuit of high density cannot be mounted on the board due to necessity of area for locating the ground via. Further, a case of using solder plating for the end portion of the board causes a problem that manufacturing process is added and that numbers of days and costs for manufacturing the multi-layer printed circuit board are increased. In a multi-layer printed circuit board has a plurality of ground layers and at least one signal layer, the signal layer in which a signal pattern is wired at an end portion of the multi-layer printed circuit board is sandwiched between upper adjacent and lower adjacent ground layers, and the upper adjacent and lower adjacent ground layers are connected to each other by recessed conductors at the end portion thereof.

Abstract: Exemplary systems and methods in accordance with embodiments of the present invention may provide a plurality of data services by employing splittable, mergable and transferable redundant chains of data containers. The chains and containers may be automatically split and/or merged in response to changes in storage node network configurations and may be stored in erasure coded fragments distributed across different storage nodes. Data services provided in a distributed secondary storage system utilizing redundant chains of containers may include global deduplication, dynamic scalability, support for multiple redundancy classes, data location, fast reading and writing of data and rebuilding of data due to node or disk failures.

Abstract: A layout apparatus stores a plurality of capacitor cells which are classifiable into a first classification for identifying capacitor cells having different sizes by frequency characteristic correlating with gate width of a capacitor and a second classification for identifying capacitor cells having different frequency characteristics by cell size.

Abstract: Provided is voltage/current conversion circuit including: first and second capacitors; first and second resistors each connected to input terminal; first and second current sources; third and fourth resistors connected to current sources; differential amplifier for controlling the current sources; control unit for performing control, in first state, the input terminal is connected to the first and second capacitors; one input of the differential amplifier is connected to the first resistor and output of the first current source; the other input of the differential amplifier is connected to the second resistor and output of the second current source, and in second state, the second capacitor is connected between the output of the first current source and the one input of the differential amplifier, the first capacitor is connected between the output of the second current source and the other input of the differential amplifier.

Abstract: A sliceable router includes a forwarding engine; a routing engine coupled to the forwarding engine; multiple virtual packet interfaces coupled to the forwarding engine, wherein the interfaces shares an optical orthogonal frequency-division multiple accesses (OFDMA)-based programmable transceiver for interface virtualization; and one or more physical packet interfaces coupled to the forwarding engine.

Abstract: A semiconductor integrated circuit device includes a column of first logic circuit cells arranged along a first side of a chip and a column of second logic circuit cells arranged along a second side orthogonal to the first side. At a corner part where the first side crosses the second side, a first test logic circuit cell is arranged to have its long side faced with a side of a cell at an end portion of the column of the first logic circuit cells and a second logic circuit cell is arranged to have its long side faced with a side of a cell at an end portion of the column of the second logic circuit cells. The first and the second test logic circuit cells are arranged so a that planar shapes thereof are symmetrical (mirror symmetrical) to each other with respect to a virtual line intermediate between the oblique sides arranged opposite to each other.