Patents Assigned to NEC
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Patent number: 7685473Abstract: A computer system includes a processor that executes a device driver, and a bus controller that controls an input/output bus that connects a plurality of input/output devices. The bus controller includes a stall detector that detects a stall state of the input/output bus and an error reply generator that transmits an error reply to the processor regarding a transaction transmitted to the input/output bus where the stall state is detected.Type: GrantFiled: December 8, 2005Date of Patent: March 23, 2010Assignee: NEC CorporationInventor: Hiroaki Oshida
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Patent number: 7684672Abstract: A broadcast storage system is disclosed which is easily controllable by the user for setting programs for timer recording and playing back recorded programs. The broadcast storage system has one or more slave apparatus and a master apparatus. The master apparatus grasps programs set for timer recording by each of the slave apparatus. When a program to be recorded is determined by the user or an automatic timer recording process, the master apparatus selects an apparatus to record the program such that a plurality of timer recording settings are not made at one time in one apparatus, and instructs the selected apparatus to set the program for timer recording. When instructed to set the program for timer recording, a slave apparatus sets the program for timer recording, and records the program at the time when the program is broadcast.Type: GrantFiled: January 15, 2002Date of Patent: March 23, 2010Assignee: NEC CorporationInventors: Hiroshi Matoba, Takuya Nishibayashi, Satoshi Onodera, Akihisa Kenmochi, Hidetaka Hane, Jun-Ichi Yamato
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Patent number: 7683687Abstract: In a hysteresis characteristic input circuit, first and second resistors are connected in parallel between a first power supply terminal and a connection point, and first and second MOS transistors are connected in parallel between the connection point and a second power supply terminal and are controlled by an input voltage. An inverter has an input connected to the connection point and an output adapted to generate an output voltage. A first switching element is connected in series to the second resistor, and a second switching element is connected in series to the second MOS transistor. The first and second switching elements are complementarily controlled by the output voltage.Type: GrantFiled: November 7, 2007Date of Patent: March 23, 2010Assignee: NEC Electronics CorporationInventors: Shinji Kawashima, Kazunori Doi
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Patent number: 7683762Abstract: A control apparatus 10 has a housing containing an IC memory 25 of an RFID tag 20 as a memory element. The RFID tag 20 has an antenna 21 so as to close the housing. The antenna 21 may be attached to an outside of the housing so as to transmit and receive a radio wave to and from the outside of the housing and is connected to the inside of the housing in a closed state via a lead wire insulated from the housing. The housing may be made of a metal with a removable metallic cover formed at a part thereof to allow transmission and reception of the radio wave. The control apparatus 10 may have an RFID tag counterpart section 14 with an antenna 16 so that the RFID tag 20 is electrically insulated from a control circuit of the control apparatus 10.Type: GrantFiled: January 26, 2005Date of Patent: March 23, 2010Assignee: NEC Infrontia CorporationInventor: Yutaka Kinoshita
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Patent number: 7683819Abstract: Disclosed is a pipeline ADC in which an operational amplifier is shared between circuit blocks that construct local A/D converters of nth and (n+1)th stages, a sampling capacitor of the nth stage is divided into a plurality of sampling capacitors, and some of the plurality of sampling capacitors thus divided in the nth stage are adopted as sampling capacitors of the (n+1)th stage.Type: GrantFiled: February 15, 2008Date of Patent: March 23, 2010Assignee: NEC Electronics CorporationInventor: Akira Kurauchi
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Patent number: 7683590Abstract: A step-down switching DC-DC converter may include an input coil on the input side, an output coil on the output side, a switch, an output capacitor, a first series circuit connected between a connection point on which the input coil and the switch are connected each other and a negative pole of a power source, and a second series circuit connected between a connection point on which the output coil and the switch are connected to each other and the negative pole of the power source. A connection point between a first intermediate capacitor and the first intermediate coil is connected to a connection point between a second intermediate capacitor and the switch via a switching device cooperating with the switch. The input coil and the first intermediate coil are electromagnetically coupled with each other. The output coil and the second intermediate coil are electromagnetically coupled with each other.Type: GrantFiled: March 13, 2009Date of Patent: March 23, 2010Assignee: NEC CorporationInventor: Teiji Yoshida
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Patent number: 7685284Abstract: When a communication malfunction occurs in the transmission line between routers, and operation is carried out by a backup system control device, IP telephone terminals can connect to the backup system control device through the use of an IP address that is previously acquired from the address management device and saved. When the transmission line has been restored, the IP telephone terminals reconnect to the address management device so that operation can be carried out using an IP address under the control of the address management device. In a system that is operated by DHCP, it is thereby possible to construct a network that can be operated without installing a DHCP server at each remote station.Type: GrantFiled: February 2, 2006Date of Patent: March 23, 2010Assignee: NEC CorporationInventor: Tetsuya Yamashita
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Patent number: 7684270Abstract: In a conventional equalizer circuit, in an equalizing operation for setting voltages of a wiring pair having a predetermined voltage difference therebetween to be the same, it takes a long time to make the voltages of the wirings in a pair converge to a voltage having an offset with respect to a midpoint voltage of the voltages of the wiring pair after the equalizing operation. According to an equalizer circuit of the present invention, provided is an equalizer circuit (50) which sets the voltages of a first wiring (SAP) and a second wiring (SAN) to be substantially the same and which has a first transistor (N1) connected between the first wiring (SAP) and a first power supply circuit (for example, HVDD?Va) and a second transistor (N2) connected between the first wiring SAP and the second wiring (SAN). The equalizer circuit 50 makes the first transistor (N1) conductive, and then makes the second transistor (N2) conductive.Type: GrantFiled: August 23, 2007Date of Patent: March 23, 2010Assignee: NEC Electronics CorporationInventors: Takuya Hirota, Takao Yanagida, Hiroyuki Takahashi
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Patent number: 7683600Abstract: An output circuit in accordance with one embodiment of the present invention includes: an input terminal for receiving an input signal; an output transistor connected between a first power supply and an output terminal; a current control circuit connected to the input terminal and the output transistor for controlling current outflow and inflow for the gate of the output transistor based on the input signal; a voltage generating circuit connected to the first power supply; and a switch circuit coupled between the gate of the output transistor and the voltage generating circuit, the switch circuit having alternatively an on state and an off state thereof in response to the input signal; wherein the switch circuit becomes the off state when the potential difference between the gate of the output transistor and the first power supply becomes equal to or below a predetermine value regardless of the voltage level of the input signal.Type: GrantFiled: April 16, 2008Date of Patent: March 23, 2010Assignee: NEC Electronics CorporationInventors: Jiro Kanamaru, Toshiaki Akioka
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Patent number: 7684451Abstract: An optical transmitter module includes a semiconductor laser for outputting forward outgoing light and backward outgoing light, a temperature control device for controlling a temperature of the semiconductor laser, a beam splitter plate for receiving incidence of the backward outgoing light and outputting split light, which is reflected part of the backward outgoing light and transmitted light, which is part of the backward outgoing light, a first photoelectric conversion element for converting the split light into an electric signal. The beam splitter plate includes an anti-stray-light structure for preventing the transmitted light reflected by an incident surface of a wavelength filter from entering the first photoelectric conversion element through a side end surface portion of the beam splitter plate.Type: GrantFiled: August 23, 2007Date of Patent: March 23, 2010Assignee: NEC Electronics CorporationInventor: Shigenori Satou
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Patent number: 7683627Abstract: A resistance wiring and a judgement circuit for judging a potential in a middle of a path of the resistance wiring are provided on a periphery of a semiconductor chip. One end of the resistance wiring is connected to a power supply and the other end thereof is grounded. Connection points of the resistance wiring to the power supply and the ground are disposed at a corner on the periphery of the semiconductor chip, while a connection point of the resistance wiring to the judgement circuit is disposed at a corner diagonal to the corner on the periphery. When breakages such as chipping and peeling of an interlayer insulating film is caused on the periphery, resistance of the resistance wiring changes.Type: GrantFiled: July 12, 2007Date of Patent: March 23, 2010Assignee: NEC Electronics CorporationInventor: Masayuki Tsukuda
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Patent number: 7683375Abstract: A thin-film transistor includes a gate layer, a gate insulting layer, a semiconductor layer, a drain layer, a passivation layer (each of which being formed on or over an insulating substrate), and a conductive layer formed on the passivation layer. The conductive layer is connected to the gate layer or the drain layer by way of a contact hole penetrating at least the passivation layer. The passivation layer has a multiple-layer structure comprising at least a first sublayer and a second sublayer stacked, the first sublayer having a lower etch rate than that of the second sublayer. The first sublayer is disposed closer to the substrate than the second sublayer. The second sublayer has a thickness equal to or less than that of the conductive layer. The shape or configuration of the passivation layer and the underlying gate insulating layer can be well controlled in the etching process, and the conductive layer formed on the passivation layer is prevented from being divided.Type: GrantFiled: October 2, 2006Date of Patent: March 23, 2010Assignee: NEC LCD Technologies, Ltd.Inventor: Hiroaki Tanaka
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Patent number: 7683690Abstract: Provided is a multiphase clock generation circuit (1) including: a phase-locked loop circuit (10) for generating multiphase clock signals based on a reference clock signal; a frequency profile holding circuit (20) for holding a frequency profile of each of the multiphase clock signals, starting output of the frequency profile in response to a start signal, and for updating the frequency profile with a predetermined cycle based on the reference clock signal; and a clock selection circuit (30) for selecting a clock signal with an arbitrary phase from among the multiphase clock signals based on the frequency profile, and for feeding back the selected clock signal to the phase-locked loop circuit (10).Type: GrantFiled: October 29, 2007Date of Patent: March 23, 2010Assignee: NEC Electronics CorporationInventor: Yasuyuki Hiraku
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Patent number: 7683420Abstract: A nonvolatile memory semiconductor device and a method for manufacturing thereof are provided to avoid deterioration of the tunnel insulating film to increase frequency of writing data on the nonvolatile memory semiconductor device and erasing thereof. Concentration of atomic nitrogen in a tunnel insulating film 151 of a nonvolatile memory semiconductor device 1 is 0.1 to 5 atomic %. In addition, larger amount of atomic nitrogen in the tunnel insulating film 151 is distributed primarily in the interface layer of the tunnel insulating film 151, and concentration of atomic nitrogen in the interface layer is 10 times or more higher than concentration of atomic nitrogen in other portion of the tunnel insulating film 151. Further, density per unit area of atomic nitrogen in the surface of the tunnel insulating film 151 contacting with the floating gate is equal to or lower than 4×1014 atoms/cm2.Type: GrantFiled: July 26, 2006Date of Patent: March 23, 2010Assignee: NEC Electronics CorporationInventor: Shien Cho
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Patent number: 7684796Abstract: A mobile communication system includes a management agent, server, and temporary server. The management agent manages the destination of a mobile node. The server serves as a communication partner of the mobile node. The temporary server has a network function equivalent to that of the server. The management agent includes a position registration unit which registers position information of the destination of the mobile node when the mobile node moves, and a server function relocation unit which sets the temporary server as the communication partner of the mobile node instead of the server. A management agent apparatus and server function moving method are also disclosed.Type: GrantFiled: December 5, 2005Date of Patent: March 23, 2010Assignee: NEC CorporationInventor: Yasuhiro Mizukoshi
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Patent number: 7684133Abstract: A thermal contraction stress and a residual contraction stress caused by a difference between the linear expansion coefficients of an optical element unit and a carrier are reduced as much as possible. An optical module includes an optical element unit including optical elements requiring a stress control, and a carrier which supports the optical element unit. As the carrier is made of a material having the same property as that of the substrate material of the optical element, the thermal contraction stress is reduced.Type: GrantFiled: January 29, 2008Date of Patent: March 23, 2010Assignee: NEC CorporationInventors: Isao Tomita, Masaaki Nido, Taro Kaneko
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Patent number: 7683714Abstract: Disclosed is a differential amplifier which comprises a differential pair comprising depletion-type first and second N-channel MOS transistors, a first current source that supplies a current for the differential pair, a current mirror circuit formed by transistor pairs connected in cascode fashion in two stages, for connecting an output pair of the differential pair in folded connection, second and third current sources connected to an input terminal of the current mirror circuit and an output terminal of the current circuit, respectively, and a buffer amplifier with that has an input terminal connected to the output terminal of the current mirror circuit and has an output terminal connected to an output terminal of the differential amplifier.Type: GrantFiled: December 27, 2006Date of Patent: March 23, 2010Assignee: NEC Electronics CorporationInventors: Kouichi Nishimura, Atsushi Shimatani, Toshikazu Murata
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Publication number: 20100070508Abstract: When a collation result of user information is not matched, user information in one system need be prevented from being leaked to the other system. When hash values for an item serving as a key of correlation match with each other between a plurality of user information lists, it is determined that relevance is present, and then user information of the corresponding user is correlated.Type: ApplicationFiled: February 19, 2008Publication date: March 18, 2010Applicant: NEC CORPORATIONInventor: Masafumi Watanabe
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Publication number: 20100067161Abstract: An overcurrent detection circuit in accordance with an exemplary aspect of the present invention includes a detection transistor, a potential difference setting unit, and a first transistor whose current value is controlled by the potential difference setting unit. Further, the potential difference setting unit includes a first depletion type transistor, a power-supply voltage being supplied to the drain of the first depletion type transistor, and the gate and source of the first depletion type transistor being connected to the gate of the first transistor, a second transistor, the drain and gate of the second transistor being connected to the gate of the first transistor, and a second depletion type transistor provided on the current path between the sources of the first transistor and the second transistor, the gate and drain of the second depletion type transistor being connected to the source of the detection transistor.Type: ApplicationFiled: August 12, 2009Publication date: March 18, 2010Applicant: NEC ELECTRONICS CORPORATIONInventor: Sakae Nakajima
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Publication number: 20100070839Abstract: Processor 23 calculates a first remainder, which is a remainder produced when an integral multiple data block is divided by a generator poly-nomial, by processing bits represented by the number of parallel bits in parallel. The integral multiple data block comprises bits positioned closer to the leading end of the input data than a final word which is a word at the tail end of the input data, in the case where a plurality of bits making up the input data are successively divided from the leading end with respect to each word which comprises the bits represented by the number of parallel bits. Processor 23 calculates a second remainder, which is a remainder produced when a final word valid data block made up of bits of the input data other than the integral multiple data block is divided by the generator polynomial. Processor 23 calculates an input data remainder, which is a remainder produced when the input data are divided by the generator polynomial, based on the first remainder and the second remainder.Type: ApplicationFiled: September 10, 2009Publication date: March 18, 2010Applicant: NEC CORPORATIONInventors: Masahiro SHIGIHARA, Toru TAKAMICHI