Patents Assigned to NEC
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Patent number: 6337867Abstract: A multiplexor multiplexing an unlimited number of channels without the load on the multiplexor being increased. This multiplexor has a plurality of one channel encoders, for example four stages of encoders connected in series. When the first encoder is inputted with audio/video data of one channel, the data is inputted from the first encoder to the second encoder at the next stage, multiplexed by audio/video data of one channel inputted to the second encoder and then inputted to the third encoder at the next stage. By repeating this multiplexing, the number of multiplexed channels can be increased, and the load on the multiplexor is not increased because each encoder is inputted only with data for one channel. An abnormality detector is provided for each encoder to release an abnormal encoder from the multiplexor when the encoder's abnormality is detected.Type: GrantFiled: March 12, 1998Date of Patent: January 8, 2002Assignee: NEC CorporationInventor: Satoru Ejiri
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Patent number: 6337883Abstract: An apparatus for synchronously reproducing a video data and audio data includes a separating section, an audio data processing section, a video data processing section, and a synchronization processing section. The separating section separates a multiplexed compressed audio and video data into a compressed video data and a compressed audio data. The audio data processing section expands the compressed audio data to reproduce an audio data from the expanded audio data, and outputs the audio data to the synchronization processing section. The video data processing section expands the compressed video data in response to a control signal to reproduce a video data from the expanded video data, and outputs a signal indicative of each of frames, and a signal indicative of each of time stamps to the synchronization processing section.Type: GrantFiled: June 10, 1999Date of Patent: January 8, 2002Assignee: NEC CorporationInventor: Mitsumasa Tanaka
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Patent number: 6337598Abstract: A reference voltage generating device and method enables dissipation current to be reduced at the time of normal operation. An oscillator outputs a voltage of a low level intermittently during a prescribed time interval. An operational amplifier operates only when an output voltage of the oscillator is a low level. When the output voltage of the oscillator is a high level, a reference voltage “VREF” becomes a floating state so that a level is maintained by compensating the capacity of a capacitor C1. The reference voltage “VREF,” whose electric charge leaks due to a leak at the junction of a transistor, is maintained while operating the operational amplifier during a time interval T in a time period 10 T.Type: GrantFiled: February 29, 2000Date of Patent: January 8, 2002Assignee: NEC CorporationInventor: Kazuki Ohno
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Patent number: 6338108Abstract: A memory section and coprocessor sections in a coprocessor-integrated packet-type DRAM are provided with unique memory device ID and coprocessor device IDs respectively. The coprocessor-integrated packet-type DRAMs are connected to a single bus master type packet-type memory/coprocessor bus via external I/O terminals. A request packet is transmitted by the bus master to the packet-type memory/coprocessor bus, and each of the coprocessor-integrated packet-type DRAMs which received the request packet verifies a device ID field in the request packet against the memory device ID and the coprocessor device IDs stored in the coprocessor-integrated packet-type DRAM. If the device ID field matched, the request packet is decoded and memory access to the memory section or coprocessor access to the coprocessor section requested by the request packet is executed.Type: GrantFiled: April 14, 1998Date of Patent: January 8, 2002Assignee: NEC CorporationInventor: Masato Motomura
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Patent number: 6337890Abstract: A Viterbi decoder for Viterbi-decoding an input signal, includes a path memory, a shift register, and a traceback circuit. The shift register has at least (constraint length −1) bits as the number of stages. The traceback circuit inputs, to the shift register, the AND per bit between a signal generated by a decoder connected to the shift register and the content of the path memory designated by a traceback address counter.Type: GrantFiled: August 28, 1998Date of Patent: January 8, 2002Assignee: NEC CorporationInventor: Tsuguo Maru
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Patent number: 6337582Abstract: A buffer circuit is provided, which suppresses the fluctuation or deviation of the power supply voltage and the ground voltage that are caused by the logic state change of an address signal applied thereto. The buffer circuit comprises (a) a first inverter circuit having the CMOS configuration; (b) a second inverter circuit having the CMOS configuration; and (c) an equalization circuit for equalizing the first output signal of the first inverter circuit and the second output signal of the second inverter circuit. Each of the first and second inverter circuits is activated or inactivated by a control signal. When the first and second inverter circuits are activated, the equalization circuit is set in the high-impedance state, in which the first inverter circuit generates a first output signal at its output terminal and the second inverter circuit generates a second output signal at its output terminal.Type: GrantFiled: October 18, 2000Date of Patent: January 8, 2002Assignee: NEC CorporationInventor: Syuhei Yoshioka
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Patent number: 6337248Abstract: Manufactured is a semiconductor device that has a substrate and a surface channel nMOS and a buried channel nMOS as well as a surface channel pMOS and a buried channel pMOS formed on the substrate. An n+ dopant is introduced prior to pattering a polycrystalline semiconductor layer that forms respective gate electrodes of the surface channel nMOS and the buried channel pMOS. A p+ dopant is also introduced prior to pattering a polycrystalline semiconductor layer that forms respective gate electrodes of the surface channel pMOS and the buried channel nMOS.Type: GrantFiled: August 19, 1999Date of Patent: January 8, 2002Assignee: NEC CorporationInventor: Kiyotaka Imai
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Patent number: 6337438Abstract: A casing structure for a communication equipment in which panels mounted in the casing are electrically insulated from a messenger wire. When the casing of the communication equipment is mounted on the messenger wire, the insulation prohibits impediments otherwise caused by extraneous noise current flowing in the messenger wire. The mounting portion of the case has a handle structure which provides improved operability and convenience.Type: GrantFiled: November 10, 1997Date of Patent: January 8, 2002Assignee: NEC CorporationInventor: Takashi Oyamada
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Patent number: 6337514Abstract: A cell plate electrode is shared between storage capacitors of memory cells incorporated in a semiconductor dynamic random access memory device of the type having the storage capacitors over bit lines, and slits are formed in the cell plate electrode in such a manner that the boundaries between channel regions and gate oxide layers are horizontally spaced from the outer periphery of the cell plate electrode and the slits by distances equal to or less than a critical distance determined on the basis of a diffusion length of hydrogen in an inter-level insulating layer, thereby causing the hydrogen to surely reach the boundaries for reducing the density of surface state.Type: GrantFiled: December 16, 1998Date of Patent: January 8, 2002Assignee: NEC CorporationInventor: Mitsuma Ooishi
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Patent number: 6337810Abstract: The provision of a semiconductor memory device for which access times in burst mode can be improved with no increase in the chip surface area and with no increase in power consumption. A latch pulse selection circuit 6 uses a control signal CA0T to output an input control signal SALF and a control signal SALS, to a first latch group within a latch circuit 7 as a latch pulse SAL0A, and to a second latch group within the latch circuit 7 as a latch pulse SAL1A, respectively. Based on a control signal YS0˜YS31 input from a column decoder circuit 11, a Y selector 12 is connected to a sense amplifier circuit 8 via Y switches connected to the corresponding digit lines. The sense amplifier circuit 8 comprises 256 sense amplifiers, and performs data evaluations of the signal YD0˜signal YD127 from the Y selector.Type: GrantFiled: October 12, 2000Date of Patent: January 8, 2002Assignee: NEC CorporationInventors: Kazuyuki Yamasaki, Tonomi Egawa
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Patent number: 6337272Abstract: A method of manufacturing a semiconductor device in which a cobalt silicide layer is formed on a semiconductor substrate. In the method, the semiconductor substrate is prepared, and cobalt is deposited on the semiconductor substrate by sputtering while heating the semiconductor substrate at a temperature approximately equal to 200 degrees Celsius. Thereafter, cobalt is deposited on the semiconductor substrate by sputtering while heating the semiconductor substrate at a temperature between 300 degrees Celsius and 400 degrees Celsius without exposing the semiconductor substrate to the atmosphere. Preferably, the semiconductor substrate is thereafter rapid thermal annealed at a temperature equal to or higher than 500 degrees Celsius in nitrogen atmosphere for a predetermined time. Further, at least a part of cobalt portion or cobalt oxide portion on the semiconductor substrate is removed by wet etching.Type: GrantFiled: February 17, 2000Date of Patent: January 8, 2002Assignee: NEC CorporationInventor: Nobuaki Hamanaka
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Patent number: 6337870Abstract: In the pattern of a selective growth mask for directly forming an active layer, open stripes for growing recombination layers to be inserted into a current blocking are formed in addition to an open stripe for growing the active layer. By this mask pattern, the position and band gap of the recombination layers are controlled. Whereby, at an arbitrary position in the vicinity of the active layer, recombination layers having an arbitrary band gap can be batch formed together with the active layer. Thus, a semiconductor laser element with an excellent high-temperature high-output characteristic can be fabricated with good uniformity and reproducibility.Type: GrantFiled: October 20, 1998Date of Patent: January 8, 2002Assignee: NEC CorporationInventor: Yuji Furushima
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Patent number: 6337252Abstract: There is provided a method of manufacturing a semiconductor device which can use commonly a part of a step of forming a PAP transistor with a step of forming an NON transistor. In an area separated by a side separation region (5) of PNP formed by doping N-type impurities simultaneously with the formation of the collector region (4) of NPN, an N-type bottom separation region (8) of PNP, a collector region (9) and a base region (10) are formed by using the same mask. Trenches (18, 17) extending to the collector regions (9, 4) are formed by an over-etching treatment carried out when the emitter electrodes (16, 15) of PNP and NPN are subjected to a patterning treatment, and N-type impurities are doped through the trench (17) simultaneously with the formation of an external base region (20) of PNP, thereby forming a collector drawing region (21) of NPN.Type: GrantFiled: May 21, 1999Date of Patent: January 8, 2002Assignee: NEC CorporationInventor: Hiroshi Yoshida
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Patent number: 6336724Abstract: In a projector device for magnifically projecting onto a screen a beam of light emitted from a light source which is irradiated at a mirror reflecting type light modulator after being color-separated into light beams of three primary colors and after respective light beams of primary colors modulated in the mirror reflecting type light modulator are synthesized by a color prism, a light beam emitted from a first light source is polarized into an “p” polarization by a polarization converter and a light beam emitted from a second light source is polarized into a “s” polarization by the polarization converter, thereby both light beams are synthesized by a polarization beam splitter.Type: GrantFiled: December 17, 1999Date of Patent: January 8, 2002Assignee: NEC CorporationInventors: Eisaku Shouji, Takayuki Matsumoto, Katsuyuki Takeuchi
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Patent number: 6336463Abstract: A production line includes a centralized cleaning/drying station for cleaning a wafer by using an HF cleaning solution or a non-HF cleaning solution and subsequently drying the wafer based on the desired cleaning/drying conditions, and a transport system for transporting the wafer between each processing station and the centralized cleaning/drying station. The production line has a large flexibility for selecting the cleaning/drying conditions for the wafer with a reduced system size.Type: GrantFiled: March 30, 1999Date of Patent: January 8, 2002Assignee: NEC CorporationInventor: Nahomi Ohta
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Patent number: 6337979Abstract: A PDC communication controlling apparatus includes an audio processing section for converting a digital audio signal which has been encoded at a transmission rate of a personal digital cellular (PDC) into a digital audio signal at a transmission rate of a digital exchange network, a small radio base station controlling section accommodating a plurality of small radio base stations which are connected to PDC portable terminal units through radio circuits and which have different radio cover areas, the small radio base station controlling section managing the radio cover areas of the PDC portable terminal units, controlling calls, and controlling and managing the radio circuits, a network-side adaptor used in non-audio communications with the PDC portable terminal units, a PDC/network interface section connected to a private branch exchange through a plurality of communication paths, a time division switch for connecting the PDC/network interface, the audio processing section, the radio base station controllingType: GrantFiled: June 29, 1998Date of Patent: January 8, 2002Assignee: NEC CorporationInventor: Kanada Nakayasu
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Patent number: 6336975Abstract: A thin film forming equipment and a method for forming thin films are provided which are capable of forming the thin film of high quality and of effectively preventing CVD material gas from leaking to surroundings at a low cost. The thin film equipment contains a substrate, a substrate holding device used to hold the substrate and a device used to provide an atmospheric gas to a surface of the substrate held by the substrate holding device, wherein an upper face of the substrate held by the substrate holding device and an upper face of the substrate holding device are almost on one plane.Type: GrantFiled: March 22, 2000Date of Patent: January 8, 2002Assignee: NEC CorporationInventors: Yukio Morishige, Makoto Omiya
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Patent number: 6338061Abstract: In a symbol string search method of performing an approximate matching for a target symbol string from a symbol string to be searched by allowing insertion/deletion/replacement of symbols of not more than a designated number of times, the approximate matching is performed by using pieces of transposition information storing appearance positions of symbols in a preformed symbol string to be searched. A symbol string search apparatus and a recording medium recording a symbol string search program are also disclosed.Type: GrantFiled: January 14, 1999Date of Patent: January 8, 2002Assignee: NEC CorporationInventor: Hideki Shimomura
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Patent number: 6337936Abstract: An optical amplifier comprises an optical circulator and an optical fiber grating connected to this. The optical fiber grating reflects a backscattered light of a probe light coming back from an optical fiber transmission path. The optical circulator returns this reflected light through said optical fiber transmission path to an optical receiver. A method for monitoring an optical fiber transmission path comprises a step of sending out a probe light having a specific wavelength to an optical fiber transmission path, a step of selecting a backscattered light of this probe light, and a step of receiving this light through said optical fiber transmission path and measuring a time change in level of this light.Type: GrantFiled: February 17, 2000Date of Patent: January 8, 2002Assignee: NEC CorporationInventor: Kenichi Yoneyama
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Patent number: 6338035Abstract: A voice-input document creation system which reduces correction times to a wrongly-recognized input to ensure input efficiency. The system has a determination means for comparing the feature content of a newest voice input extracted by a feature extracting module with a feature content of an immediately preceding voice input to determine if the newest voice input is a correction to the immediately preceding voice input. When a first-time correction is received, the system displays a list of all output candidates for the immediately preceding voice input stored in a second memory. When a second-time correction is received, the system stores the output candidates for the newest voice input into a third memory and, at the same time, displays the output candidates; at this time, the system neither displays nor stores in the third memory those output candidates displayed upon the first-time correction.Type: GrantFiled: December 28, 1998Date of Patent: January 8, 2002Assignee: NEC CorporationInventor: Ichiro Mori