Abstract: A system and method for configuring fault tolerance in nonvolatile memory (NVM) are operative to set a first threshold value, declare one or more portions of NVM invalid based on an error criterion, track the number of declared invalid NVM portions, determine if the tracked number exceeds the first threshold value, and if the tracked number exceeds the first threshold value, perform one or more remediation actions, such as issue a warning or prevent backup of volatile memory data in a hybrid memory system. In the event of backup failure, an extent of the backup can still be assessed by determining the amount of erased NVM that has remained erased after the backup, or by comparing a predicted backup end point with an actual endpoint.

Abstract: According to certain aspects, a memory subsystem is coupled to a memory controller of a host computer system via an interface. The memory subsystem comprises dynamic random access memory elements and a memory subsystem controller. During a normal memory read or write operation, the memory subsystem controller is configured to receive address and command signals associated with the memory read or write operations and to control the dynamic random access memory elements in accordance with the address and command signals. The memory subsystem controller is further configured to output via the open drain output a parity error signal in response to a parity error having occurred during the memory read or write operation. During an initialization operation, the memory subsystem controller is configured to output via the open train output a signal related to one or more parts of initialization operation sequences.

Abstract: A memory system that has a multi-channel volatile memory subsystem is coupled to a non-volatile memory subsystem to provide independent, configurable backup of data. The volatile memory subsystem has one or more main memory modules that use a form of volatile memory such as DRAM memory, for which the NV subsystem provides selective persistent backup. The main memory modules are dual in-line memory modules or DIMMs using DDR SDRAM memory devices. The non-volatile memory subsystem (NV backup) includes an NV controller and non-volatile memory NVM. The NV backup can also include a memory cache to aid with handling and storage of data. In certain embodiments, the NV controller and the nonvolatile memory are coupled to the one or more DIMM channels of the main memory via associated signal lines. Such signal lines can be, for example, traces on a motherboard, and may include one or more signal buses for conveying data, address, and/or control signals.

Abstract: A memory module is operable in a computer system to communicate data with a system memory controller via a system memory bus. The memory module comprises a plurality of memory devices mounted on a circuit board, a data module mounted on the circuit board and coupled between the plurality of memory devices and the system memory bus, and a control circuit mounted on the circuit board and coupled to the data module, the plurality of memory devices, and the system memory bus. The data module includes a plurality of data handlers in a plurality of integrated circuits. The memory module is operable in any of a plurality of modes, including a first mode and a second mode. The plurality of memory devices in the first mode is accessed by the system memory controller for normal memory read or write operations.

Abstract: A system and method for configuring fault tolerance in nonvolatile memory (NVM) are operative to set a first threshold value, declare one or more portions of NVM invalid based on an error criterion, track the number of declared invalid NVM portions, determine if the tracked number exceeds the first threshold value, and if the tracked number exceeds the first threshold value, perform one or more remediation actions, such as issue a warning or prevent backup of volatile memory data in a hybrid memory system. In the event of backup failure, an extent of the backup can still be assessed by determining the amount of erased NVM that has remained erased after the backup, or by comparing a predicted backup end point with an actual endpoint.

Abstract: The present application presents a Uniform Memory Access (UMA) network including a cluster of UMA nodes. A system in a UMA node comprises persistent memory; non-persistent memory, a node control device operatively coupled to the persistent memory and the non-persistent memory, a local interface for interfacing with the local server in the respective UMA node, and a network interface for interfacing with the UMA network. The node control device is configured to translate between a local unified memory access (UMA) address space accessible by applications running on a local server and a global UMA address space that is mapped to a physical UMA address space. The physical UMA address space includes physical address spaces associated with different UMA nodes in the cluster of UMA nodes. Thus, a server in the UMA network can access the physical address spaces at other UMA nodes without going through the servers in the other UMA nodes.

Abstract: A memory module is operable in a memory system with a memory controller. The memory module comprises memory devices, a module control circuit, and a plurality of buffer circuits coupled between respective sets of data signal lines in a data bus and respective sets of the memory devices. Each respective buffer circuit is mounted on the module board and coupled between a respective set of data signal lines and a respective set of memory devices. Each respective buffer circuit is configured to receive the module control signals and the module clock signal, and to buffer a respective set of data signals in response to the module control signals and the module clock signal. Each respective buffer circuit includes a delay circuit configured to delay the respective set of data signals by an amount determined based on at least one of the module control signals.

Abstract: A memory module comprises a volatile memory subsystem including DRAM, a non-volatile memory subsystem including Flash memory, and a module control device. The Flash memory includes main Flash providing a main Flash memory space and scratch Flash providing a scratch Flash memory space. The module control device is configured to receive a request from the memory controller to move one or more segments of data in a first Flash block in the main Flash to the DRAM and to, for each respective segment of data: select a respective set of pages in the DRAM; transfer respective data stored in the respective set of pages from the DRAM to a corresponding segment in the scratch Flash; and transfer the respective segment of data to the respective set of pages in the DRAM. Thus, data can be moved segment by segment between the DRAM and the Flash memory.

Abstract: A memory module comprises a volatile memory subsystem, a non-volatile memory subsystem, and a module controller coupled to the volatile memory subsystem and to the non-volatile memory subsystem. The module controller is configurable to control data transfers between the volatile memory subsystem and the non-volatile memory subsystem. The module controller includes a data selection circuit configurable to pre-search data transferred from the non-volatile memory with respect to one or more search criteria before providing the pre-select data relevant to the one or more search criteria to the volatile memory subsystem.

Abstract: A memory system that has a multi-channel volatile memory subsystem is coupled to a non-volatile memory subsystem to provide independent, configurable backup of data. The volatile memory subsystem has one or more main memory modules that use a form of volatile memory such as DRAM memory, for which the NV subsystem provides selective persistent backup. The main memory modules are dual in-line memory modules or DIMMs using DDR SDRAM memory devices. The non-volatile memory subsystem (NV backup) includes an NV controller and non-volatile memory NVM. The NV backup can also include a memory cache to aid with handling and storage of data. In certain embodiments, the NV controller and the non-volatile memory are coupled to the one or more DIMM channels of the main memory via associated signal lines. Such signal lines can be, for example, traces on a motherboard, and may include one or more signal buses for conveying data, address, and/or control signals.

Abstract: A memory module according to some embodiments is operable in a computer system, and comprises a volatile memory subsystem and a module controller coupled to the volatile memory subsystem. The volatile memory subsystem is configurable to be coupled to a memory channel including a data bus, and includes dynamic random access memory (DRAM) devices. The memory module allows independent control of strobe paths and data paths between the DRAM devices and the data bus, and is configurable to perform a memory write operation during which write data is provided to the volatile memory subsystem together with write strobes transmitted via first strobe paths between the DRAM devices and the data bus, and a memory read operation during which read data from the volatile memory subsystem is output onto the data bus together with read strobes transmitted via second strobe paths between the module controller and the data bus.

Abstract: A memory module is operable in a memory system with a memory controller. The memory module comprises a module control device to receive command signals and a system clock from the memory controller and to output a module clock, module C/A signals and data buffer control signals. The module C/A signals are provided to memory devices organized in one or more ranks, while the data buffer control signals, together with the module clock, are provided to a plurality of buffer circuits corresponding to respective groups of memory devices and are used to control data paths in the buffer circuits. The plurality of buffer circuits include clock regeneration circuits to regenerate clock signals with programmable delays from the module clock. The regenerated clock signals are provided to respective groups of memory devices so as to locally sync the buffer circuits with respective groups of memory devices.

Abstract: A memory expansion device operable with a host computer system (host) comprises a non-volatile memory (NVM) subsystem, cache memory, and control logic configurable to receive a submission from the host including a read command and specifying a payload in the NVM subsystem and demand data in the payload. The control logic is configured to request ownership of a set of cache lines corresponding to the payload, to indicate completion of the submission after acquiring ownership of the cache lines, and to load the payload to the cache memory. The set of cache lines correspond to a set of cache lines in a coherent destination memory space accessible by the host. The control logic is further configured to, after indicating completion of the submission and in response to a request from the host to read demand data in the payload, return the demand data after determining that the demand data is in the cache memory.

Abstract: In certain embodiments, a memory module includes a printed circuit board (PCB) having an interface that couples it to a host system for provision of power, data, address and control signals. First, second, and third buck converters receive a pre-regulated input voltage and produce first, second and third regulated voltages. A converter circuit reduces the pre-regulated input voltage to provide a fourth regulated voltage. Synchronous dynamic random access memory (SDRAM) devices are coupled to one or more regulated voltages of the first, second, third and fourth regulated voltages, and a voltage monitor circuit monitors an input voltage and produces a signal in response to the input voltage having a voltage amplitude that is greater than a threshold voltage.

Abstract: According to certain embodiments, a memory module is operable with a memory controller of a host system. The memory module includes a module controller configurable to receive address and control signals from the memory controller, and dynamic random access memory elements configurable to communicate data signals with the memory controller in accordance with the address and control signals. The module controller has an open-drain output and is configurable to drive the open-drain output with a first signal to indicate a parity error having occurred when the memory module is being accessed for a normal memory read or write operation. The module controller is further configurable to drive the open drain output with a second signal related to one or more training sequences when the memory module performs operations associated with the one or more training sequences and not associated with any normal memory read or write operations.

Abstract: A system and method for configuring fault tolerance in nonvolatile memory (NVM) are operative to set a first threshold value, declare one or more portions of NVM invalid based on an error criterion, track the number of declared invalid NVM portions, determine if the tracked number exceeds the first threshold value, and if the tracked number exceeds the first threshold value, perform one or more remediation actions, such as issue a warning or prevent backup of volatile memory data in a hybrid memory system. In the event of backup failure, an extent of the backup can still be assessed by determining the amount of erased NVM that has remained erased after the backup, or by comparing a predicted backup end point with an actual endpoint.

Abstract: A memory system that has a multi-channel volatile memory subsystem is coupled to a non-volatile memory subsystem to provide independent, configurable backup of data. The volatile memory subsystem has one or more main memory modules that use a form of volatile memory such as DRAM memory, for which the NV subsystem provides selective persistent backup. The main memory modules are dual in-line memory modules or DIMMs using DDR SDRAM memory devices. The non-volatile memory subsystem (NV backup) includes an NV controller and non-volatile memory NVM. The NV backup can also include a memory cache to aid with handling and storage of data. In certain embodiments, the NV controller and the non-volatile memory are coupled to the one or more DIMM channels of the main memory via associated signal lines. Such signal lines can be, for example, traces on a motherboard, and may include one or more signal buses for conveying data, address, and/or control signals.

Abstract: A memory module comprises a volatile memory subsystem configured to coupled to a memory channel in computer system and capable of serving as main memory for the computer system, a non-volatile memory subsystem providing storage for the computer system, and a module controller coupled to the volatile memory subsystem, the non-volatile memory subsystem, and the C/A bus. The module controller is configured to control intra-module data transfers between the volatile memory subsystem and the non-volatile memory subsystem. The module controller is further configured to monitor C/A signals on the C/A bus and schedule the intra-module data transfers in accordance with the C/A signals so that the intra-module data transfers do not conflict with accesses to the volatile memory subsystem by the memory controller.

Abstract: In certain embodiments, a memory module includes a printed circuit board (PCB) having an interface that couples it to a host system for provision of power, data, address and control signals. First, second, and third buck converters receive a pre-regulated input voltage and produce first, second and third regulated voltages. A converter circuit reduces the pre-regulated input voltage to provide a fourth regulated voltage. Synchronous dynamic random access memory (SDRAM) devices are coupled to one or more regulated voltages of the first, second, third and fourth regulated voltages, and a voltage monitor circuit monitors an input voltage and produces a signal in response to the input voltage having a voltage amplitude that is greater than a threshold voltage.

Abstract: A system and method for configuring fault tolerance in nonvolatile memory (NVM) are operative to set a first threshold value, declare one or more portions of NVM invalid based on an error criterion, track the number of declared invalid NVM portions, determine if the tracked number exceeds the first threshold value, and if the tracked number exceeds the first threshold value, perform one or more remediation actions, such as issue a warning or prevent backup of volatile memory data in a hybrid memory system. In the event of backup failure, an extent of the backup can still be assessed by determining the amount of erased NVM that has remained erased after the backup, or by comparing a predicted backup end point with an actual endpoint.