Patents Assigned to NetLogic Microsystems, Inc.
  • Configurable non-volatile logic structure for characterizing an integrated circuit device
    Patent number: 7589362
    Abstract: An integrated circuit (IC) device including a substrate, a plurality of device layers formed over the substrate, and a plurality of multi-level revision (MLR) structures that generate a revision code indicative of device revisions. Each MLR group structure includes a number of MLR cells and includes a parity circuit having a number of inputs coupled to the outputs of the MLR cells and having an output to generate a corresponding bit of the revision code. The MLR cells in each MLR group structure are assigned to different device layers, and each device layer is assigned to one MLR cell in each MLR group structure. Each revision code bit is controllable by any MLR cell in the corresponding MLR group structure.
    Type: Grant
    Filed: June 15, 2007
    Date of Patent: September 15, 2009
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Dimitri Argyres, Bindiganavale S. Nataraj
  • Controlling a searchable range within a network search engine
    Patent number: 7581059
    Abstract: Controlling a searchable range within a network search engine. A CAM array is provided within the network search engine to store data values in entries having respective addresses and to compare the data values with a search key. First address and a second addresses that define a range of the addresses are received at an interface of the network search engine, and range-control circuitry is provided within the network search engine to generate a hit signal having either a first state or a second state according to whether any of the entries having addresses within the range of addresses match the search key.
    Type: Grant
    Filed: July 27, 2006
    Date of Patent: August 25, 2009
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Pankaj Gupta, Srinivasan Venkalachary
  • Full-ternary content addressable memory (CAM) configurable for pseudo-ternary operation
    Patent number: 7577784
    Abstract: A ternary content addressable memory (TCAM) system and method of operating the same can enable a user to configure the system to operate as either a pseudo TCAM or full TCAM system. Control logic (206) can have an address modification circuit (250) coupled between multiple inputs and row decoders (206-0 and 206-1) for simultaneously writing the same mask value to mask fields of a predetermined number of memory locations in a full TCAM array.
    Type: Grant
    Filed: December 13, 2004
    Date of Patent: August 18, 2009
    Assignee: Netlogic Microsystems, Inc.
    Inventor: Scott Smith
  • Network device, storage medium and methods for incrementally updating a forwarding database
    Patent number: 7571156
    Abstract: Network devices, storage mediums and methods for updating a memory structure in a data plane of the network device when route updates are received in the control plane of the network device. The methods described herein can be used to perform one of the following algorithms: a Basic Incremental Split-Merge (BISM) algorithm, a Lazy Incremental Split-Merge (LISM) algorithm, and a Down-support Split-Merge (DSM) algorithm. Each of the algorithms described herein may be used to incrementally update portions of a forwarding database stored within the memory structure, where the updated portions correspond to only those portions affected by the route updates.
    Type: Grant
    Filed: March 25, 2004
    Date of Patent: August 4, 2009
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Pankaj Gupta, Srinivasan Venkatachary
  • Ternary content addressable memory (TCAM) cells with low signal line numbers
    Patent number: 7570503
    Abstract: A ternary content addressable memory (TCAM) cell circuit formed in a TCAM memory cell array having cells arranged in rows and columns can include a first storage circuit with first and second data path, a second storage circuit with a third and fourth data path, and a compare circuit. No more than four conductive lines in a column wise direction have a direct electrical connection to the TCAM cell. Such conductive lines can include a first bit line coupled to the first data path and the third data path and a second bit line coupled to the second data path and the fourth data path.
    Type: Grant
    Filed: May 22, 2006
    Date of Patent: August 4, 2009
    Assignee: Netlogic Microsystems, Inc.
    Inventors: Dinesh Maheshwari, Andrew Wright, Bin Jiang, Bartosz Banachowicz
  • Memory optimized pattern searching
    Patent number: 7565380
    Abstract: A method of modifying a finite state machine (FSM) wherein the FSM is accessed by a plurality of entries, with each entry comprised of a substring and a next-state pointer, and the FSM is modified so that each entry comprises a length, which is less than or equal to a maximum size boundary placed on a memory device configured for storing the FSM.
    Type: Grant
    Filed: March 24, 2006
    Date of Patent: July 21, 2009
    Assignee: NetLogic Microsystems, Inc.
    Inventor: Srinivasan Venkatachary
  • Method and device for scalable multiple match extraction from search data
    Patent number: 7565482
    Abstract: A search engine system (100) compares search key values to stored entry values, and includes first blocks of entries (102) and second blocks of entries (104). First blocks of entries (102) can be “search” blocks that can provide a relatively fast search speed of stored data value, and each store a unique first portion of one or more entry values. Second blocks of entries (104) can be randomly accessible entries logically arranged into search nodes that each correspond to a first portion of an entry value stored in the first block of entries. Each search node can include one or more second portions of an entry value.
    Type: Grant
    Filed: December 13, 2006
    Date of Patent: July 21, 2009
    Assignee: Netlogic Microsystems, Inc.
    Inventors: Anand Rangarajan, Srinivasan Venkatachary
  • Content addressable memory (CAM) device and method for flexible suppression of hit indications
    Patent number: 7565481
    Abstract: A content addressable memory (CAM) device (200) can provide for suppression of hit indications. Prioritized match indications (212) can be applied in parallel to both an encoding read-only-memory (ROM) (204-1) and suppression data store (206). A suppression data store (206) can output suppression bits (SH0 and SH1) that correspond to each CAM entry. Hit indications can be selectively suppressed according the values of suppression bits (SH0 and SH1). Hit suppression methods for a CAM device are also disclosed.
    Type: Grant
    Filed: October 29, 2004
    Date of Patent: July 21, 2009
    Assignee: Netlogic Microsystems, Inc.
    Inventor: Hari Om
  • Range representation in a content addressable memory (CAM) using an improved encoding scheme
    Patent number: 7555594
    Abstract: In a method and apparatus for encoding a bit field within a memory device, the bit field is encoded in a manner that requires fewer memory device entries and fewer encoded bits per entry than conventional encoding schemes.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: June 30, 2009
    Assignee: NetLogic Microsystems, Inc.
    Inventor: Srinivasan Venkatachary
  • Simultaneous multi-threading in a content addressable memory
    Patent number: 7555593
    Abstract: A CAM device having two execution pipelines includes control logic and a CAM core. The CAM core includes a plurality of independently searchable CAM arrays for storing CAM words. The control logic receives a first request that selects any number of the CAM arrays for a first compare operation, and receives a second request that selects any number of the CAM arrays for a second, separate compare operation. The control logic determines whether the same CAM array is selected by both requests. If not, the control logic schedules the first and second compare operations to be executed simultaneously in the CAM core. Otherwise, the control logic schedules the first and second compare operations for sequential executionuses a suitable arbitration technique to determine the order in which the first and second compare operations will be executed in the CAM core.
    Type: Grant
    Filed: January 31, 2006
    Date of Patent: June 30, 2009
    Assignee: NetLogic Microsystems, Inc.
    Inventor: Andrew Rosman
  • Content addressable memory with twisted data lines
    Patent number: 7545661
    Abstract: A content addressable memory (CAM) device having CAM cells arranged in rows and columns. A plurality of pairs of data lines extend along respective columns of the CAM cells, each pair of data lines including at least one data line that is formed by conductive segments disposed in two different conductivity layers of the CAM device.
    Type: Grant
    Filed: October 22, 2007
    Date of Patent: June 9, 2009
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Varadarajan Srinivasan, Sandeep Khanna
  • Inexact pattern searching using bitmap contained in a bitcheck command
    Patent number: 7539031
    Abstract: A search circuit for determining whether an input string including a plurality of input characters matches an inexact pattern including a number of pattern characters that are members of a specified character set, the search circuit including an input for receiving a bitcheck command, the bitcheck command containing a bitmap including a plurality of compliance bits each indicating whether a corresponding one of a plurality of reference characters of a general character set is a member of the specified character set, and a circuit for referencing each of the input characters to a corresponding compliance bit in the bitmap to determine whether the input character are members of the specified character set.
    Type: Grant
    Filed: September 19, 2006
    Date of Patent: May 26, 2009
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Ajit V. Ninan, Alexander Y. Levitskiy
  • Regular expression searching of packet contents using dedicated search circuits
    Patent number: 7539032
    Abstract: A network system includes a content search system for determining whether an input string matches a regular expression comprising an exact pattern and an inexact pattern, the content search system including a first search circuit dedicated to perform an exact string match operation to determine whether the input string contains a first portion that matches the exact pattern, and a second search circuit dedicated to perform an inexact string match operation to determine whether the input string contains a second portion that matches the inexact pattern.
    Type: Grant
    Filed: September 19, 2006
    Date of Patent: May 26, 2009
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Michael E. Ichiriu, Martin Fabry, Larry A. Wall, Sanjay Sreenath
  • Search circuit having individually selectable search engines
    Patent number: 7529746
    Abstract: A content search circuit for determining whether an input string matches one or more of a plurality of regular expressions, the content search circuit including an instruction memory for storing a plurality of microprograms, each microprogram embodying a corresponding one of the regular expressions, a control circuit having an input to receive the input string, and having a number of outputs, and a plurality of search engines, each having a first input coupled to a corresponding output of the control circuit and having a second input coupled to the instruction memory, wherein each search engine is selectable to execute any of the microprograms stored in the instruction memory to search the input string for any of the regular expressions embodied in the microprograms.
    Type: Grant
    Filed: September 19, 2006
    Date of Patent: May 5, 2009
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Michael E. Ichiriu, Martin Fabry, Larry A. Wall, Sanjay Sreenath
  • Content addressable memory with multi-row write function
    Patent number: 7505295
    Abstract: A content addressable memory (CAM) device having a multi-row write function. The CAM device includes a CAM array and an address circuit. The CAM array includes a plurality of CAM cells and word lines coupled to respective rows of the CAM cells. The address circuit is coupled to the CAM array and configured to activate a plurality of the word lines simultaneously to enable a write value to be stored within a selected plurality of the rows of CAM cells.
    Type: Grant
    Filed: July 1, 2004
    Date of Patent: March 17, 2009
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Bindiganavale S. Nataraj, Sandeep Khanna
  • Method and apparatus for performing priority encoding in a segmented classification system
    Patent number: 7487200
    Abstract: A digital signal processor. The digital signal processor includes a first data classification block. The first data classification block outputs a first block priority number associated with a first data stored in the first data classification block that matches a search key. The digital signal processor includes a second data classification block. The second data classification block outputs a second priority number associated with a second data stored in the second data classification block that matches the search key. The digital signal processor includes a device index processor. The device index processor selects a most significant block priority number from the first block priority number and the second block priority number.
    Type: Grant
    Filed: December 5, 2000
    Date of Patent: February 3, 2009
    Assignee: NetLogic Microsystems, Inc.
    Inventor: Varadarajan Srinivasan
  • Random access memory (RAM) method of operation and device for search engine systems
    Patent number: 7474586
    Abstract: A search engine system (100) is disclosed that can include at least one content addressable memory (CAM) device (102) arranged in a cascade configuration with at least one memory device (104), such as a static random access memory (SRAM). A CAM device (102) and memory device (104) may be connected to one another by point-to-point unidirectional connections. Command data issued by a device, such as a network processing unit (NPU) (110), can flow through all devices beginning with a CAM device (102) and eventually to a memory device (104). A memory device (104) can compare its own current result data with that of a previous device in a flow (such as another RAM device), and generate an output response.
    Type: Grant
    Filed: April 25, 2008
    Date of Patent: January 6, 2009
    Assignee: Netlogic Microsystems, Inc.
    Inventors: David V. James, Jagadeesan Rajamanickam
  • Soft priority circuit and method for content addressable memory (CAM) device
    Patent number: 7474545
    Abstract: A content addressable memory (CAM) device can include a plurality of CAM super-blocks each comprising a plurality of sub-blocks. Each sub-block can include a plurality of CAM entries that generate match results in response to a key value. For each sub-block there can be storage for a programmable local priority value that establishes priority of match results of the sub-block with respect to match results of the other sub-blocks of the same CAM super-block. In addition, for each sub-block there can be a programmable global priority value, different from the programmable local priority value, that establishes priority of match indications of the sub-block with respect to match results of sub-blocks of the plurality of CAM super-blocks.
    Type: Grant
    Filed: June 13, 2006
    Date of Patent: January 6, 2009
    Assignee: NetLogic Microsystems, Inc.
    Inventor: Dinesh Maheshwari
  • Method and apparatus for overlaying flat and tree based data sets onto content addressable memory (CAM) device
    Patent number: 7461200
    Abstract: A content addressable memory device (100) and method can have CAM blocks (102-0 to 102-29) organized in block sections (104-0 to 104-6). In an overlay mode of operation, an overlay engine (106) can access an algorithmic search (SPEAR) CAM (102-28 and 102-29) to generate overlay data set search keys (keyFIB<0> and <1>). Multiple data sets (e.g., FIB0, FIB1, ACL0) can be accommodated on the same CAM device by search key multiplexers (108-0 to 108-6) that selectively apply any of a number of data set search keys (keyACL<0>, keyFIB<0> and keyFIB<1>).
    Type: Grant
    Filed: September 23, 2004
    Date of Patent: December 2, 2008
    Assignee: Netlogic Microsystems, Inc.
    Inventors: Mark Birman, Ajay Srikrishna, Srinivasan Venkatachary
  • Content addressable memory (CAM) devices that perform pipelined multi-cycle look-up operations using cam sub-arrays and longest match detection
    Patent number: RE40932
    Abstract: A CAM system is provided for determining which data word in a CAM array exhibits the longest continuous, unmasked match with an input data value. The input data value is divided into non-overlapping subfields, thereby creating a series of keys, the first key of the series including either the least significant bit (LSB) or most significant bit (MSB) of the input data value. The CAM array is divided along columns into a similar series of non-overlapping sub-arrays corresponding to the subfields defined by the series of keys. A first CAM sub-array compares the first key with its stored rows of data bit values to generate a first match signal. The first match signal disables each row of the second CAM sub-array for which the corresponding row of the first CAM sub-array did not show a match. A second CAM sub-array then compares the second key with its enabled rows to generate a second match signal.
    Type: Grant
    Filed: October 31, 2002
    Date of Patent: October 6, 2009
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Thomas Diede, John R. Mick