Patents Assigned to NetLogic Microsystems, Inc.
  • Patent number: 7907432
    Abstract: A CAM device includes a CAM array coupled to a programmable priority encoding (PPE) logic circuit. The CAM array concurrently compares multiple input data with stored data to generate corresponding match results that are provided to the PPE logic circuit. The PPE logic circuit selectively favors the match results of a selected flow over the match results of the other flows in response to a flow select signal, which can be toggled to alternately select the match results of various flows. In this manner, the match results of the selected flow are generated and output even if the HPM index of the selected flow is of a lower priority than those of the non-selected flows, thereby ensuring an even distribution of match results reporting between different flows.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: March 15, 2011
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Chetan Deshpande, Sandeep Khanna, Varadarajan Srinivasan
  • Patent number: 7904642
    Abstract: A method of minimizing an amount of memory area required to store a plurality of rules associated with one or more access control lists (ACLs) includes selectively combining the plurality of rules into one or more groups depending upon similarities between the entries within each field and storing the groups in a database including a content addressable memory (CAM) device and a random access memory (RAM) device.
    Type: Grant
    Filed: November 5, 2007
    Date of Patent: March 8, 2011
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Pankaj Gupta, Liao Wei-Cherng
  • Patent number: 7904643
    Abstract: A content addressable memory (CAM) device, method, and method of generating entries for range matching are disclosed. A CAM device (800) according to one embodiment can include a pre-encoder (806) that encodes range bit values W into additional bits E. Additional bits E can indicate compression of range rules according to particular bit pairs. A CAM array (802) can include entries that store compressed range code values (RANGE) with corresponding additional bit values (ENC). Alternate embodiments can include pre-encoders that encode portions of range values (K1 to Ki) in a “one-hot” fashion. Corresponding CAM entries can include encoded value having sections that each represent increasingly finer divisions of a range space.
    Type: Grant
    Filed: March 26, 2010
    Date of Patent: March 8, 2011
    Assignee: Netlogic Microsystems, Inc.
    Inventor: Srinivasan Venkatachary
  • Patent number: 7893858
    Abstract: A method and apparatus for performing pipelined capacitive folding and interpolation analog-to-digital conversion. In one embodiment, the apparatus comprises a multistage pipelined analog-to-digital converter having: a distributed sample/hold and preamp, folding and interpolation unit which combines a plurality of preamplified signals using a capacitive folding and capacitive interpolation; and a decoding unit coupled to decode the output signals from the folding and interpolation unit. The distributed sample/hold and preamp drastically improves the input dynamic range and hence increases ADC over all linearity. This technique offers an inherent dynamic offset cancellation in every sample and can be implemented in submicron CMOS, using the core digital supply.
    Type: Grant
    Filed: March 5, 2009
    Date of Patent: February 22, 2011
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Pirooz Hojabri, Jack Lam
  • Patent number: 7889727
    Abstract: A content matching engine (CME) uses a content addressable memory (CAM) array that stores a plurality of strings in separate entries. The strings define one or more rules to be matched. The strings of each rule are linked, thereby providing a required order. The strings of each rule can be linked by per-entry counters associated with each string, or by a state machine. The strings in the CAM array are compared with a packet, which is shifted one symbol at a time (because the strings can start on any boundary). When the CAM detects a match, the CAM skips over the string that resulted in the match, thereby preventing erroneous matches. The CAM allows parallel matching to be performed for multiple rules. If the contents of a packet match all of the strings of a rule, in order, then the CME asserts a match/index signal that identifies the matched rule.
    Type: Grant
    Filed: February 8, 2008
    Date of Patent: February 15, 2011
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Michael J. Miller, Vladan Djakovic
  • Patent number: 7889582
    Abstract: A memory device is provided for performing writing operations on memory cells while maintaining a stability thereof. A memory array is provided including a plurality of memory cells. Additionally, segmented write bitlines are provided for performing writing operations on the memory cells while maintaining a stability thereof.
    Type: Grant
    Filed: March 12, 2008
    Date of Patent: February 15, 2011
    Assignee: NetLogic Microsystems, Inc.
    Inventor: Steven Butler
  • Patent number: 7885300
    Abstract: A method and system to drive large off-chip loads, such as, for example, laser diodes, wherein the system includes an integrated circuit coupled to an external differential diode load. Alternatively, the external diode load may be driven single-ended. The integrated circuit includes a data buffer device and a clock buffer device. The integrated circuit also includes a multiplexer device coupled to the clock buffer device configured to multiplex a data input signal and a clock input signal received at respective inputs of the integrated circuit. If the external diode is single-ended, the data input signal is transmitted to the data buffer device, which is then used solely to drive the diode load. If the diode load is differential, the data buffer device receives the data input signal. At the same time, the multiplexer device receives both the data input signal and the clock input signal and selects the data signal to drive the clock buffer device.
    Type: Grant
    Filed: March 2, 2006
    Date of Patent: February 8, 2011
    Assignee: NetLogic Microsystems, Inc
    Inventors: Stefanos Sidiropoulos, Shwetabh Verma, Shahriar Rabii
  • Patent number: 7881090
    Abstract: A read operation and a search operation are performed during the same cycle within a CAM system including a CAM array by: (1) forcing a non-matching condition to exist in the row of the CAM array selected for the read operation, (2) comparing the read data value with the search data value outside of the CAM array to determine whether a match exists, and (3) prioritizing the results of the search operation performed within the CAM array and the results of the comparison performed outside of the CAM array to provide a final search result.
    Type: Grant
    Filed: March 16, 2009
    Date of Patent: February 1, 2011
    Assignee: NetLogic Microsystems, Inc.
    Inventor: Kee Park
  • Patent number: 7881125
    Abstract: A content addressable memory (CAM) device includes a CAM array, a programmable interconnect structure, and a priority encoder. The CAM array includes a plurality of CAM rows, each row including a number of CAM cells for storing a data word and coupled to a match line that indicates a match result for the CAM row. The programmable interconnect structure is coupled to each CAM row and a plurality of CAM rows, each row including a number of CAM cells for storing a data word and coupled to a match line that indicates match results for the row. The programmable interconnect structure coupled to each CAM row, and is configured to logically connect any number N of selected CAM rows together to form a data word chain spanning N rows, regardless of whether the selected CAM rows are contiguous.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: February 1, 2011
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Maheshwaran Srinivasan, Varadarajan Srinivasan, Sandeep Khanna, Sachin Joshi, Mark Birman
  • Patent number: 7876590
    Abstract: A content addressable memory (CAM) device includes a plurality of CAM rows, a number of sequencing logic circuits, and a programmable interconnect structure. Each CAM row includes a number of CAM cells to generate a match signal on a match line and includes an enable input. Each sequencing logic circuit includes an input and an output, and is configured to count sequences of match signals from the CAM rows. The programmable interconnect structure selectively connects the match line of any CAM row to the input of any sequencing logic circuit, and selectively connects the output of any sequencing logic circuit to the enable input of any CAM row.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: January 25, 2011
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Sachin Joshi, Mark Birman, Maheshwaran Srinivasan, Sandeep Khanna, Varadarajan Srinivasan
  • Publication number: 20110013643
    Abstract: The invention relates to a crossbar switch controller including an input terminal configured to receive a set of service request signals from a set of virtual output queues each comprising a set of packets. The invention also includes a matrix circuit coupled to the input terminal and configured to represent the set of service request signals in the form of a matrix, wherein each service request signal is described by a row position M and a column position N. The invention further includes an output terminal configured to receive a portion of the set of packets during an epoch, an arbiter circuit configured to iteratively scan the matrix during the epoch and issue the set of grant signals to the virtual output queues to determine which service requests are granted, and an arbiter controller configured to initiate the arbiter circuit with an array of non-conflicting matrix elements.
    Type: Application
    Filed: September 24, 2010
    Publication date: January 20, 2011
    Applicant: NETLOGIC MICROSYSTEMS, INC.
    Inventors: Brian Hang Wai Yang, Kai-Yeung (Sunny) Siu, Mizanur M. Rahman, Wei-Han Lien, Gaurav Singh
  • Patent number: 7872890
    Abstract: A counter circuit is configured to simultaneously maintain individual character match count values for a plurality of overlapping substrings of an input string of characters that match a portion of a regular expression stored in a plurality of rows of content addressable memory (CAM) cells of a ternary CAM device. The counter circuit is selectable between a normal operational mode in which all matching portions of the input string are identified, and a minimum match length operational mode in which only matching portions of the input string that have at least a specified minimum number of characters are identified.
    Type: Grant
    Filed: August 10, 2009
    Date of Patent: January 18, 2011
    Assignee: NetLogic Microsystems, Inc.
    Inventor: Alexey Starovoytov
  • Patent number: 7868383
    Abstract: An integrated circuit (IC) device including a substrate, a plurality of device layers formed over the substrate, and a plurality of multi-level revision (MLR) structures that generate a revision code indicative of device revisions. Each MLR group structure includes a number of MLR cells and includes a parity circuit having a number of inputs coupled to the outputs of the MLR cells and having an output to generate a corresponding bit of the revision code. The MLR cells in each MLR group structure are assigned to different device layers, and each device layer is assigned to one MLR cell in each MLR group structure. Each revision code bit is controllable by any MLR cell in the corresponding MLR group structure.
    Type: Grant
    Filed: June 12, 2009
    Date of Patent: January 11, 2011
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Dimitri Argyres, Bindiganavale S. Nataraj
  • Patent number: 7864760
    Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: January 4, 2011
    Assignee: Netlogic Microsystems, Inc.
    Inventor: David T. Hass
  • Patent number: 7859876
    Abstract: A method and apparatus for a CAM with reduced cross-coupling interference have been disclosed.
    Type: Grant
    Filed: June 19, 2007
    Date of Patent: December 28, 2010
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Chuen-Der Lien, Chau-Chin Wu
  • Patent number: 7860849
    Abstract: A search tree embodying a plurality of signatures and a number of states each having a failure transition to a fail state and one or more success transitions to next states is optimized by selecting a success size parameter that indicates a maximum number of input characters to be traversed on the success transitions and compressing the search tree to create a compressed search tree characterized by the selected success size parameter.
    Type: Grant
    Filed: March 21, 2007
    Date of Patent: December 28, 2010
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Srinivasan Venkatachary, Pankaj Gupta
  • Patent number: 7856524
    Abstract: An apparatus and method of transposing one or more bits in input data relative to other bits of the input data to form a comparand for searching in a content addressable memory. The comparand may have one or more bits rearranged from their order appearing in the input data such that one or more bits from a first segment of the input data are replaced with, or substituted by, one or more bits from a second segment of the input data.
    Type: Grant
    Filed: July 7, 2008
    Date of Patent: December 21, 2010
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Dimitri C. Argyres, Varadarajan Srinivasan
  • Patent number: 7856570
    Abstract: A method and system for shaping an electronic pulse with a two-pulse response. An input node receives an initial electronic pulse and splits the electronic pulse into a first path and a second path. An output node combines together the first path and the second path into an output path, and transmits a shaped electronic pulse, matched to an output impedance. An Ethernet chip generates two pulses and transmits the pulses along a first path and a second path respectively. A power combiner/splitter combines together the pulses along the first path and the second path into an output path, and transmits a shaped electronic pulse, matched to an output impedance.
    Type: Grant
    Filed: August 24, 2007
    Date of Patent: December 21, 2010
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Haw-Jyh Liaw, Shwetabh Verma
  • Publication number: 20100318703
    Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. The data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. In one aspect of an embodiment of the invention, the messaging network connects to a high-bandwidth star-topology serial bus such as a PCI express (PCIe) interface capable of supporting multiple high-bandwidth PCIe lanes. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.
    Type: Application
    Filed: June 14, 2010
    Publication date: December 16, 2010
    Applicant: NETLOGIC MICROSYSTEMS, INC.
    Inventors: Julianne Jiang Zhu, David T. Hass
  • Publication number: 20100318763
    Abstract: Extended translation look-aside buffers (eTLB) for converting virtual addresses into physical addresses are presented, the eTLB including, a physical memory address storage having a number of physical addresses, a virtual memory address storage configured to store a number of virtual memory addresses corresponding with the physical addresses, the virtual memory address storage including, a set associative memory structure (SAM), and a content addressable memory (CAM) structure; and comparison circuitry for determining whether a requested address is present in the virtual memory address storage, wherein the eTLB is configured to receive an index register for identifying the SAM structure and the CAM structure, and wherein the eTLB is configured to receive an entry register for providing a virtual page number corresponding with the plurality of virtual memory addresses.
    Type: Application
    Filed: August 18, 2010
    Publication date: December 16, 2010
    Applicant: NETLOGIC MICROSYSTEMS, INC.
    Inventors: Gaurav SINGH, Dave HASS, Daniel CHEN