Patents Assigned to NetLogic Microsystems, Inc.
  • Content addressable memory having selectively interconnected rows of counter circuits
    Patent number: 7876590
    Abstract: A content addressable memory (CAM) device includes a plurality of CAM rows, a number of sequencing logic circuits, and a programmable interconnect structure. Each CAM row includes a number of CAM cells to generate a match signal on a match line and includes an enable input. Each sequencing logic circuit includes an input and an output, and is configured to count sequences of match signals from the CAM rows. The programmable interconnect structure selectively connects the match line of any CAM row to the input of any sequencing logic circuit, and selectively connects the output of any sequencing logic circuit to the enable input of any CAM row.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: January 25, 2011
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Sachin Joshi, Mark Birman, Maheshwaran Srinivasan, Sandeep Khanna, Varadarajan Srinivasan
  • Counter circuit for regular expression search engines
    Patent number: 7872890
    Abstract: A counter circuit is configured to simultaneously maintain individual character match count values for a plurality of overlapping substrings of an input string of characters that match a portion of a regular expression stored in a plurality of rows of content addressable memory (CAM) cells of a ternary CAM device. The counter circuit is selectable between a normal operational mode in which all matching portions of the input string are identified, and a minimum match length operational mode in which only matching portions of the input string that have at least a specified minimum number of characters are identified.
    Type: Grant
    Filed: August 10, 2009
    Date of Patent: January 18, 2011
    Assignee: NetLogic Microsystems, Inc.
    Inventor: Alexey Starovoytov
  • Configurable non-volatile logic structure for characterizing an integrated circuit device
    Patent number: 7868383
    Abstract: An integrated circuit (IC) device including a substrate, a plurality of device layers formed over the substrate, and a plurality of multi-level revision (MLR) structures that generate a revision code indicative of device revisions. Each MLR group structure includes a number of MLR cells and includes a parity circuit having a number of inputs coupled to the outputs of the MLR cells and having an output to generate a corresponding bit of the revision code. The MLR cells in each MLR group structure are assigned to different device layers, and each device layer is assigned to one MLR cell in each MLR group structure. Each revision code bit is controllable by any MLR cell in the corresponding MLR group structure.
    Type: Grant
    Filed: June 12, 2009
    Date of Patent: January 11, 2011
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Dimitri Argyres, Bindiganavale S. Nataraj
  • Advanced processor with mechanism for enforcing ordering between information sent on two independent networks
    Patent number: 7864760
    Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: January 4, 2011
    Assignee: Netlogic Microsystems, Inc.
    Inventor: David T. Hass
  • Optimizing search trees by increasing success size parameter
    Patent number: 7860849
    Abstract: A search tree embodying a plurality of signatures and a number of states each having a failure transition to a fail state and one or more success transitions to next states is optimized by selecting a success size parameter that indicates a maximum number of input characters to be traversed on the success transitions and compressing the search tree to create a compressed search tree characterized by the selected success size parameter.
    Type: Grant
    Filed: March 21, 2007
    Date of Patent: December 28, 2010
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Srinivasan Venkatachary, Pankaj Gupta
  • Method and apparatus for CAM with reduced cross-coupling interference
    Patent number: 7859876
    Abstract: A method and apparatus for a CAM with reduced cross-coupling interference have been disclosed.
    Type: Grant
    Filed: June 19, 2007
    Date of Patent: December 28, 2010
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Chuen-Der Lien, Chau-Chin Wu
  • Transposing of bits in input data to form a comparand within a content addressable memory
    Patent number: 7856524
    Abstract: An apparatus and method of transposing one or more bits in input data relative to other bits of the input data to form a comparand for searching in a content addressable memory. The comparand may have one or more bits rearranged from their order appearing in the input data such that one or more bits from a first segment of the input data are replaced with, or substituted by, one or more bits from a second segment of the input data.
    Type: Grant
    Filed: July 7, 2008
    Date of Patent: December 21, 2010
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Dimitri C. Argyres, Varadarajan Srinivasan
  • Method and apparatus for shaping electronic pulses
    Patent number: 7856570
    Abstract: A method and system for shaping an electronic pulse with a two-pulse response. An input node receives an initial electronic pulse and splits the electronic pulse into a first path and a second path. An output node combines together the first path and the second path into an output path, and transmits a shaped electronic pulse, matched to an output impedance. An Ethernet chip generates two pulses and transmits the pulses along a first path and a second path respectively. A power combiner/splitter combines together the pulses along the first path and the second path into an output path, and transmits a shaped electronic pulse, matched to an output impedance.
    Type: Grant
    Filed: August 24, 2007
    Date of Patent: December 21, 2010
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Haw-Jyh Liaw, Shwetabh Verma
  • Match line precharge circuits and methods for content addressable memory (CAM) device
    Patent number: 7852652
    Abstract: A content addressable memory (CAM) device can include a number of match lines, each coupled to a plurality of CAM cells. The CAM device also includes one or more one precharge circuits. Such a precharge circuit can have a first precharge path that couples a match line to a precharge voltage node in response the activation of a first control signal, and a second precharge path that couples the match line to the precharge voltage node in response to the activation of a second control signal. Prior to a compare operation leakage current through the CAM cells can prevented by disabling the precharge paths and isolating the CAM cells from a reference voltage (e.g., ground). The second control signal can be activated after the first control signal in a compare operation.
    Type: Grant
    Filed: June 27, 2008
    Date of Patent: December 14, 2010
    Assignee: Netlogic Microsystems, Inc.
    Inventor: Martin Fabry
  • Dynamically partitioned CAM array
    Patent number: 7848129
    Abstract: A content addressable memory (CAM) device includes a comparand register, a CAM array, and partition logic. The comparand register has inputs to receive a search key, and outputs coupled to the CAM array, which includes a plurality of individually selectable sub-arrays. Each sub-array includes a number of rows of CAM cells and a control circuit, wherein each row of CAM cells is coupled to a match line, and wherein the control circuit has an input to receive a corresponding sub-array enable signal. The partition logic has an input to receive a partition select signal, and is configured to generate the sub-array enable signals in response to the partition select signal. The control circuits selectively propagate the search key through the sub-arrays in response to the sub-array enable signals.
    Type: Grant
    Filed: November 20, 2008
    Date of Patent: December 7, 2010
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Chetan Deshpande, Vinay Iyengar, Bindiganavale S. Nataraj
  • Combined processor access and built in self test in hierarchical memory systems
    Patent number: 7844867
    Abstract: A hierarchical memory includes a plurality of memory blocks, a common access bus coupled to the plurality of memory blocks, and a host bus interface coupled to the common access bus and configured to provide communication between an external host and the plurality of memory blocks over the common access bus. The memory further includes a Built-In Self Test (BIST) module coupled to the common access bus and configured to communicate with the plurality of memory blocks over the common access bus, and a test access interface coupled to the BIST main module and configured to receive test instructions and test data, to provide the test data to the BIST main module, and to configure the BIST main module in response to the test instructions. BIST operations are carried out in the memory blocks in response to BIST control signals and test data transmitted by the BIST module over the common access bus.
    Type: Grant
    Filed: December 19, 2007
    Date of Patent: November 30, 2010
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Sudhakar Reddy, Gary Depelteau
  • Analog echo canceller with filter banks
    Patent number: 7843859
    Abstract: A method and system are described for canceling an echo signal in analog domain with adaptive filters working in digital domain. In one embodiment, a system includes an analog-to-digital converter (ADC) sampling at two different phases to generate a first error signal and a second error signal having different phases. The ADC operates at a frequency significantly lower than the frequency at which the individual filters run. The first adaptive filter unit and a second adaptive filter unit are independently trained with the first and second error signals, respectively. The first and second adaptive filter units generate echo estimate signals used to cancel the echo signal.
    Type: Grant
    Filed: September 23, 2008
    Date of Patent: November 30, 2010
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Roubik Gregorian, Gaurav Malhotra
  • System and method for performing a register renaming operation utilizing hardware which is capable of operating in at least two modes utilizing registers of multiple widths
    Patent number: 7840783
    Abstract: A system, method, and computer program product are provided for performing a register renaming operation utilizing hardware which operates in at least two modes. In operation, hardware is operated in at least two modes including a first mode for operating the hardware using a logical register of a first bit width and a second mode for operating the hardware using a logical register of a second bit width. The first bit width is twice a width of the second bit width. Additionally, a register renaming operation is performed, including renaming at least one logical register to at least one physical register of the first bit width, utilizing the hardware.
    Type: Grant
    Filed: September 10, 2007
    Date of Patent: November 23, 2010
    Assignee: Netlogic Microsystems, Inc.
    Inventors: Gaurav Singh, Srivatsan Srinivasan, Ricardo Ramirez, Wei-Hsiang Chen, Hai Ngoc Nguyen
  • Method and apparatus for overlaying flat and/or tree based data sets onto content addressable memory (CAM) device
    Patent number: 7836246
    Abstract: A content addressable memory device (100) and method can have CAM blocks (102-0 to 102-29) organized in block sections (104-0 to 104-6). In an overlay mode of operation, an overlay engine (106) can access an algorithmic search (SPEAR) CAM (102-28 and 102-29) to generate overlay data set search keys (keyFIB<0> and <1>). Multiple data sets (e.g., FIB0, FIB1, ACL0) can be accommodated on the same CAM device by search key multiplexers (108-0 to 108-6) that selectively apply any of a number of data set search keys (keyACL<0>, keyFIB<0> and keyFIB<1>).
    Type: Grant
    Filed: June 23, 2008
    Date of Patent: November 16, 2010
    Assignee: Netlogic Microsystems, Inc.
    Inventors: Mark Birman, Ajay Srikrishna, Srinivasan Venkatachary
  • Output queued switch with a parallel shared memory, and method of operating same
    Patent number: 7835334
    Abstract: A network switch includes an input layer to receive a data stream with a set of cells. Each cell includes data and a header to designate a destination device. The input layer includes a set of input layer circuits. A selected input layer circuit of the set of input layer circuits receives the data stream. The selected input layer circuit includes a set of queues corresponding to a set of destination devices. The selected input layer circuit is configured to assign a selected cell from the data stream to a selected queue of the set of queues. The selected queue corresponds to a selected destination device specified by the header of the selected cell. An intermediate layer includes a set of intermediate layer circuits, each intermediate layer circuit has a set of buffers corresponding to the set of destination devices.
    Type: Grant
    Filed: August 26, 2008
    Date of Patent: November 16, 2010
    Assignee: Netlogic Microsystems, Inc.
    Inventors: Kai-Yeung (Sunny) Siu, Brain Hang Wai Yang, Mizanur M. Rahman
  • Integrated search engine devices having a plurality of multi-way trees of search keys therein that share a common root node
    Patent number: 7831626
    Abstract: An integrated search engine includes a hierarchical memory configured to support a plurality of multi-way trees of search keys. These multi-way trees, which share a common root node, support respective databases of search keys. The child pointers associated with search keys within the common root node may be allocated at a single key level of granularity, which means that each search key within the common root node may be associated with a pair of child pointers when each search key within the common root node is associated with a different multi-way tree of search keys.
    Type: Grant
    Filed: September 20, 2007
    Date of Patent: November 9, 2010
    Assignee: NetLogic Microsystems, Inc.
    Inventor: Gary Depelteau
  • Low power content addressable memory
    Patent number: 7830691
    Abstract: A low power content addressable memory (CAM) device. The CAM device receives an N-bit comparand value and, in response, activates less than N compare lines within the CAM device to compare each of the N bits of the comparand value with contents of CAM cells coupled to the N compare lines.
    Type: Grant
    Filed: July 17, 2008
    Date of Patent: November 9, 2010
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Varadarajan Srinivasan, Sandeep Khanna, Bindiganavale S. Nataraj
  • Advanced telecommunications router and crossbar switch controller
    Patent number: 7826477
    Abstract: The invention relates to a crossbar switch controller including an input terminal configured to receive a set of service request signals from a set of virtual output queues each comprising a set of packets. The invention also includes a matrix circuit coupled to the input terminal and configured to represent the set of service request signals in the form of a matrix, wherein each service request signal is described by a row position M and a column position N. The invention further includes an output terminal configured to receive a portion of the set of packets during an epoch, an arbiter circuit configured to iteratively scan the matrix during the epoch and issue the set of grant signals to the virtual output queues to determine which service requests are granted, and an arbiter controller configured to initiate the arbiter circuit with an array of non-conflicting matrix elements.
    Type: Grant
    Filed: July 9, 2008
    Date of Patent: November 2, 2010
    Assignee: Netlogic Microsystems, Inc.
    Inventors: Brian Hang Wal Yang, Kai-Yeung (Sunny) Siu, Mizanur M. Rahman, Wei-Han Lien, Gaurav Singh
  • Content addresable memory having selectively interconnected counter circuits
    Patent number: 7826242
    Abstract: A content addressable memory (CAM) device includes a plurality of CAM rows, a number of sequencing logic circuits, and a programmable interconnect structure. Each CAM row includes a number of CAM cells to generate a match signal on a match line and includes an enable input. Each sequencing logic circuit includes an input and an output, and is configured to count sequences of match signals from the CAM rows. The programmable interconnect structure selectively connects the match line of any CAM row to the input of any sequencing logic circuit, and selectively connects the output of any sequencing logic circuit to the enable input of any CAM row.
    Type: Grant
    Filed: November 16, 2009
    Date of Patent: November 2, 2010
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Sachin Joshi, Mark Birman, Maheshwaran Srinivasan, Sandeep Khanna, Varadarajan Srinivasan
  • Content addresable memory having programmable interconnect structure
    Patent number: 7821844
    Abstract: A content addressable memory (CAM) device includes a CAM array, a programmable interconnect structure, and a priority encoder. The CAM array includes a plurality of CAM rows, each row including a number of CAM cells for storing a data word and coupled to a match line that indicates a match result for the CAM row. The programmable interconnect structure is coupled to each CAM row and a plurality of CAM rows, each row including a number of CAM cells for storing a data word and coupled to a match line that indicates match results for the row. The programmable interconnect structure coupled to each CAM row, and is configured to logically connect any number N of selected CAM rows together to form a data word chain spanning N rows, regardless of whether the selected CAM rows are contiguous.
    Type: Grant
    Filed: November 12, 2009
    Date of Patent: October 26, 2010
    Assignee: NetLogic Microsystems, Inc
    Inventors: Maheshwaran Srinivasan, Varadarajan Srinivasan, Sandeep Khanna, Sachin Joshi, Mark Birman