Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

Abstract: A content addressable memory (CAM) cell includes a first storage element for storing a data value, a second storage element for storing the data value, and a compare circuit having first inputs to receive from the first storage element a first complementary data signal indicative of the data value, second inputs to receive from the second storage element a second complementary data signal indicative of the data value, third inputs to receive comparand data, and an output coupled to a match line. The CAM cell allows for simultaneous read and compare operations, as well as simultaneous refresh and compare operations.

Abstract: A method may include selectively coupling a result line to a reference node in response to a compare data value being applied to a plurality of compare cell circuits; precharging the result line to the precharge potential by enabling a first precharge path while the compare data value is being applied; and after precharging the result line by enabling the first precharge path, disabling the first precharge path to place it in a high impedance state.

Abstract: A method of placing a content addressable memory (CAM) into a low current state is disclosed. The CAM can include at least one storage location that does not store valid data for a compare operation and includes a plurality of CAM cells, each CAM cell having at least two data controllable impedance paths arranged in parallel with one another. The method can include configuring the majority of the CAM cells to store data values that maintain the corresponding at least two data controllable impedance paths in high impedance states.

Abstract: An integrated search engine device evaluates span prefix masks for keys residing at leaf parent levels of a search tree to identify a longest prefix match to an applied search key. This longest prefix match resides at a leaf node of the search tree that is outside a search path of the search tree for the applied search key. The search engine device is also configured to read a bitmap associated with the leaf node to identify a pointer to associated data for the longest prefix match. The pointer has a value that is based on a position of a set bit within the bitmap that corresponds to a set bit within the span prefix mask that signifies the longest prefix match.

Abstract: Extended translation look-aside buffers (eTLB) for converting virtual addresses into physical addresses are presented, the eTLB including, a physical memory address storage having a number of physical addresses, a virtual memory address storage configured to store a number of virtual memory addresses corresponding with the physical addresses, the virtual memory address storage including, a set associative memory structure (SAM), and a content addressable memory (CAM) structure; and comparison circuitry for determining whether a requested address is present in the virtual memory address storage, wherein the eTLB is configured to receive an index register for identifying the SAM structure and the CAM structure, and wherein the eTLB is configured to receive an entry register for providing a virtual page number corresponding with the plurality of virtual memory addresses.

Abstract: A method, apparatus, and storage medium product are provided for forming a forwarding database, and for using the formed database to more efficiently and quickly route packets of data across a computer network. The forwarding database is arranged into multiple sub-databases. Each sub-database is pointed to by a pointer within a pointer table. When performing a longest-match search of incoming addresses, a longest prefix matching algorithm can be used to find the longest match among specialized “spear prefixes” stored in the pointer table. After the longest spear prefixes are found, the pointer table will direct the next search within a sub-database pointed to by that spear prefix. Another longest-match search can be performed for database prefixes (or simply “prefixes”) within the sub-database selected by the pointer. Only the sub-database of interest will, therefore, be searched and all other sub-databases are not accessed.

Abstract: A method and an apparatus for slicing an analog signal using an analog encoder.

Abstract: An advanced processor comprises a plurality of multithreaded processor cores configured to support a plurality of software generated read or write instructions for interfacing with a star topology serial bus interface. The multiple-core processor has at least one of an internal fast messaging network or an interface switch interconnect configured to link the processor cores together such that each processor core has a data pathway to each of the other processor cores without going through memory. The fast messaging network or interface switch is also configured to be operably coupled to the star topology serial bus interface. In one aspect of an embodiment of the invention, the fast messaging network connects to a high-bandwidth star-topology serial bus such as a PCI express (PCIe) interface capable of supporting multiple high-bandwidth PCIe lanes.

Abstract: A method and apparatus for performing pipelined capacitive folding and interpolation analog-to-digital conversion. In one embodiment, the apparatus comprises a multistage pipelined analog-to-digital converter having: a distributed sample/hold and preamp, folding and interpolation unit which combines a plurality of preamplified signals using a capacitive folding and capacitive interpolation; and a decoding unit coupled to decode the output signals from the folding and interpolation unit. The distributed sample/hold and preamp drastically improves the input dynamic range and hence increases ADC over all linearity. This technique offers an inherent dynamic offset cancellation in every sample and can be implemented in submicron CMOS, using the core digital supply.

Abstract: An encoding scheme is disclosed that allows a CAM device to selectively store, within each cell of a row of the CAM device, either a single bit of a binary value or two bits of an encoded data word encoded from the binary value. By storing two bits of the encoded data word in each CAM cell, data may be stored more efficiently and CAM systems may consume less power. The encoded data words can be balanced data words that have equal number of logic high and logic low values.

Abstract: A method and apparatus for joint training of an analog equalizer (AEQ) and an analog echo canceller (AEC) is described. In one embodiment, which both the AEQ and AEC process an input analog signal in the analog domain. In one embodiment, the method includes joint training the AEQ and the AEC using independent analog error signals.

Abstract: A method and apparatus are disclosed for improving reliability in a memory circuit. The method includes coupling a pull-down element to a word line, the pull-down element coupled distal to a word line driver. The method further includes, when the word line exhibits a defect causing a first portion of the word line to be electrically isolated from a second portion of the word line, holding the second portion of the word line at a logically low value using the pull-down element. A memory device is disclosed that includes a word line coupled to a memory cell, a word line driver coupled to one end of the word line, and a pull-down element coupled proximate the other end of the word line. The pull-down element is operable, when the word line exhibits a defect causing a first portion of the word line to be electrically isolated from a second portion of the word line, to hold the second portion of the word line at a logical low value.

Abstract: A method and apparatus are disclosed for determining the lengths of one or more substrings of an input string that matches a regular expression (regex) The input string is searched for the regex using an non-deterministic finite automaton (NFA), and upon detecting a match state a selected portion of the input string is marked as a match string. The NFA is inverted to create a reverse NFA that embodies the inverse of the regex. For some embodiments, the reverse NFA is created by inverting the NFA such that the match state of the NFA becomes the initial state of the reverse NFA, the initial state of the NFA becomes the match state of the reverse NFA, and the goto transitions of the NFA are inverted to form corresponding goto transitions in the reverse NFA. The match string is reversed and searched for the inverted regex using the reverse NFA, and a counter is incremented for each character processed during the reverse search operation.

Abstract: A method of signal processing comprises receiving an unknown input signal that includes a distorted component and an undistorted component, the unknown input signal having a sampling rate of R; and performing self-linearization based at least in part on the unknown signal to obtain an output signal that is substantially undistorted, including by generating a replica distortion signal that is substantially similar to the distorted component, the generation being based at least in part on a target component having a sampling rate of R/L, L being an integer greater than 1.

Abstract: A method and an apparatus for slicing a multilevel analog signal using a two-level slicer having one threshold level to generate an analog error signal. The method may be performed by delaying a received multilevel analog signal in a plurality of serial analog stages (n), further delaying a multilevel analog signal tapped from stage n, combining the further delayed signal from stage n with an analog error signal e(t) to provide an analog weighting function Wn, wherein the combining of the delayed signal from stage n with Wn results in a plurality of signals XnWn, summing the plurality of signals XnWn, slicing a multilevel analog signal resulting from the summing of the plurality of signals XnWn using one threshold level to generate the analog error signal e(t), and combining the delayed signal from stage n with Wn.

Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. The data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. In one aspect of an embodiment of the invention, the messaging network connects to a high-bandwidth star-topology serial bus such as a PCI express (PCIe) interface capable of supporting multiple high-bandwidth PCIe lanes. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

Abstract: A method of signal processing includes receiving a distorted signal comprising a distorted component and an undistorted component, the distorted component being at least in part attributed to an exogenous signal, and performing linearization, based at least in part on the distorted signal and information associated with the exogenous signal, to obtain a corrected signal that is substantially similar to the undistorted component. An adaptive distortion reduction system includes an input interface configured to receive a distorted signal comprising a distorted component and an undistorted component, the distorted component being at least in part attributed to an exogenous signal; and an adaptive distortion reduction module coupled to the input interface, configured to perform linearization based at least in part on the distorted signal and information associated with the exogenous signal, to obtain a corrected signal that is substantially similar to the undistorted component.

Abstract: The power consumption of a search engine such as a CAM device is dynamically adjusted to prevent performance degradation and/or damage resulting from overheating. For some embodiments, the CAM device is continuously sampled to generate sampling signals indicating the number of active states and number of compare operations performed during each sampling period. The sampling signals are accumulated to generate an estimated device power profile, which is compared with reference values corresponding to predetermined power levels to generate a dynamic power control signal indicating predicted increases in the device's operating temperature resulting from its power consumption. The dynamic power control signal is then used to selectively reduce the input data rate of the CAM device, thereby reducing power consumption and allowing the device to cool.

Abstract: Present embodiments describe a CAM device having a segmented CAM array. Each segment of the CAM array, or cell blocks, includes one or more rows of CAM cells. One or more of the cell blocks in the CAM array are selectively enabled during a search operation based on a detected matching condition of another cell block. By selectively enabling cell blocks during search operations only when needed, energy consumption is reduced. Selectively enabling a cell block includes selectively pre-charging match lines to the cell block, selectively enabling word lines to the cell block, and selectively enabling comparand line to the cell block. In accordance with certain embodiments, the CAM device is configurable to perform search operations in a pipelined manner. Accordingly, the CAM device is capable of performing multiple search operations simultaneously.