Patents Assigned to NetLogic Microsystems, Inc.
  • Content addressable memory device capable of parallel state information transfers
    Patent number: 8023300
    Abstract: Present embodiments allow a search engine to quickly save and restore state information to and from an external state memory when switching between multiple data flows by transferring the state information between the search engine and the external state memory in a parallel manner. More specifically, for CAM-based search engines configured according to present embodiments, the CAM array includes state information gating circuits that selectively allow state information stored in the CAM array's match latches to be transposed onto the array's bit lines and then read from the array using the array's sense amplifiers.
    Type: Grant
    Filed: June 18, 2010
    Date of Patent: September 20, 2011
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Varadarajan Srinivasan, Chetan Deshpande, Maheshwaran Srinivasan, Sandeep Khanna, Venkat Rajendher Reddy Gaddam
  • Encoding data for storage in a content addressable memory
    Patent number: 8023298
    Abstract: Approaches for an improved encoding scheme that allows a CAM device to selectively store, within each cell of a row of the CAM device, either a single bit of a binary value or two bits of an encoded data word encoded from the binary value. By storing two bits of the encoded data word in each CAM cell, data may be stored more efficiently and CAM systems may consume less power as compared to traditional binary CAMS when performing certain types of operations, such as exact matching and longest prefix matching. Encoded data words may be, but need not be, balanced data words which have equal number of logic high and logic low values.
    Type: Grant
    Filed: February 19, 2010
    Date of Patent: September 20, 2011
    Assignee: NetLogic Microsystems, Inc.
    Inventor: Kee Park
  • Content addressable memory device having spin torque transfer memory cells
    Patent number: 8023299
    Abstract: A CAM device includes an array of CAM cells each having a spin torque transfer (STT) storage cell to store a data bit. Each STT storage cell includes a first magnetic tunnel junction (MTJ) element coupled between a first input node and an output node of the CAM cell, a second MTJ element coupled between a second input node and the output node of the CAM cell, and a first match transistor coupled between the match line and ground potential and having a gate coupled to the output node. The logic state of the data bit is represented by the relative resistances of the first and second MTJ elements.
    Type: Grant
    Filed: March 23, 2010
    Date of Patent: September 20, 2011
    Assignee: NetLogic Microsystems, Inc.
    Inventor: Nilesh A. Gharia
  • Content addressable memory device having state information processing circuitry
    Patent number: 8023301
    Abstract: Present embodiments allow a search engine to quickly save and restore state information to and from an external state memory when switching between multiple data flows by transferring the state information between the search engine and the external state memory in a parallel manner. More specifically, for CAM-based search engines configured according to present embodiments, the CAM array includes state information gating circuits that selectively allow state information stored in the CAM array's match latches to be transposed onto the array's bit lines and then read from the array using the array's sense amplifiers.
    Type: Grant
    Filed: October 6, 2010
    Date of Patent: September 20, 2011
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Varadarajan Srinivasan, Maheshwaran Srinivasan, Chetan Deshpande, Sandeep Khanna, Venkat Rajendher Reddy Gaddam
  • Ternary content addressable memory (TCAM) cells with low signal line numbers
    Patent number: 8018751
    Abstract: A ternary content addressable memory (TCAM) cell circuit formed in a TCAM memory cell array having cells arranged in rows and columns can include a first storage circuit with first and second data path, a second storage circuit with a third and fourth data path, and a compare circuit. No more than four conductive lines in a column wise direction have a direct electrical connection to the TCAM cell. Such conductive lines can include a first bit line coupled to the first data path and the third data path and a second bit line coupled to the second data path and the fourth data path.
    Type: Grant
    Filed: July 16, 2009
    Date of Patent: September 13, 2011
    Assignee: Netlogic Microsystems, Inc.
    Inventors: Dinesh Maheshwari, Andrew Wright, Bin Jiang, Bartosz Banachowicz
  • Advanced processor with mechanism for packet distribution at high line rate
    Patent number: 8015567
    Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: September 6, 2011
    Assignee: NetLogic Microsystems, Inc.
    Inventor: David T. Hass
  • Low power serial link
    Patent number: 8000412
    Abstract: The present invention relates to a low power serial link employing differential return-to-zero signaling. A receiver circuit consistent with some embodiments includes an input circuit for receiving differential serial data signals that form a differential return-to-zero signaling and a clock recovery circuit. The clock recovery circuit is coupled to the input circuit and includes a logic gate configured to generate a clock signal by using said differential serial data signals.
    Type: Grant
    Filed: May 31, 2007
    Date of Patent: August 16, 2011
    Assignee: NetLogic Microsystems, Inc.
    Inventor: Marc Loinaz
  • System and method for offloading packet protocol encapsulation from software
    Patent number: 7995596
    Abstract: A method is provided for offloading packet protocol encapsulation from software. In operation, pointer information is received. Furthermore, packet protocol encapsulation is offloaded from software by assembling packets in hardware, using the pointer information.
    Type: Grant
    Filed: May 13, 2008
    Date of Patent: August 9, 2011
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Kaushik Kuila, David T. Hass, Ahmed Shahid
  • Advanced processor translation lookaside buffer management in a multithreaded system
    Patent number: 7991977
    Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: August 2, 2011
    Assignee: NetLogic Microsystems, Inc.
    Inventors: David T. Hass, Basab Mukherjee
  • Integrated search engine devices having pipelined node maintenance sub-engines therein that support database flush operations
    Patent number: 7987205
    Abstract: An integrated search engine device contains a pipelined arrangement of a plurality of search and tree maintenance sub-engines therein. This pipelined arrangement of sub-engines includes a hierarchical memory, which is configured to store a plurality of databases of search prefixes. These databases are arranged as a corresponding plurality of multi-way trees that span multiple levels of the hierarchical memory. The plurality of search and tree maintenance sub-engines are configured to respond to a database flush command by redesignating active nodes of a selected database within the hierarchical memory as free nodes using downstream and upstream communications between the plurality of search and tree maintenance sub-engines.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: July 26, 2011
    Assignee: NetLogic Microsystems, Inc.
    Inventor: Gary Depelteau
  • Advanced processor scheduling in a multithreaded system
    Patent number: 7984268
    Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.
    Type: Grant
    Filed: July 23, 2004
    Date of Patent: July 19, 2011
    Assignee: NetLogic Microsystems, Inc.
    Inventors: David T. Hass, Abbas Rashid
  • Method and apparatus for a mesochronous transmission system
    Patent number: 7978802
    Abstract: A method and apparatus for a multiple lane transmission system that provides both a low latency mode of operation, while at the same time, provides reduced lane-lane skew. The overall transmission system operates as a mesochronous system, whereby each clock domain of the transmission system is synchronized to the leaf nodes of a global clock tree. A phase aligner is then used to align the phase of both the bit and byte clocks of each transmission lane to the clock signal generated at the leaf nodes of the global clock tree.
    Type: Grant
    Filed: October 12, 2007
    Date of Patent: July 12, 2011
    Assignees: Xilinx, Inc., NetLogic Microsystems, Inc.
    Inventors: Prasun K. Raha, Donald Stark, Dean Liu, Pak Shing Chau
  • Packet matching method and system
    Patent number: 7978709
    Abstract: A method of constructing a hierarchical database from an initial plurality of rules. A first rule of the initial plurality of rules is added to: a first sub-database if a first bit of the rule is a logic ‘0’ value; a second sub-database if the first bit is a logic ‘1’ value; or a third sub-database if the first bit is in a masked state, ‘X’, indicating that the first bit may be either a logic ‘1’ or a logic ‘0’ value.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: July 12, 2011
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Srinivasan Venkatachary, Pankaj Gupta
  • Multiple string searching using ternary content addressable memory
    Patent number: 7969758
    Abstract: Disclosed herein is a method and apparatus for multiple string searching using a ternary content addressable memory. The method includes receiving a text string having a plurality of characters and performing an unanchored search of a database of stored patterns matching one or more characters of the text string using a state machine, wherein the state machine comprises a ternary content addressable memory (CAM) and wherein the performing comprises comparing a state and one of the plurality of characters with contents of a state field and a character field, respectively, stored in the ternary CAM. In the method and apparatus described herein, one or more of the following search features may be supported: exact string matching, inexact string matching, single character wildcard matching, multiple character wildcard matching, case insensitive matching, parallel matching and rollback.
    Type: Grant
    Filed: September 16, 2008
    Date of Patent: June 28, 2011
    Assignee: NetLogic Microsystems, Inc.
    Inventor: Sunder Rathnavelu Raj
  • Advanced processor with mechanism for enforcing ordering between information sent on two independent networks
    Patent number: 7961723
    Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: June 14, 2011
    Assignee: NetLogic Microsystems, Inc.
    Inventor: David T. Hass
  • Integrated search engine devices that support database key dumping and methods of operating same
    Patent number: 7953721
    Abstract: Methods of operating a search engine device include repeatedly reading next keys (and associated handles) from a database within the search engine device in order to identify and transfer some or possibly all of the contents of the database to another device (e.g., command host) requesting the database contents. An operation to read a next key includes: (i) searching a pipelined database within the search engine device with a first key to identify at least one key therein that is greater than the first key and then (ii) executing a next key fetch operation in the pipelined database to identify the next key from the at least one key. The next key and a handle associated with the next key are then retrieved from the search engine device (e.g., transferred to a command host).
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: May 31, 2011
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Gary Depelteau, David Walter Carr
  • Integrated circuit device with electronically accessible device identifier
    Patent number: 7943400
    Abstract: An semiconductor device having a plurality of fabrication layers. A first region of a first fabrication layer of the semiconductor device is revised. To signal the revision, a connectivity structure in a second region of the first fabrication layer is omitted to interrupt an otherwise continuous signal path that extends through a plurality of interconnection layers of the semiconductor device.
    Type: Grant
    Filed: May 7, 2007
    Date of Patent: May 17, 2011
    Assignee: NetLogic Microsystems, Inc.
    Inventor: Bindiganavale S. Nataraj
  • Mechanism for managing access to resources in a heterogeneous data redirection device
    Patent number: 7944829
    Abstract: A system and method for policing of access to resources in a heterogeneous data redirection device is disclosed. The invention utilizes Random Early Detection to determine whether or not a given packet should be dropped or accepted into the resource. The invention uses a combination of different metrics each of which utilizes a different version of RED. Schemes can include a Per-Flow Weighted RED metric, a Global RED metric and a Fair Share Pool metric, where shared resource allocation is dependent dynamically upon the number of users at the time a packet requests access. These metrics can be combined in variety of ways to yield a final drop or accept decision for an incoming packet so that it does not access resources.
    Type: Grant
    Filed: March 28, 2005
    Date of Patent: May 17, 2011
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Paolo Narvaez, Murat Bog
  • Ternary content addressable memory having reduced leakage effects
    Patent number: 7944724
    Abstract: A column of ternary content addressable memory (TCAM) cells includes a bit line pair that is twisted at a location at or near the center of the column. Data is written to (and read from) TCAM cells located above the twist location with a first bit line polarity. Data is written to (and read from) TCAM cells located below the twist location with a second bit line polarity, opposite the first bit line polarity. As a result, read leakage currents introduced by TCAM cells storing ‘Don't Care’ values are reduced.
    Type: Grant
    Filed: April 28, 2009
    Date of Patent: May 17, 2011
    Assignee: NetLogic Microsystems, Inc.
    Inventor: Scott Chu
  • Programmable address space built-in self test (BIST) device and method for fault detection
    Patent number: 7945823
    Abstract: A built-in self-test (BIST) circuit for testing addressable locations can include a BIST generator (202) that can generate test addresses for testing each addressable location. Defective addresses can be stored in a fault address store (216). An address range selector circuit (230) can limit the range of addresses generated by an address generator (234). Once defective addresses for a first range have been detected, an address range selector circuit (230) can test another range. An entire address range can thus be tested regardless of the depth of a fault address store (216).
    Type: Grant
    Filed: March 2, 2007
    Date of Patent: May 17, 2011
    Assignee: Netlogic Microsystems, Inc.
    Inventors: Ramesha Doddamane, Eswar Vadlamani, Gopalakrishnan Perur Krishnan, Tarjinder Singh