Patents Assigned to NetLogic Microsystems, Inc.
  • Advanced processor translation lookaside buffer management in a multithreaded system
    Patent number: 7991977
    Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: August 2, 2011
    Assignee: NetLogic Microsystems, Inc.
    Inventors: David T. Hass, Basab Mukherjee
  • Integrated search engine devices having pipelined node maintenance sub-engines therein that support database flush operations
    Patent number: 7987205
    Abstract: An integrated search engine device contains a pipelined arrangement of a plurality of search and tree maintenance sub-engines therein. This pipelined arrangement of sub-engines includes a hierarchical memory, which is configured to store a plurality of databases of search prefixes. These databases are arranged as a corresponding plurality of multi-way trees that span multiple levels of the hierarchical memory. The plurality of search and tree maintenance sub-engines are configured to respond to a database flush command by redesignating active nodes of a selected database within the hierarchical memory as free nodes using downstream and upstream communications between the plurality of search and tree maintenance sub-engines.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: July 26, 2011
    Assignee: NetLogic Microsystems, Inc.
    Inventor: Gary Depelteau
  • Advanced processor scheduling in a multithreaded system
    Patent number: 7984268
    Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.
    Type: Grant
    Filed: July 23, 2004
    Date of Patent: July 19, 2011
    Assignee: NetLogic Microsystems, Inc.
    Inventors: David T. Hass, Abbas Rashid
  • Method and apparatus for a mesochronous transmission system
    Patent number: 7978802
    Abstract: A method and apparatus for a multiple lane transmission system that provides both a low latency mode of operation, while at the same time, provides reduced lane-lane skew. The overall transmission system operates as a mesochronous system, whereby each clock domain of the transmission system is synchronized to the leaf nodes of a global clock tree. A phase aligner is then used to align the phase of both the bit and byte clocks of each transmission lane to the clock signal generated at the leaf nodes of the global clock tree.
    Type: Grant
    Filed: October 12, 2007
    Date of Patent: July 12, 2011
    Assignees: Xilinx, Inc., NetLogic Microsystems, Inc.
    Inventors: Prasun K. Raha, Donald Stark, Dean Liu, Pak Shing Chau
  • Packet matching method and system
    Patent number: 7978709
    Abstract: A method of constructing a hierarchical database from an initial plurality of rules. A first rule of the initial plurality of rules is added to: a first sub-database if a first bit of the rule is a logic ‘0’ value; a second sub-database if the first bit is a logic ‘1’ value; or a third sub-database if the first bit is in a masked state, ‘X’, indicating that the first bit may be either a logic ‘1’ or a logic ‘0’ value.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: July 12, 2011
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Srinivasan Venkatachary, Pankaj Gupta
  • Multiple string searching using ternary content addressable memory
    Patent number: 7969758
    Abstract: Disclosed herein is a method and apparatus for multiple string searching using a ternary content addressable memory. The method includes receiving a text string having a plurality of characters and performing an unanchored search of a database of stored patterns matching one or more characters of the text string using a state machine, wherein the state machine comprises a ternary content addressable memory (CAM) and wherein the performing comprises comparing a state and one of the plurality of characters with contents of a state field and a character field, respectively, stored in the ternary CAM. In the method and apparatus described herein, one or more of the following search features may be supported: exact string matching, inexact string matching, single character wildcard matching, multiple character wildcard matching, case insensitive matching, parallel matching and rollback.
    Type: Grant
    Filed: September 16, 2008
    Date of Patent: June 28, 2011
    Assignee: NetLogic Microsystems, Inc.
    Inventor: Sunder Rathnavelu Raj
  • Advanced processor with mechanism for enforcing ordering between information sent on two independent networks
    Patent number: 7961723
    Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: June 14, 2011
    Assignee: NetLogic Microsystems, Inc.
    Inventor: David T. Hass
  • Integrated search engine devices that support database key dumping and methods of operating same
    Patent number: 7953721
    Abstract: Methods of operating a search engine device include repeatedly reading next keys (and associated handles) from a database within the search engine device in order to identify and transfer some or possibly all of the contents of the database to another device (e.g., command host) requesting the database contents. An operation to read a next key includes: (i) searching a pipelined database within the search engine device with a first key to identify at least one key therein that is greater than the first key and then (ii) executing a next key fetch operation in the pipelined database to identify the next key from the at least one key. The next key and a handle associated with the next key are then retrieved from the search engine device (e.g., transferred to a command host).
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: May 31, 2011
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Gary Depelteau, David Walter Carr
  • Integrated circuit device with electronically accessible device identifier
    Patent number: 7943400
    Abstract: An semiconductor device having a plurality of fabrication layers. A first region of a first fabrication layer of the semiconductor device is revised. To signal the revision, a connectivity structure in a second region of the first fabrication layer is omitted to interrupt an otherwise continuous signal path that extends through a plurality of interconnection layers of the semiconductor device.
    Type: Grant
    Filed: May 7, 2007
    Date of Patent: May 17, 2011
    Assignee: NetLogic Microsystems, Inc.
    Inventor: Bindiganavale S. Nataraj
  • Ternary content addressable memory having reduced leakage effects
    Patent number: 7944724
    Abstract: A column of ternary content addressable memory (TCAM) cells includes a bit line pair that is twisted at a location at or near the center of the column. Data is written to (and read from) TCAM cells located above the twist location with a first bit line polarity. Data is written to (and read from) TCAM cells located below the twist location with a second bit line polarity, opposite the first bit line polarity. As a result, read leakage currents introduced by TCAM cells storing ‘Don't Care’ values are reduced.
    Type: Grant
    Filed: April 28, 2009
    Date of Patent: May 17, 2011
    Assignee: NetLogic Microsystems, Inc.
    Inventor: Scott Chu
  • Programmable address space built-in self test (BIST) device and method for fault detection
    Patent number: 7945823
    Abstract: A built-in self-test (BIST) circuit for testing addressable locations can include a BIST generator (202) that can generate test addresses for testing each addressable location. Defective addresses can be stored in a fault address store (216). An address range selector circuit (230) can limit the range of addresses generated by an address generator (234). Once defective addresses for a first range have been detected, an address range selector circuit (230) can test another range. An entire address range can thus be tested regardless of the depth of a fault address store (216).
    Type: Grant
    Filed: March 2, 2007
    Date of Patent: May 17, 2011
    Assignee: Netlogic Microsystems, Inc.
    Inventors: Ramesha Doddamane, Eswar Vadlamani, Gopalakrishnan Perur Krishnan, Tarjinder Singh
  • Mechanism for managing access to resources in a heterogeneous data redirection device
    Patent number: 7944829
    Abstract: A system and method for policing of access to resources in a heterogeneous data redirection device is disclosed. The invention utilizes Random Early Detection to determine whether or not a given packet should be dropped or accepted into the resource. The invention uses a combination of different metrics each of which utilizes a different version of RED. Schemes can include a Per-Flow Weighted RED metric, a Global RED metric and a Fair Share Pool metric, where shared resource allocation is dependent dynamically upon the number of users at the time a packet requests access. These metrics can be combined in variety of ways to yield a final drop or accept decision for an incoming packet so that it does not access resources.
    Type: Grant
    Filed: March 28, 2005
    Date of Patent: May 17, 2011
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Paolo Narvaez, Murat Bog
  • Method and apparatus for implementing cache coherency of a processor
    Patent number: 7941603
    Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: May 10, 2011
    Assignee: NetLogic Microsystems, Inc.
    Inventor: David T. Hass
  • Match line precharge circuits and methods for content addressable memory (CAM) device
    Patent number: 7936577
    Abstract: A content addressable memory (CAM) may include a plurality of precharge circuits, each coupled to a group of CAM cells and comprising a first precharge path that is temporarily enabled in response to an activated first control signal, and a second precharge path that is temporarily enabled in response to an activated second control signal and a valid indication that indicates whether or not the corresponding group of CAM cells stores valid data, the valid indication being different than the first and second control signals.
    Type: Grant
    Filed: December 9, 2010
    Date of Patent: May 3, 2011
    Assignee: Netlogic Microsystems, Inc.
    Inventor: Martin Fabry
  • Packet classification device for storing groups of rules
    Patent number: 7933282
    Abstract: A packet classification device includes a CAM device, an SRAM device, and a control circuit that controls and coordinates the operations of the CAM and SRAM devices. For some embodiments, a first CAM block stores unique entries for each packet header field, a RAM block coupled to the first CAM block stores field labels for the unique packet header fields, a second CAM block stores group labels consisting of unique combinations of concatenated field labels, and a second RAM block coupled to the second CAM block stores a group identification (ID) for each group label, wherein each group ID identifies a corresponding one of the groups of rules.
    Type: Grant
    Filed: November 5, 2007
    Date of Patent: April 26, 2011
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Pankaj Gupta, Liao Wei-Cherng
  • Longest matching prefix search engine with hierarchical decoders
    Patent number: 7933885
    Abstract: A search engine searches a database for key candidates having a longest matching prefix with a search key. The search engine includes first stage decoders each having a matrix of interconnected cells for identifying preliminary candidate keys in the database. The search engine also includes a second stage decoder having a matrix of interconnected cells for identifying secondary candidate keys from the preliminary candidate keys. Additionally, the search engine includes a longest candidate prefix module to determine whether one of the secondary candidate keys matches the search key. In some embodiments, the search engine includes a longest prefix match module for identifying the secondary candidate key having a longest matching prefix with the search key.
    Type: Grant
    Filed: April 25, 2008
    Date of Patent: April 26, 2011
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Cristian Lambiri, Paul Nadj
  • Prefix matching structure and method for fast packet switching
    Patent number: 7934198
    Abstract: A prefix matching apparatus for directing information to a destination port includes a memory configured to store a piece of data including an address and a plurality of levels each including a plurality of memory locations, the levels each representing a unique address space. A controller is coupled to the memory and to the plurality of levels, and is configured to read the data address and to direct the data to the next level associated with a unique address space associated with the data address. In one embodiment, the controller is configured to match the data address prefix to a plurality of addresses associated with the unique address spaces. Advantages of the invention include fast switch decisions and low switch latency.
    Type: Grant
    Filed: October 18, 2004
    Date of Patent: April 26, 2011
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Frederick R. Gruner, Gaurav Singh, Elango Ganesan, Samir C. Vora, Christopher M. Eccles, Brian Hang Wai Yang
  • Row redundancy for content addressable memory having programmable interconnect structure
    Patent number: 7924589
    Abstract: A content addressable memory (CAM) device includes an array having a number N of CAM rows, each row including a plurality of CAM cells coupled to a match line, a spare CAM row including a plurality of CAM cells coupled to a spare match line, and row replacement circuitry configured to functionally replace a defective CAM row and each subsequent CAM row in the array with corresponding next adjacent CAM rows, wherein a last CAM row in the array is functionally replaced by the spare CAM row.
    Type: Grant
    Filed: January 12, 2009
    Date of Patent: April 12, 2011
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Varadarajan Srinivasan, Sandeep Khanna
  • Compiling regular expressions for programmable content addressable memory devices
    Patent number: 7924590
    Abstract: A content search system includes CAM device, a compiler, and an image loader. The CAM device, which includes a plurality of rows of CAM cells and a number of counter circuits selectively interconnected by a programmable interconnect structure (PRS), performs regular expression search operations. The compiler selectively converts the regular expression into a number of various bit groups, and the image loader loads corresponding bit groups into the CAM cells, into a number of memory elements that control configuration of the PRS, and into the counter circuits.
    Type: Grant
    Filed: July 27, 2010
    Date of Patent: April 12, 2011
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Alexei Starovoitov, Maheshwaran Srinivasan, Varadarajan Srinivasan, Sandeep Khanna, Sachin Joshi, Mark Birman
  • Advanced processor with mechanism for fast packet queuing operations
    Patent number: 7924828
    Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: April 12, 2011
    Assignee: NetLogic Microsystems, Inc.
    Inventors: David T. Hass, Abbas Rashid