Patents Assigned to NetLogic Microsystems
  • SYSTEMS AND METHODS FOR UTILIZING AN EXTENDED TRANSLATION LOOK-ASIDE BUFFER HAVING A HYBRID MEMORY STRUCTURE
    Publication number: 20100318763
    Abstract: Extended translation look-aside buffers (eTLB) for converting virtual addresses into physical addresses are presented, the eTLB including, a physical memory address storage having a number of physical addresses, a virtual memory address storage configured to store a number of virtual memory addresses corresponding with the physical addresses, the virtual memory address storage including, a set associative memory structure (SAM), and a content addressable memory (CAM) structure; and comparison circuitry for determining whether a requested address is present in the virtual memory address storage, wherein the eTLB is configured to receive an index register for identifying the SAM structure and the CAM structure, and wherein the eTLB is configured to receive an entry register for providing a virtual page number corresponding with the plurality of virtual memory addresses.
    Type: Application
    Filed: August 18, 2010
    Publication date: December 16, 2010
    Applicant: NETLOGIC MICROSYSTEMS, INC.
    Inventors: Gaurav SINGH, Dave HASS, Daniel CHEN
  • Match line precharge circuits and methods for content addressable memory (CAM) device
    Patent number: 7852652
    Abstract: A content addressable memory (CAM) device can include a number of match lines, each coupled to a plurality of CAM cells. The CAM device also includes one or more one precharge circuits. Such a precharge circuit can have a first precharge path that couples a match line to a precharge voltage node in response the activation of a first control signal, and a second precharge path that couples the match line to the precharge voltage node in response to the activation of a second control signal. Prior to a compare operation leakage current through the CAM cells can prevented by disabling the precharge paths and isolating the CAM cells from a reference voltage (e.g., ground). The second control signal can be activated after the first control signal in a compare operation.
    Type: Grant
    Filed: June 27, 2008
    Date of Patent: December 14, 2010
    Assignee: Netlogic Microsystems, Inc.
    Inventor: Martin Fabry
  • Dynamically partitioned CAM array
    Patent number: 7848129
    Abstract: A content addressable memory (CAM) device includes a comparand register, a CAM array, and partition logic. The comparand register has inputs to receive a search key, and outputs coupled to the CAM array, which includes a plurality of individually selectable sub-arrays. Each sub-array includes a number of rows of CAM cells and a control circuit, wherein each row of CAM cells is coupled to a match line, and wherein the control circuit has an input to receive a corresponding sub-array enable signal. The partition logic has an input to receive a partition select signal, and is configured to generate the sub-array enable signals in response to the partition select signal. The control circuits selectively propagate the search key through the sub-arrays in response to the sub-array enable signals.
    Type: Grant
    Filed: November 20, 2008
    Date of Patent: December 7, 2010
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Chetan Deshpande, Vinay Iyengar, Bindiganavale S. Nataraj
  • Analog echo canceller with filter banks
    Patent number: 7843859
    Abstract: A method and system are described for canceling an echo signal in analog domain with adaptive filters working in digital domain. In one embodiment, a system includes an analog-to-digital converter (ADC) sampling at two different phases to generate a first error signal and a second error signal having different phases. The ADC operates at a frequency significantly lower than the frequency at which the individual filters run. The first adaptive filter unit and a second adaptive filter unit are independently trained with the first and second error signals, respectively. The first and second adaptive filter units generate echo estimate signals used to cancel the echo signal.
    Type: Grant
    Filed: September 23, 2008
    Date of Patent: November 30, 2010
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Roubik Gregorian, Gaurav Malhotra
  • Combined processor access and built in self test in hierarchical memory systems
    Patent number: 7844867
    Abstract: A hierarchical memory includes a plurality of memory blocks, a common access bus coupled to the plurality of memory blocks, and a host bus interface coupled to the common access bus and configured to provide communication between an external host and the plurality of memory blocks over the common access bus. The memory further includes a Built-In Self Test (BIST) module coupled to the common access bus and configured to communicate with the plurality of memory blocks over the common access bus, and a test access interface coupled to the BIST main module and configured to receive test instructions and test data, to provide the test data to the BIST main module, and to configure the BIST main module in response to the test instructions. BIST operations are carried out in the memory blocks in response to BIST control signals and test data transmitted by the BIST module over the common access bus.
    Type: Grant
    Filed: December 19, 2007
    Date of Patent: November 30, 2010
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Sudhakar Reddy, Gary Depelteau
  • System and method for performing a register renaming operation utilizing hardware which is capable of operating in at least two modes utilizing registers of multiple widths
    Patent number: 7840783
    Abstract: A system, method, and computer program product are provided for performing a register renaming operation utilizing hardware which operates in at least two modes. In operation, hardware is operated in at least two modes including a first mode for operating the hardware using a logical register of a first bit width and a second mode for operating the hardware using a logical register of a second bit width. The first bit width is twice a width of the second bit width. Additionally, a register renaming operation is performed, including renaming at least one logical register to at least one physical register of the first bit width, utilizing the hardware.
    Type: Grant
    Filed: September 10, 2007
    Date of Patent: November 23, 2010
    Assignee: Netlogic Microsystems, Inc.
    Inventors: Gaurav Singh, Srivatsan Srinivasan, Ricardo Ramirez, Wei-Hsiang Chen, Hai Ngoc Nguyen
  • Output queued switch with a parallel shared memory, and method of operating same
    Patent number: 7835334
    Abstract: A network switch includes an input layer to receive a data stream with a set of cells. Each cell includes data and a header to designate a destination device. The input layer includes a set of input layer circuits. A selected input layer circuit of the set of input layer circuits receives the data stream. The selected input layer circuit includes a set of queues corresponding to a set of destination devices. The selected input layer circuit is configured to assign a selected cell from the data stream to a selected queue of the set of queues. The selected queue corresponds to a selected destination device specified by the header of the selected cell. An intermediate layer includes a set of intermediate layer circuits, each intermediate layer circuit has a set of buffers corresponding to the set of destination devices.
    Type: Grant
    Filed: August 26, 2008
    Date of Patent: November 16, 2010
    Assignee: Netlogic Microsystems, Inc.
    Inventors: Kai-Yeung (Sunny) Siu, Brain Hang Wai Yang, Mizanur M. Rahman
  • Method and apparatus for overlaying flat and/or tree based data sets onto content addressable memory (CAM) device
    Patent number: 7836246
    Abstract: A content addressable memory device (100) and method can have CAM blocks (102-0 to 102-29) organized in block sections (104-0 to 104-6). In an overlay mode of operation, an overlay engine (106) can access an algorithmic search (SPEAR) CAM (102-28 and 102-29) to generate overlay data set search keys (keyFIB<0> and <1>). Multiple data sets (e.g., FIB0, FIB1, ACL0) can be accommodated on the same CAM device by search key multiplexers (108-0 to 108-6) that selectively apply any of a number of data set search keys (keyACL<0>, keyFIB<0> and keyFIB<1>).
    Type: Grant
    Filed: June 23, 2008
    Date of Patent: November 16, 2010
    Assignee: Netlogic Microsystems, Inc.
    Inventors: Mark Birman, Ajay Srikrishna, Srinivasan Venkatachary
  • Integrated search engine devices having a plurality of multi-way trees of search keys therein that share a common root node
    Patent number: 7831626
    Abstract: An integrated search engine includes a hierarchical memory configured to support a plurality of multi-way trees of search keys. These multi-way trees, which share a common root node, support respective databases of search keys. The child pointers associated with search keys within the common root node may be allocated at a single key level of granularity, which means that each search key within the common root node may be associated with a pair of child pointers when each search key within the common root node is associated with a different multi-way tree of search keys.
    Type: Grant
    Filed: September 20, 2007
    Date of Patent: November 9, 2010
    Assignee: NetLogic Microsystems, Inc.
    Inventor: Gary Depelteau
  • Low power content addressable memory
    Patent number: 7830691
    Abstract: A low power content addressable memory (CAM) device. The CAM device receives an N-bit comparand value and, in response, activates less than N compare lines within the CAM device to compare each of the N bits of the comparand value with contents of CAM cells coupled to the N compare lines.
    Type: Grant
    Filed: July 17, 2008
    Date of Patent: November 9, 2010
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Varadarajan Srinivasan, Sandeep Khanna, Bindiganavale S. Nataraj
  • Content addresable memory having selectively interconnected counter circuits
    Patent number: 7826242
    Abstract: A content addressable memory (CAM) device includes a plurality of CAM rows, a number of sequencing logic circuits, and a programmable interconnect structure. Each CAM row includes a number of CAM cells to generate a match signal on a match line and includes an enable input. Each sequencing logic circuit includes an input and an output, and is configured to count sequences of match signals from the CAM rows. The programmable interconnect structure selectively connects the match line of any CAM row to the input of any sequencing logic circuit, and selectively connects the output of any sequencing logic circuit to the enable input of any CAM row.
    Type: Grant
    Filed: November 16, 2009
    Date of Patent: November 2, 2010
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Sachin Joshi, Mark Birman, Maheshwaran Srinivasan, Sandeep Khanna, Varadarajan Srinivasan
  • Advanced telecommunications router and crossbar switch controller
    Patent number: 7826477
    Abstract: The invention relates to a crossbar switch controller including an input terminal configured to receive a set of service request signals from a set of virtual output queues each comprising a set of packets. The invention also includes a matrix circuit coupled to the input terminal and configured to represent the set of service request signals in the form of a matrix, wherein each service request signal is described by a row position M and a column position N. The invention further includes an output terminal configured to receive a portion of the set of packets during an epoch, an arbiter circuit configured to iteratively scan the matrix during the epoch and issue the set of grant signals to the virtual output queues to determine which service requests are granted, and an arbiter controller configured to initiate the arbiter circuit with an array of non-conflicting matrix elements.
    Type: Grant
    Filed: July 9, 2008
    Date of Patent: November 2, 2010
    Assignee: Netlogic Microsystems, Inc.
    Inventors: Brian Hang Wal Yang, Kai-Yeung (Sunny) Siu, Mizanur M. Rahman, Wei-Han Lien, Gaurav Singh
  • Integrated circuit search engine devices having priority sequencer circuits therein that sequentially encode multiple match signals
    Patent number: 7822916
    Abstract: A search engine device includes a lookup circuit, such as a content addressable memory (CAM) array. This lookup circuit is configured to generate multiple active match signals in response to detecting multiple matches between a search operand applied to said lookup circuit and multiple entries therein, during a search operation. A priority sequencer circuit is also provided. This priority sequencer circuit, which is electrically coupled to outputs of the lookup circuit, is configured to sequentially encode each of the multiple active match signals according to priority.
    Type: Grant
    Filed: October 31, 2006
    Date of Patent: October 26, 2010
    Assignee: NetLogic Microsystems, Inc.
    Inventor: Tingjun Wen
  • Content addresable memory having programmable interconnect structure
    Patent number: 7821844
    Abstract: A content addressable memory (CAM) device includes a CAM array, a programmable interconnect structure, and a priority encoder. The CAM array includes a plurality of CAM rows, each row including a number of CAM cells for storing a data word and coupled to a match line that indicates a match result for the CAM row. The programmable interconnect structure is coupled to each CAM row and a plurality of CAM rows, each row including a number of CAM cells for storing a data word and coupled to a match line that indicates match results for the row. The programmable interconnect structure coupled to each CAM row, and is configured to logically connect any number N of selected CAM rows together to form a data word chain spanning N rows, regardless of whether the selected CAM rows are contiguous.
    Type: Grant
    Filed: November 12, 2009
    Date of Patent: October 26, 2010
    Assignee: NetLogic Microsystems, Inc
    Inventors: Maheshwaran Srinivasan, Varadarajan Srinivasan, Sandeep Khanna, Sachin Joshi, Mark Birman
  • Content addressable memory (CAM) cell having column-wise conditional data pre-write
    Patent number: 7813155
    Abstract: A content addressable memory (CAM) device can include a plurality of CAM cells arranged in rows and columns to form multi-byte words. Each CAM cell can include a comparator circuit and one or more data storing circuits. Each comparator circuit can have one or more charge transfer paths arranged between a match line and a first voltage source node. Each data storing circuit can include a write circuit that provides a controllable impedance path between one or more charge transfer paths and a data storage node of the data storing circuit.
    Type: Grant
    Filed: October 22, 2008
    Date of Patent: October 12, 2010
    Assignee: Netlogic Microsystems, Inc.
    Inventor: Dinesh Maheshwari
  • Row expansion reduction by inversion for range representation in ternary content addressable memories
    Patent number: 7814268
    Abstract: A method and circuit to implement a match against range rule functionality. A first rule entry and a second rule entry are stored. The first rule entry includes at least two consecutive identical bits. The first rule entry represents a numerical range. A first field of a binary key is compared with the first rule entry to determine whether any of the bits of the first field are not identical. A logical result of the comparison between the first field and the first rule entry is inverted to generate a first comparison result. A second field of the binary key is compared with a second rule entry to generate a second comparison result. The first comparison result is then logically ANDed with the second comparison result to determine whether the binary key falls within the numerical range represented by the first rule entry and matches the second rule entry.
    Type: Grant
    Filed: February 25, 2008
    Date of Patent: October 12, 2010
    Assignee: Netlogic Microsystems, Inc.
    Inventor: Dinesh Maheshwari
  • Partial row expansion by logically combining range representation values in content addressable memory
    Patent number: 7814266
    Abstract: A method and apparatus to reduce the number of rule entries used to implement ranging matching in a Content Addressable Memory (“CAM”) array. A first CAM entry is stored in a single CAM cell of an array of CAM cells. The first CAM entry is compared with a first key entry of the CAM array to generate a first comparison result. Each of multiple second CAM entries is stored in corresponding multiple CAM cells of the array of CAM cells. The multiple second CAM entries are compared with a second key entry to generate multiple second comparison results. A match signal is generated by the CAM array if the first key entry matches the first CAM entry and the second key entry matches one of the multiple second CAM entries.
    Type: Grant
    Filed: September 1, 2005
    Date of Patent: October 12, 2010
    Assignee: Netlogic Microsystems, Inc.
    Inventor: Dinesh Maheshwari
  • Processor with compare operations based on any of multiple compare data segments
    Patent number: 7814267
    Abstract: A processor device integrated circuit can include a plurality of storage locations logically configurable into at least one database. Such a database can include a number of records, record having a selectable size of up to F multi-bit segments, where F is an integer greater than one. A search key application circuit can apply a search key value of up to F multi-bit segments to the at least one database in response to receiving one search key segment value. The one search key segment can be applied as any of the F multi-bit segments according to a segment selection value.
    Type: Grant
    Filed: February 4, 2008
    Date of Patent: October 12, 2010
    Assignee: Netlogic Microsystems, Inc.
    Inventors: Vinay Raja Iyengar, Venkat Rajendher Reddy Gaddam, Aparna Bharat
  • System and Method for Performing Concatenation of Diversely Routed Channels
    Publication number: 20100254709
    Abstract: A system and method are provided for performing Local Centre Authorization Service (LCAS) in a network system, the system having a data aligner configured to align bytes of input data according to groups of members. The system also including an LCAS control manager configured to generate de-sequencing control commands in response to data input from the data aligner. The system further including a de-sequencer configured to de-sequence the input data input from the data aligner according to de-sequencing control commands received from the LCAS control manager.
    Type: Application
    Filed: March 2, 2010
    Publication date: October 7, 2010
    Applicant: NETLOGIC MICROSYSTEMS, INC.
    Inventors: Paolo Narvaez, Murat Bog
  • Transistor with spatially integrated schottky diode
    Patent number: 7808223
    Abstract: An integrated circuit device for delivering power to a load includes a composite transistor and a composite schottky diode. The composite transistor is formed by a plurality of component transistors that have commonly coupled source terminals, commonly coupled drain terminals and commonly coupled gate terminals. The composite schottky diode is formed by a plurality of component schottky diodes that have anodes coupled in common and coupled to the source terminals of the plurality of component transistors, and for which drain terminals of the commonly coupled drain terminals constitute respective cathodes.
    Type: Grant
    Filed: May 8, 2007
    Date of Patent: October 5, 2010
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Sandeep Khanna, Mozafar Maghsoudnia