Abstract: A content addressable memory (CAM) architecture. For one embodiment, the CAM architecture includes a plurality of rows of CAM cells, each row configured to generate match results on a corresponding match line, a number of comparand lines, each coupled to a corresponding CAM cell in each of the plurality of rows of CAM cells, a plurality of timed storage circuits, each having a data input coupled to a corresponding match line and having an enable input coupled to an enable signal line, a timing generator configured to generate an enable signal on the enable signal line, and a plurality of load elements.

Abstract: A system and method are provided for reducing the capacitive coupling noise on a fuse line of a content addressable memory (CAM) system. The CAM system includes a plurality of CAM arrays having a plurality of rows of CAM cells to store data coupled to wordlines, searchlines, bitlines and matchlines for reading from, writing to, and searching data in the CAM cells and a hit circuit coupled to the matchlines of each of the plurality of CAM arrays, the hit circuit to compare the data stored in the CAM cells against data presented on the wordlines of the CAM array.

Abstract: Cost-based methods of exchanging/transferring intellectual property (IP) among parties are provided that include royalty rates and mark-up rates based on a common factor. The common factor of an embodiment includes the cost of a component material of a product. The IP includes at least one of technology, patents, and trade secrets. The methods include a first company that transfers IP to a second company. The first and second companies, in effecting the transfer, establish a royalty rate that is a first percentage of a cost of a component material of the products and a mark-up rate that is a second percentage of the cost of the component material.

Abstract: A system and method are provided for performing Local Center Authorization Service (LCAS) in a network system, the system having a data aligner configured to align bytes of input data according to groups of members. The system also including an LCAS control manager configured to generate de-sequencing control commands in response to data input from the data aligner. The system further including a de-sequencer configured to de-sequence the input data input from the data aligner according to de-sequencing control commands received from the LCAS control manager.

Abstract: A digital linear voltage regulator includes a comparator, a finite state machine, and a current digital-to-analog converter (DAC). The comparator is preferably coupled to receive a reference voltage and an operating voltage supplied to a dynamic load. The comparator generates, during a clock cycle, a binary output based on a comparison between reference and operating voltages. The finite state machine (FSM) is coupled to receive at least one control signal that indicates a target operating state for the digital linear voltage regulator. The FSM receives the binary output from the comparator and generates a digital word, during a clock cycle, based on the target operating state of the digital linear voltage regulator and on the binary output. The current DAC is coupled to the FSM, receives the digital word and delivers current at the desired voltage to the dynamic load.

Abstract: A search engine for selectively perform iterative compare operations between a searchable pattern and S overlapping substrings of an input string of characters includes a memory for storing a bitmap having S next success size (NSS) bits, wherein each NSS bit indicates whether an associated substring including a corresponding unique number of the input characters is to be compared with the searchable pattern in successive compare operations, and includes a compare circuit for selectively performing the successive compare operations in response to the NSS bits.

Abstract: Content addressable memory (CAM) devices use both hard and soft priority techniques to allocate entries of different priority therein. The priorities of multiple CAM array blocks within the CAM device may be programmed before or as entries are loaded therein and may be reprogrammed during operation as the allocation of entries within the CAM device changes. The allocation of entries may change in response to additions or deletions of entries or as entries are reprioritized. The CAM devices include preferred priority resolution circuits that can resolve competing soft and hard priorities between multiple hit signals that are generated in response to a search operation. Such hit signals may be active to reflect the presence of at least one matching entry within a CAM array block. The resolution of which active hit signal has the highest overall priority among many can be used to facilitate the identification of the location (e.g.

Abstract: A traffic management processor configured to selectively terminate individual traffic flows includes an instruction decoder to receive a termination instruction specifying which traffic flows are to be deleted, and a content addressable memory device having a plurality of rows, each including a flow ID and termination bit for a corresponding packet.

Abstract: A content addressable memory (CAM) device includes a plurality of CAM rows, a number of sequencing logic circuits, and a programmable interconnect structure. Each CAM row includes a number of CAM cells to generate a match signal on a match line and includes an enable input. Each sequencing logic circuit includes an input and an output, and is configured to count sequences of match signals from the CAM rows. The programmable interconnect structure selectively connects the match line of any CAM row to the input of any sequencing logic circuit, and selectively connects the output of any sequencing logic circuit to the enable input of any CAM row.

Abstract: A system for searching an input string for a number of regular expressions includes a search block and a compiler. The search block includes a plurality of content addressable memory (CAM) devices, wherein each of the CAM devices is differently configured to implement search operations for regular expressions having a unique level of complexity. The compiler is configured to determine the complexity level of each of the regular expressions, and is configured to store each regular expression in a selected one of the CAM devices according to its complexity level.

Abstract: A pipelined search engine device, such as a longest prefix match (LPM) search engine device, includes a hierarchical memory and a pipelined tree maintenance engine therein. The hierarchical memory is configured to store a b-tree of search prefixes (and possibly span prefix masks) at multiple levels therein. The pipelined tree maintenance engine, which is embedded within the search engine device, includes a plurality of node maintenance sub-engines that are distributed with the multiple levels of the hierarchical memory. The search engine device may also include pipeline control and search logic that is distributed with the multiple levels of the hierarchical memory.

Abstract: A content addressable memory (CAM) device includes a CAM array, a programmable interconnect structure, and a priority encoder. The CAM array includes a plurality of CAM rows, each row including a number of CAM cells for storing a data word and coupled to a match line that indicates a match result for the CAM row. The programmable interconnect structure is coupled to each CAM row and is configured to selectively route the match results from a first CAM row as an input match signal to any number of arbitrarily selected CAM rows at the same time.

Abstract: A content search system for determining whether a plurality of input strings each belonging to any one of a number of different process flows matches one or more of a plurality of regular expressions, including a search circuit for searching the input strings for the regular expressions and a data management unit including a control circuit having an input to receive the plurality of input strings, wherein each input string has an associated flow identification (ID) value, a packet queue having a number of storage locations for storing the input strings, and a flow engine that forwards a selected input string from the packet queue to the search circuit.

Abstract: A search tree embodying a plurality of signatures to be compared with an input string of characters and including a number of success transitions characterized by a success size parameter and including a number of failure transitions characterized by a failure size parameter is selectively modified to achieve a desired balance between processing speed and memory area requirements.

Abstract: A method and apparatus for multiple string searching using a ternary content addressable memory. For one embodiment, the method includes receiving a text string having a plurality of characters and performing an unanchored search of a database of a stored patterns matching one or more characters of the text string using a state machine, wherein the state machine comprises a ternary content addressable memory (CAM) and wherein the performing comprises comparing a state and one of the plurality of characters with contents of a state field and a character field, respectively, stored in the ternary CAM. In various embodiments, one or more of the following search features may be supported: exact string matching, inexact string matching, single character wildcard matching, multiple character wildcard matching, case insensitive matching, parallel matching and rollback.

Abstract: A communication network, networking device and method is provided herein for locating (i.e., searching for) an interval of numbers i within a set of numbers N given a point P. The search algorithm provided herein provides fast search speed (e.g., requires only one memory access) with minimum storage requirements (e.g., consumes up to, but not exceeding, N entries within a memory device).

Abstract: A search engine configured to determine whether an input string including a plurality of input characters matches a regular expression including an inexact pattern including a specified range of instances of pattern characters each belonging to a specified set of characters, the search engine including a microcontroller having an input to receive a microprogram embodying the inexact pattern, a first co-processor coupled to the microcontroller and dedicated to determine whether each input character in a first portion of the input string is a member of the specified set of characters, and a second co-processor coupled to the microcontroller and dedicated to determine whether the number of input characters in the first portion of the input string falls within the specified range.

Abstract: A traffic management processor for scheduling packets for transmission across a network includes a departure time calculator for generating a departure time for each packet, a departure time prioritizer for comparing the departure times with each other to determine which of the departure times is the earliest, and a token generator for generating a token for each packet.

Abstract: In a signature searching system, contents of a ternary content addressable memory (CAM) are searched to obtain a first index value that corresponds to a first group of predetermined data sequences. The first group of predetermined data sequences is selected from among a plurality of groups of predetermined data sequences based, at least in part, on the first index value, and a determination made as to whether any of the predetermined data sequences within the first group is present within a stream of data.

Abstract: A method for representing a search tree embodying a plurality of signatures to be searched for in an input string of characters constructs a failure tree in which the states are re-organized in levels according to the number of failure transitions between each state and the root node of the search tree.