Abstract: A level shifting circuit can include a shift stage that latches first and second internal nodes to opposite shifted logic potentials in response to different transitions at an input signal node. The input signal node can vary between non-shifted logic potentials. An output stage can enable a first controllable impedance path coupled between an output node and a first shifted power supply node in response to a first type transition at the first internal node, and can enable a second controllable impedance path coupled between the output node and a second shifted power supply node in response to the first type transition at the second internal node.

Abstract: A method for assigning state codes to states of a state diagram embodying a plurality of signatures to be searched for in an input string of characters re-organizes the states of a search tree embodying the signatures to construct a failure tree in which the states are organized in levels according to a number of failure transitions between each state and the root node of the search tree.

Abstract: An integrated circuit search engine device supports a multi-way tree of search keys therein. The search engine device includes at least one multi-node sub-engine. The multi-node sub-engine includes a node processor and a plurality of columns of sub-nodes containing search keys. The node processor is configured to distribute an applied search key in parallel to each of the plurality of columns of sub-nodes in response to a search request. The node processor is also configured to receive and resolve corresponding sub-node search results from the plurality of columns of sub-nodes.

Abstract: An integrated circuit device can include a plurality of compare cell circuits that selectively provide charge transfer path between a result line and a reference node according to a comparison between a stored data value and an applied compare data value during a compare time period. A first precharge circuit can have a controllable impedance path coupled between the result line and a precharge voltage node. A control circuit can place the first precharge circuit into a low impedance state during a first portion of the compare time period, and into a high impedance state during a second portion of the compare time period.

Abstract: Integrated circuit search engine devices include serially connected stages, a handle memory and a handle memory access manager. The stages store search keys in a multilevel tree of search keys. A first level stage is responsive to an input search key and a last level stage identifies a best match key for the input search key. The handle memory includes handle memory locations that store search result handles. The handle memory access manager searches the handle memory to retrieve a search result handle that corresponds to a best match key. The handle memory access manager refrains from modifying the handle memory in response to modify instructions during active periods of the handle memory when the handle memory is being searched. The handle memory access manager modifies the handle memory in response to the modify instructions during idle periods of the handle memory when the handle memory is not being searched. Related methods are also disclosed.

Abstract: Extended translation look-aside buffers (eTLB) for converting virtual addresses into physical addresses are presented, the eTLB including, a physical memory address storage having a number of physical addresses, a virtual memory address storage configured to store a number of virtual memory addresses corresponding with the physical addresses, the virtual memory address storage including, a set associative memory structure (SAM), and a content addressable memory (CAM) structure; and comparison circuitry for determining whether a requested address is present in the virtual memory address storage, wherein the eTLB is configured to receive an index register for identifying the SAM structure and the CAM structure, and wherein the eTLB is configured to receive an entry register for providing a virtual page number corresponding with the plurality of virtual memory addresses.

Abstract: A search engine device that supports a Patricia trie arrangement of search keys includes an array of comparator cells that supports parallel decoding of the Patricia trie. This array of comparator cells processes a plurality of distinguishing bit identifiers for nodes in the Patricia trie in parallel with a corresponding plurality of bits of an applied search key during a search operation. In response to this processing, the array generates a match signal that identifies a location of a matching search key candidate within the Patricia trie.

Abstract: A content addressable memory (CAM) device includes a plurality of independently configurable CAM groups, each CAM group including a number of CAM rows and a programmable combinational logic circuit. Each CAM row includes a plurality of CAM cells coupled to a match line that generates a row match signal during a compare operation between a search key and data stored in the CAM row. The programmable combinational logic circuit logically combines the row match signals to generate a corresponding group match signal according to a respective one of a plurality of selectable logical operations selected by a corresponding function select signal.

Abstract: An integrated circuit device can include a plurality of configuration storage locations each comprising at least one encoding field. Each encoding field can selectively enable at least one received data value to be encoded into an encoded data value prior to being applied to a corresponding block of the integrated circuit device. Each block can comprise a plurality of content addressable memory (CAM) cells.

Abstract: A method and apparatus for multiple string searching using a ternary content addressable memory. For one embodiment, the method includes selecting character groups from an input text string in a temporal sequence, each character group having more than one character. A first character group of the character groups is compared with a plurality of character fields and a current state of a state machine is compared with a plurality of states of the state machine that correspond to the plurality of character fields to identify information indicative of a subsequent state of the state machine. Comparison of the first character group with the plurality of sets of character fields is repeated if the information indicative of the subsequent state of the state machine indicates that a terminal number of characters of a desired character pattern has been located and that the terminal number of characters is fewer than the number of characters in the first character group.

Abstract: An integrated circuit device can include a core section coupled to a plurality of signal paths having a predetermined physical order with respect to one another. A configuration circuit can selectively connect each signal path to a corresponding one of a plurality of physical connection points to the IC device according to one of at least two different physical orders in response to configuration information.

Abstract: A search engine device includes a hierarchical memory that is configured to store a b-tree of search prefixes and span prefix masks (SPMs). These SPMs are evaluated during each search operation to identify search prefixes that match an applied search key yet reside at nodes of the b-tree that are not traversed during the search operation. The search engine device also includes handle memory. This handle memory is configured to support a respective handle memory block for each search prefix within each of a plurality of nodes of the b-tree that reside at a leaf parent level within the b-tree. Each of these handle memory blocks may have sufficient capacity to support one result handle per bit within a span prefix mask associated with a corresponding search prefix. In other cases, each of these handle memory blocks may have sufficient capacity to support only M+1 handles, where M is a positive integer corresponding to a quantity of search prefixes supported by each of a plurality of leaf nodes within the b-tree.

Abstract: A search engine includes a pipelined arrangement of a plurality of search and tree maintenance sub-engines therein, which are configured to support the performance of search operations on exclusively valid multi-way trees of search prefixes concurrently with the performance of update operations on the multi-way trees as they are being searched.

Abstract: A handle allocation manager is provided for an integrated circuit search engine device that includes multiple stages of a multilevel tree of search keys and a handle memory. The handle allocation manager includes a handle availability memory that stores handle availability indicators to provide an indication of whether a handle is available for association with a key. A handle availability summary memory stores indicators for groups of handles and a block availability summary memory stores indicators for multiple groups of handle availability summary memories. The handle allocation manager can use these memories to search for a next available handle. Related methods are also provided.

Abstract: A system for speculative branch predictions. An embodiment of the system includes branch prediction logic, fetch logic, and branch identification logic. The branch prediction logic is configured to predict a branch path for a branch in an instruction stream. The fetch logic is coupled to the branch prediction logic. The fetch logic is configured to speculatively fetch an instruction corresponding to the predicted branch path. The branch identification logic is coupled to the branch prediction logic and the fetch logic. The branch identification logic is configured to mark the speculatively fetched instruction with a branch identifier using a universal branch identification format. The universal branch identification format includes a bit value at a bit position corresponding to the predicted branch path.

Abstract: A content addressable memory (CAM) device, method, and method of generating entries for range matching are disclosed. A CAM device (800) according to one embodiment can include a pre-encoder (806) that encodes range bit values W into additional bits E. Additional bits E can indicate compression of range rules according to particular bit pairs. A CAM array (802) can include entries that store compressed range code values (RANGE) with corresponding additional bit values (ENC). Alternate embodiments can include pre-encoders that encode portions of range values (K1 to Ki) in a “one-hot” fashion. Corresponding CAM entries can include encoded value having sections that each represent increasingly finer divisions of a range space.

Abstract: Methods of updating b-tree data structures (e.g., b*tree data structure) using search key insertion and deletion operations proceed from respective known states (e.g., respective canonical forms). These insertion operations include inserting a first search key into the b-tree by reconfiguring (e.g., pre-processing) a plurality of sibling nodes of the b-tree into a predetermined overloaded form having a shape that is independent of a value of the first search key to be inserted therein. An operation is then performed to split the sibling nodes by redistributing the first and other search keys among an expanded plurality of the sibling nodes. These insertion operations use a process that trades off possibly performing additional memory accesses (e.g., to shift search keys (and/or handles or pointers) to the predetermined overloaded form) for the certainty that the same key movements are ultimately performed during operations to split sibling nodes.

Abstract: A CAM system includes an integrated circuit chip having: logic & control circuitry, a CAM cell array, read/write access circuitry that performs read and write accesses to the CAM cell array, comparison access circuitry that performs comparison operations to the CAM cell array, a first voltage supply pad coupled to the read/write access circuitry; and a second voltage supply pad coupled to the comparison access circuitry. A first voltage supply, external to the integrated circuit chip, provides a first supply voltage to the first voltage supply pad, wherein the logic & control circuitry is powered by the first supply voltage. A second voltage supply, external to the integrated circuit chip, provides a second supply voltage to the second voltage supply pad, wherein at least a portion of the comparison access circuitry is powered by the second supply voltage, wherein the second supply voltage is less than the first supply voltage.

Abstract: A processing system includes a network processor and a CAM device having a re-entrant processor coupled to a CAM array. The re-entrant processor is configured to selectively modify an initial search key provided by the network processor by replacing portions of the initial search key with portions of one or more previous search keys and/or one or more previous results. The re-entrant processor is also configured to initiate a series of subsequent compare operations between new search keys and data stored in the CAM array without receiving additional instructions or search keys from the network processor.

Abstract: A CAM array including volatile or non-volatile ternary CAM cells that discharge their associated match line through a special discharge line (e.g., a low match line), instead of through the bit line, is disclosed. Each ternary CAM cell includes a pair of storage elements that are used to store a data bit value, a comparison element that is used to compare the stored value with an applied data value, and a discharge element that is coupled between the discharge line and the match line. During operation, when the applied data value matches the stored value, the discharge element de-couples the discharge line from the match line (i.e., a high voltage on the match line remains high). Conversely, when the applied data value does not match the stored value, the discharge elements couple the discharge line to the match line, thereby discharging the match line to the discharge line.