Abstract: A content addressable memory device including a memory to store a searchable database, a search circuit, and a first-in-first-out storage circuit. The search circuit generates a plurality of address values that correspond to unoccupied storage locations within the memory, and the plurality of address values are queued within the first-in-first-out storage circuit to enable the address values to be read in succession by an external device.

Abstract: A search engine system (100) is disclosed that can include at least one content addressable memory (CAM) device (102) arranged in a cascade configuration with at least one memory device (104), such as a static random access memory (SRAM). A CAM device (102) and memory device (104) may be connected to one another by point-to-point unidirectional connections. Command data issued by a device, such as a network processing unit (NPU) (110), can flow through all devices beginning with a CAM device (102) and eventually to a memory device (104). A memory device (104) can compare its own current result data with that of a previous device in a flow (such as another RAM device), and generate an output response.

Abstract: A method and circuit to implement a match against range rule functionality. A first rule entry and a second rule entry are stored. The first rule entry includes at least two consecutive identical bits. The first rule entry represents a numerical range. A first field of a binary key is compared with the first rule entry to determine whether any of the bits of the first field are not identical. A logical result of the comparison between the first field and the first rule entry is inverted to generate a first comparison result. A second field of the binary key is compared with a second rule entry to generate a second comparison result. The first comparison result is then logically ANDed with the second comparison result to determine whether the binary key falls within the numerical range represented by the first rule entry and matches the second rule entry.

Abstract: A sense amplifier circuit can be coupled to a match line for receiving a match line voltage and to a low potential line for receiving a low potential voltage from a memory array. The sense amplifier circuit can include a charging circuit coupled between a power supply voltage and the match line voltage that comprises no p-channel transistors. A discharging circuit can be coupled between the low potential voltage and a ground supply voltage. An n-channel sensing device can coupled to detect a potential difference between the match line voltage and the low potential voltage.

Abstract: A traffic management processor for processing different types of traffic flows includes a departure time calculator (DTC) circuit for calculating a departure time for each packet received, a content addressable memory (CAM) device coupled to the DTC circuit and having a plurality of rows, each row including a first portion for storing the departure time for a corresponding packet and including a second portion for storing a bit indicating a traffic type for the packet, and compare logic coupled to the CAM device and configured to determine which of the departure times stored in the CAM device is the earliest.

Abstract: A traffic management processor that selectively throttles individual traffic flows or particular traffic types specified in a throttle control instruction, which may also cause the traffic management processor to throttle all network traffic.

Abstract: A traffic management processor for managing a number of traffic flows each including one or more packets includes a content address memory (CAM) device having a plurality of rows, each row storing a flow identification (ID) for a corresponding packet, the flow ID indicating to which traffic flow the packet belongs, a departure time table for storing departure times for the packets, and compare logic for comparing the departure times with each other to determine which departure time is the earliest.

Abstract: A search engine system (100) can include a key multiplexer (104) and logic circuit (108). A key from a previous operation can be received by logic circuit (108) and altered to generate an idle key. In a non-search operation, the idle key can be applied to a CAM section to draw current as in a normal search operation. Logic circuit (108) can ensure that an idle key value is always different than a previously applied key value.

Abstract: A hierarchical programmable-priority content addressable memory (CAM) system including first, second and third CAM devices. The first CAM device has a first priority number output and a first enable input. The second CAM device has a priority number input and an enable output coupled to the priority number output and the first enable input, respectively, of the first CAM device. The second CAM device also has a priority number output and an enable input. The third CAM device has a priority number input and an enable output coupled to the priority number output and the enable input, respectively, of the second CAM device.

Abstract: A CAM cell (200) can include a compare section (206) and a configuration section (208). In a binary mode of operation, two compare data values can be driven on value lines VL1 to VL4 (216-0 to 216-3) for comparison against two stored data values. In a ternary mode of operation, one compare data value can driven on two of the value lines, while the other two value lines can be forced to a potential unrelated to a compare data value allowing for dynamic configuration between binary and ternary modes of operation.

Abstract: A frequency synthesis circuit includes a phase locked loop and an interpolator circuit. The phase locked loop circuit receives a reference clock and a feedback clock and generates an output clock with a frequency based on the reference clock and the feedback clock. An interpolator circuit is coupled in the feedback path of the phase locked loop circuit. An interpolator control circuit generates an interpolator control word that specifies a variable time delay for the interpolator circuit. The interpolator circuit receives the output clock, and generates the feedback clock by introducing a variable time delay in the output clock in accordance with the interpolator control word. The time variable delay varies the frequency of the output circuit. Embodiments for frequency synthesis circuits that include a spread spectrum frequency clock generator, frequency modulators, and a fixed frequency clock generator circuit are disclosed.

Abstract: A CAM device having a plurality of CAM blocks includes circuitry to disable one or more defective CAM blocks, and to selectively translate address space in the disabled CAM blocks to the remaining enabled CAM blocks. In one embodiment, each CAM block is coupled to a corresponding block select circuit and to an address translation circuit. Each block select circuit provides a select signal to a corresponding CAM block to selectively enable or disable the CAM block. The address translation circuit includes logic that translates address space from disabled (e.g., defective) CAM blocks to enabled (e.g., non-defective) CAM blocks. During read and write operations, an address to access a row in a first of the CAM blocks is received into the address translation logic. If the first CAM block is disabled, the address translation logic translates the address to access a row in a second of the CAM blocks.

Abstract: A content addressable memory (CAM) device having CAM cells arranged in rows and columns. A plurality of first data line pairs extend along respective columns of the CAM cells. A plurality of second data line pairs extend along respective columns of the CAM array adjacent the first data line pairs, each second data line pair having a first and second constituent data lines that cross one another at a point along their lengths.

Abstract: A sense amplifier circuit with faster sensing speed and improved insensitivities to fabrication process variations (i.e., eliminated functional failures) is provided herein. According to one embodiment, the sense amplifier circuit associated with a row of memory cells within a memory device may include a charging portion, which is coupled for receiving a reference voltage that is supplied to at least one additional sense amplifier circuit within the memory device. The reference voltage is provided by a current reference generator, which is coupled to the sense amplifier circuit(s) for detecting: (i) a maximum amount of current that can pass through one compare stack within the memory cell array, or (ii) a difference between the maximum amount of current and the current contribution of an n-channel current source within the sense amplifier circuit. A memory device and method of operating one embodiment of the improved sense amplifier circuit are also provided herein.

Abstract: A ternary content addressable memory (TCAM) cell (100) can include two memory elements (102-0 and 102-1) with a single bit line (106-0 and 106-1) per memory element. A TCAM cell (100) can also include a compare stack (104) and two word lines (114 and 116) that can connect to each memory element (102-0 and 102-1). The memory elements (102-0 and 102-1) can include SRAM type memory cells with one of two data terminals connected to a pre-write potential (Vpre, which can be a ground potential, or the like). Write operations can include pre-setting the data values of memory elements (102-0 and 102-1) to the pre-write potential prior to providing write data via the bit lines (106-0 and 106-1).

Abstract: A CAM system (200) can include a number of entries (202-0 to 202-3) having one portion for storing a data value (e.g., E1) and another portion for storing a replicated data value (E1(REP)). For on-the-fly error correction, the entries can be searched by applying an appended key value that includes a key portion (KEY) and replicated key portion (KEY(REP)).

Abstract: A content addressable memory (CAM) cell circuit can include a match section that enables an impedance path coupled to a match line in response to a comparison between a data value and a compare data value. At least a first storage circuit can be connected to the match section, and provides the data value on a first storage node and a complementary data value on a second storage node. At least a first bit line can be coupled to the first storage node by a first access controllable impedance path and coupled to the second storage node by a second access controllable impedance path.

Abstract: A traffic management processor configured to selectively terminate individual traffic flows includes an instruction decoder to receive a termination instruction specifying which traffic flows are to be deleted, and a content addressable memory device having a plurality of rows, each including a flow ID and termination bit for a corresponding packet.

Abstract: A content addressable memory (CAM) device with selective error logging. The CAM device includes a CAM array and an error detection circuit coupled to receive a data value from a selected storage location within the CAM array, the error detection circuit being adapted to generate an error indication according to whether the data value includes an error. An error storage circuit is coupled to receive the error indication from the error detection circuit and is adapted to store an error address that corresponds to the selected storage location if the error indication indicates that the data value includes an error and if the error address is not already stored within the error storage circuit.

Abstract: A system (200) can provide data aggregation with a single primary table (206) formed in a content addressable memory (CAM) section (202). Within a primary table (206) CAM entries can be part of a primary table, one or more aggregate tables, or both. In one arrangement, valid bits in each CAM entry can indicate which particular schemes a CAM entry belongs to (primary table, or any of the aggregate tables). Associated data for each table can be stored in a RAM section (204) and can be accessed according to an offset address generated according to a scheme value (i).