Abstract: A semiconductor device has an active area and a terminal area surrounding the active area and includes a base region, a plurality of annular subregions, an insulating layer provided with a plurality of insulating layer openings, and a first conductive layer. The plurality of annular subregions includes a first annular subregion in contact with the base region. The first annular subregion includes a plurality of annular structures in contact with each other. All the annular structures contact the first conductive layer through the corresponding insulating layer openings. The base region, the annular subregions, and the annular structures have a second conductivity type.

Abstract: A semiconductor device includes an insulated-gate bipolar transistor (IGBT) structure and a metal-oxide-semiconductor (MOS) transistor structure integrated in a wafer. The MOS transistor structure is connected in parallel with the IGBT structure. A thickness of a trench insulating layer in the MOS transistor structure is less than a thickness of a trench insulating layer in the IGBT structure.

Abstract: A method of manufacturing a cascode HEMT semiconductor device including a lead frame, a die pad with an indentation attached to the lead frame, and a HEMT die attached to the die pad. The HEMT die includes a HEMT source and a HEMT drain on a first side, and a HEMT gate on a second side. The device further includes a MOSFET die attached to the source of the HEMT die, and the MOSFET die includes a MOSFET source, a MOSFET gate and a MOSFET drain. The MOSFET drain is connected to the HEMT source, and the MOSFET source includes a MOSFET source clip. The MOSFET source clip includes a pillar so to connect the MOSFET source to the HEMT gate, and the connection between the MOSFET source to the HEMT gate is established by a conductive material.

Abstract: The present disclosure relates to a bi-directional bus repeater. The present disclosure further relates to a communication bus including a bi-directional bus repeater, and to a communication system including the communication bus. The bi-directional bus repeater includes a first input terminal, a second input terminal, a first pulldown element connected to the first input terminal, and a second pulldown element connected to the second input terminal. By ensuring that the activation of the first and second pulldown elements is dependent on the state of the corresponding input terminal and the detection of a high-to-low transition of the corresponding other input terminal, the problem of self-locking can be avoided or at least minimized.

Abstract: A semiconductor power device includes an active region that has a drift region of a first conductivity type and a body region of a second, opposite conductivity type. A super junction region is arranged at least partially between the drift region and the body region. The super junction region has a first pillar of the first conductivity type and at least a portion of a second pillar of the second conductivity type. The first pillar is arranged adjacent to the portion of the second pillar. At least one of: a doping concentration of the first pillar is constant and a doping concentration of the portion of the second pillar decreases, or the doping concentration of the first pillar increases and the doping concentration of the portion of the second pillar is constant.

Abstract: A semiconductor device has a first surface contact provided on a first surface of the semiconductor device, a second surface contact provided on the first surface, physically separated from the first surface contact, a third surface contact provided on the first surface between the first surface contact and second surface contact and a first trench provided in the first surface and extending into the device from the first surface, and a conductive plug provided in the trench, The trench is located in an area of the first surface between an end of the third surface contact and an edge of the first surface. The first surface contact and the second surface contact overlie the first trench and the conductive plug in the first trench provides a conductive path between the first and second surface contacts.

Abstract: A semiconductor device includes a semiconductor layer with a first and second surface. The semiconductor layer includes: a source region and gate regions. The source region includes an N-type source region, a P-type body layer, and a carrier storage layer. Each gate region includes a gate oxide layer and polysilicon. The gate oxide layer surrounds a side wall and bottom of the polysilicon. The source region is arranged between adjacent gate regions and contacts the gate oxide layers. The gate oxide layer extends to a first depth. The bottom of the polysilicon is located at a second depth away from the first surface. A part of the gate oxide layer has a constant thickness in a transverse direction and another part gradually increases thickness in the transverse direction. The third depth is within a range of a depth where the first P-type body layer is located.

Abstract: The present disclosure relates to a semiconductor device and a method of manufacturing a semiconductor device and particularly to MOSFET transistors. A semiconductor device including a first-conductivity-type substrate, a first-conductivity-type epitaxy layer including a JFET region, two first well regions including two source regions, two second well regions, a scatter oxide layer, the first-conductivity-type substrate is adjacent to the first-conductivity-type epitaxy layer, the two first well regions are adjacent to the first-conductivity-type epitaxy layer and each of the two first well regions is adjacent to one second well region, the JFET region is adjacent to the two second well regions, the scatter oxide layer is adjacent to the two source regions, the two first well regions, the two second well region and the JFET region, and a width of the JFET region is greater near the scatter oxide layer than in part closest to the first-conductivity-type substrate.

Abstract: A semiconductor switching device implementing an edge termination structure is provided. The present disclosure provides an improved semiconductor switching device with an edge termination structure with an improved VBR and reliability.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes securing a die to a die paddle with solder and securing a clip to the die with solder to form a first subassembly. The method further includes heating the first subassembly to at least the melting temperature of the solder, then subsequently removing at least some of the solder from the die paddle in a region adjacent the die to expose the die paddle in that region. The method further includes moulding a casing on to the first subassembly so that the casing at least partly surrounds the die, the die paddle, and the clip.

Abstract: A controller of a synchronous rectifier of a synchronous flyback converter is presented. The synchronous rectifier includes a switch that is switchable by the controller. The controller includes an adaptive slew rate detection circuit that is configured to add a current to a base slew rate current depending on an off-time of the switch to obtain a slew rate current. The slew rate current determines a slew rate setting voltage. The controller is configured to turn on the switch of the synchronous rectifier depending on the slew rate setting voltage.

Abstract: The present disclosure relates to the field of semiconductor devices and to the edge termination of an active area of a semiconductor device. It is an object of the present disclosure to provide for a semiconductor device that has an improved termination area, and a corresponding method and power device.

Abstract: The present disclosure has a substrate for power semiconductor packaging and a package containing such a substrate. The substrate includes: a first metal layer for contacting with a semiconductor device, a second metal layer for contacting with a heat dissipation device, an electrical insulation layer disposed between the first metal layer and the second metal layer, and a first graphene bulk layer disposed between the electrical insulation layer and the first metal layer, a first surface of the first graphene bulk layer is in contact with a first surface of the first metal layer, and a second surface of the first graphene bulk layer opposite to the first surface is in contact with a first surface of the electrical insulation layer. Compared to the conventional substrate, the novel substrate of the present disclosure exhibits much lower thermal resistance, higher mechanical strength, and enhanced corrosion resistance.

Abstract: There is disclosed a semiconductor package for a PCB. The semiconductor package includes a die paddle, a die, a plurality of leads and an encapsulant. The die is coupled to the die paddle. The plurality of leads are electrically connected to the die. Each of the plurality of leads extend from the die at a first end and define a pad for attachment to the PCB at a second end. The encapsulant at least partly surrounds the die and the plurality of leads. The encapsulant defines a thickness. The one or more of the plurality of leads includes an exposed portion, the exposed portion being disposed partway along an extent of the lead between the first and second ends. The exposed portion is located partway along the thickness of the encapsulant.

Abstract: The present disclosure relates to a semiconductor device and a method of manufacturing semiconductor device. The present disclosure relates particularly to MOSFET transistors. A semiconductor device according to the disclosure including: a first-conductivity-type substrate, a first-conductivity-type epitaxy layer including a JFET region and a second-conductivity-type shield region, two well regions including two source regions, gate oxide including a gate, a drain adjacent to the first-conductivity-type substrate, the first-conductivity-type substrate is adjacent to the first-conductivity-type epitaxy layer, the two well regions are adjacent to the first-conductivity-type epitaxy layer, the JFET region is located between the two well regions, the source contact region is the outermost layer and is adjacent to the two source regions, and the gate oxide is adjacent to the two well regions, the two source regions, and the JFET region.

Abstract: There is provided a method of manufacturing a semiconductor die package. The method includes providing a leadframe having a sub-structure and at least one tie bar, the sub-structure includes a terminal-forming portion in electrical communication with the at least one tie bar. The method includes bonding a die to the sub-structure. The method includes encapsulating the sub-structure and the die within an encapsulation layer. The method includes performing a first cut through the terminal-forming portion and the encapsulation layer so as to form a side terminal, while leaving all tie bars substantially intact. The method includes electroplating the side terminal. The method includes performing a second cut through the tie bar and the encapsulation layer to singulate a semiconductor die package from the leadframe.

Abstract: An integrated circuit package is provided, including: a die having circuitry with one or more bond pads on a first surface of the die; a conductive supporting structure allowing connection to the die, the conductive supporting structure including a slot; and a passive component inserted into the slot of the conductive support structure, and a first terminal of the passive component is electrically connected to the conductive supporting structure and the circuitry of the die.

Abstract: There is disclosed a semiconductor package for a PCB. The semiconductor package includes a die paddle, a die, a connector, an anchor pad and an encapsulant. The die is coupled to the die paddle. The connector is coupled to the die, the connector including a plurality of leads for attachment to the PCB. The anchor pad is for attachment to the PCB. The encapsulant at least partly surrounds the die. The anchor pad extends across at least part of the die.

Abstract: There is disclosed a clip for a semi-conductor device. At least part of the clip is formed from a metallic foam.

Abstract: The present disclosure presents a semiconductor device including a semiconductor body, and the semiconductor body includes one or more recessed regions in a P doped Junction Termination Extension (JTE) region, and a depth of the recessed regions is smaller than a depth of the JTE region, and an N+ implant at a top surface of the JTE region, so that the N+ implant forms a part of mesa regions in between the recessed regions. A method of manufacturing such a semiconductor device is also presented.