Abstract: A method for producing a semiconductor package includes providing a lead frame and a bond pad with a space therebetween. The frame is provided with a die bonded thereon and a die pad. The die, the pad, a part of the frame, a part of the bond pad and the space between the frame and the bond pad are encapsulated. Part of the first encapsulation is removed to create a cavity having a bottom surface including an exposed surface of the die, an exposed surface of the pad, an exposed surface of the bond pad and a connecting region between the exposed surface of the pad and the bond pad. The cavity is partly filled with an electrically conductive paste. The electrically conductive paste is cured to obtain an interconnect between the die pad and the bond pad. The interconnect is encapsulated.

Abstract: A Metal Oxide Semiconductor (MOS), Field Effect Transistor (FET), (MOSFET) is provided, including a semiconductor body having a first major surface, and two trenches extending in the semiconductor body from the first major surface, a source region of a first conductivity type adjacent sidewalls of the two trenches at the first major surface, a drain region of the first conductivity type adjacent the two trenches at a position distant from the source region, a channel-accommodating region, of a second conductivity type opposite to the first conductivity type, adjacent the sidewalls of the two trenches between the source region and the drain region, and a first of the two trenches extends further into the semiconductor body compared to a second of the two trenches.

Abstract: A semiconductor device and a manufacturing method thereof is provided. The device includes a semiconductor layer having a first and second surface opposing each other; a trench gate in the semiconductor layer, extends in a first direction parallel to the first and second surface, and from the first surface to an interior of the layer, and has a gate open end distant from the second surface; a source region of a first conductivity type and a channel region of a second conductivity type, orthographic projections of the source region and the channel region on the second surface at least partially overlap with each other in a depth direction of the trench gate, the source region having a source open end distant from the second surface, and the farther the source open end is from the second surface, the smaller a width of the source open end in the second direction.

Abstract: A cross-coupled latch charge pump is provided, including a first inverter, a second inverter, and an output of the first inverter is connected to an input of the second inverter and an output of the second inverter is connected to an input of the first inverter. The first supply terminals of both the first and second inverter are connected to an output capacitor and second supply terminals for both the first and second inverter are connected to a reference voltage, a first fly capacitor, a second fly capacitor, and a first plate of the second fly capacitor is arranged for receiving a second clock signal, and a second plate of the second fly capacitor is connected to the input of the second inverter. The cross-coupled latch charge pump includes a transistor connected between the reference voltage and the second supply terminals.

Abstract: A parallel multiple-port system is provided, including a plurality of ports, a plurality of processors, and a memory storing software code which, when executed by the plurality of processors causes the processors to control the plurality of ports. A first processor is configured to control a first port. A second processor is configured to control a second port. The software code includes a common software code portion relevant to the plurality of ports and for execution by the plurality of processors. The software code further includes a port specific code portion including first configuration data for the first port and for execution by the first processor, and second configuration data for the second port and for execution by the second processor. The present application can advantageously be applied to parallel multi-port charging systems.

Abstract: An apparatus for transferring a semiconductor die from an arrangement dies to a target is provided and relates to a wafer stage, and film frame carrier, and to an assembly including the film frame carrier and arrangement of dies. The wafer chuck includes a rotationally mounted curved shell on which the arrangement of semiconductor dies can be arranged. The wafer stage includes a motor for rotating the curved shell around a rotational axis. The configuration allows improved throughput of the wafer stage. The carrier used with this wafer stage includes a ring-shaped body with an asymmetric bending stiffness allowing the ring-shaped body to be bent so that the mounting surface of the ring-shaped body changes from a first shape to a second more concave shape and prevents or limits the ring-shaped body to be bent so that the mounting surface becomes more convex than the first shape.

Abstract: A reference voltage generating circuit is provided, including a first depletion type metal-oxide semiconductor field-effect transistor (MOSFET), a first enhancement type MOSFET, a reference voltage output connected between the first depletion type MOSFET and the first enhancement type MOSFET, and a second depletion type MOSFET.

Abstract: An electronic package and method for manufacturing is provided. The package includes an electronic component having a terminal, a solidified molding compound encapsulating the electronic component, a lead including an inner and a mounting portion. The molding compound includes a first recess at or near a perimeter of a bottom surface of the mounting portion, exposing a portion of a bottom surface of the inner portion arranged near the mounting portion, and/or a second recess at the perimeter of the bottom surface of the mounting portion, the second recess exposing a portion of a side surface of the mounting portion extending between the top and the bottom surface of the mounting portion. The package provides more exposed lead space for a larger solder covering area using the first and/or second recess. Thus, solder strain accumulation is reduced or mitigated, and reliability of the electronic package can be enhanced.

Abstract: A circuit for autonomous battery lifespan boosting, the circuit including a power source, an output, a current sensing module located on an electrical load path between the power source and the output, a direct current to direct current (DC-DC) converter, and a capacitor electronically connected to the DC-DC converter.

Abstract: The present disclosure relates to a power converter and to a buck DC-to-DC power converter, such as a constant-on-time (COT) Buck DC-to-DC power converter. Additionally, a COT Buck DC-to-DC converter is provided which has a seamless transition between the normal operation mode and the 100% duty operation mode.

Abstract: The present disclosure relates to a lead-frame substrate designed to provide the semiconductor die element with electronic connection to the environment and provide a path of thermal conduction. The disclosure provides for a substrate, in particular a lead-frame substrate used in a semiconductor package for mounting a semiconductor die element, which allows for an increased thermal and electrical performance compared to conventional cladded-lead frame substrate designs. The disclosure further provides for a method of manufacturing thereof.

Abstract: A method of manufacturing a semiconductor package assembly and a semiconductor package is provided, with integral electrically conductive layers seeded on the first die side and on the part of the at least one lead frame terminal.

Abstract: A continuous time comparator including a first Field Effect Transistor, (FET) for receiving a first input signal, and a second FET for receiving a second signal, a first branch includes a first transistor and a second branch includes a second transistor, the first branch is connected to the first FET and the second branch is connected to the second FET, a first dynamic clamp circuitry connected in parallel over the first branch, the first dynamic clamp circuitry, dynamically clamps a voltage at a gate of a first output transistor, and a second dynamic clamp circuitry connected in parallel over the second branch, the second dynamic clamp circuitry, dynamically clamps a voltage at a gate of a second output transistor, the first and second output transistors provide an output of the comparator and for an inverting output of the comparator.

Abstract: A reference voltage generating circuit is provided, including a first depletion type metal-oxide semiconductor field-effect transistor (MOSFET), a first enhancement type MOSFET, a reference voltage output connected between the first depletion type MOSFET and the first enhancement type MOSFET, and a second depletion type MOSFET.

Abstract: A lateral oriented transistor embodied in a semiconductor material, including a first group of directly adjacently placed transistor cells, a second group of directly adjacently placed transistor cells, the second group is spaced apart from the first group thereby providing a spacing, each of the transistor cells includes a drain, a source and a gate, and the lateral oriented transistor further includes a gate interconnect placed in the spacing between the first and second group, and the gate interconnect connects to the gates of the transistor cells.

Abstract: An electrostatic discharge protection device is provided. The present device relates to a semiconductor device that is particularly suitable as a component for electrostatic discharge protection. The semiconductor device comprises a first structure, including: a third semiconductor region of the second charge type, a fourth semiconductor region of the first charge type and being spaced apart from the third semiconductor region, and a first connection element configured to electrically connect the third semiconductor region to the fourth semiconductor region. The third semiconductor region is arranged in between the first semiconductor region and the fourth semiconductor region, and the fourth semiconductor region is arranged in between the second semiconductor region and the third semiconductor region.

Abstract: A method of testing a semiconductor device, in a package, having a junction between a semiconductor material of a first type and a semiconductor material of a second type. The junction has a temperature dependent breakdown voltage, and the method includes the steps of determining the breakdown voltage, providing a fixed voltage over the junction, via pins of the package, and the fixed voltage is higher than the breakdown voltage, and measuring, via pins of the package, a breakdown current flowing through the junction, determining a dissipated power based on the fixed voltage and the measured breakdown current, and the dissipated power is a qualitive measure for the semiconductor device.

Abstract: A module for electric circuitry having lower parasitic inductance is provided. The module for an electric circuit includes a substrate having circuitry containing a Direct Current (DC) pad and an Alternating Current (AC) pad. A first group of semiconductor dies is mounted on the AC pad, and a second group is mounted on the DC pad. Furthermore, the module includes a first DC terminal electrically connected to the first group, a second DC terminal electrically isolated from the first DC terminal and electrically connected to the DC pad of the circuitry, and an AC terminal at least connected to the AC pad of the circuitry. The module has connecting means to electrically connect the first group to the AC pad, second connecting means to electrically connect the second group to the DC pad, and third connecting means to electrically connect the second group to the AC pad.

Abstract: The present disclosure provides a semiconductor package including: a semiconductor die attached to a lead frame having lead terminals; at least one bond clip connecting the die to a lead terminal; a die top solder connecting the bond clip and the die, and an encapsulant. The clip includes a die attachment portion having a die attachment portion side structured to be connected to the die, the side is provided with a cavity functioning as an expansion space for the die top solder. This enables preventing the molten die top solder from spreading toward die edge and lead terminals, since the molten solder flow is directed inward to the cavity, instead of flowing outward. A bond clip for use in a semiconductor package is also provided, including a cavity functioning as an expansion space for the die top solder.

Abstract: The present disclosure relates to a semiconductor device and a method of manufacturing the semiconductor device. In particular, the disclosure relates to a semiconductor power packaging including the semiconductor device. It is a goal of the present disclosure to provide a method for manufacturing a semiconductor device without an insulation layer as a support layer for semiconductor dies thereby enhancing thermal and electrical performance as well as such a semiconductor device.