Abstract: A module for an electric circuit and method of fabricating the module in which the module includes a substrate including electric circuitry, and a Direct Current (DC) power package arranged for providing DC power to the electric circuitry by being electrically connected to the substrate, the DC power package includes a first DC terminal and a second DC terminal, the second DC terminal being electrically isolated from the first DC terminal, the first DC terminal includes two planar electrical conductors and the second DC terminal includes one planar electrical conductor. The two planar electrical conductors of the first DC terminal and the one planar electrical conductor of the second DC terminal are planarly stacked with gaps between them, so that the one planar electrical conductor of the second DC terminal is sandwiched between the two planar electrical conductors of the first DC terminal reducing stray inductance in the module.

Abstract: A semiconductor package and a method of manufacturing such a semiconductor package is provided. The semiconductor package includes a first terminal exposed on a back surface of the semiconductor package, one or more further terminals extending outside the semiconductor package, and a second terminal exposed on a top surface of the semiconductor package. The second terminal includes a slug acting as the second terminal. The slug is electrically attached to the first terminal via one or more bended ends of the slug. The slug includes one or more stress relief features.

Abstract: The present disclosure provides a semiconductor electrostatic discharge (ESD), protection device, and relates to electrostatic discharge protection circuit. The semiconductor device includes a substrate of a first charge type, an epitaxial layer of a second type, an electrical insulation, a first contact region of the first charge type, and at least one second contact region of the second type, the epitaxial layer is arranged on the substrate, the electrical insulation extends from an outer surface of the epitaxial layer toward the substrate so that it creates a plurality of sectors where a current from each one of the sectors must flow toward any other sector through the substrate, and the first contact region and the at least one second contact region are formed on the outer surface of the epitaxial layer so that each of the first contact region and at least one second contact region are in different sectors.

Abstract: The present disclosure relates to a chip for a semi-conductor device. The present disclosure also relates to a method for manufacturing a chip for a semi-conductor device.

Abstract: An electronic device is provided, including: a terminal configured for receiving a bandgap voltage reference, generated by incorporating a first base-emitter voltage subject to process variation; the electronic device including a first transistor with a base configured to be exposed to the bandgap voltage reference; the first transistor is biased with a constant collector current corresponding with the first base-emitter voltage, and is configured for providing a shifted voltage, VE, based on decreasing the bandgap voltage reference by a second base-emitter voltage subject to the process variation; and the electronic device including a second transistor, of the same type as the first transistor, including an emitter configured to be exposed to the shifted voltage; and the second transistor is biased with a constant base current and is configured for providing a restored bandgap voltage based on increasing the shifted voltage by a third base-emitter voltage.

Abstract: An inductor-less power converter for converting an input voltage at an input terminal to an output voltage at an output terminal is provided, with a conversion ratio between the input and output voltage. The converter can be an inductor-less power converter which is configured for Direct Current, DC, to DC, DC-DC conversion of an input voltage to an output voltage. The input voltage is provided at an input terminal pair whereas the output voltage is provided at an output terminal pair. The ratio between the input voltage and the output voltage defines the conversion ratio, which may be either larger than one or smaller than one, meaning that the voltage may be stepped-up or stepped-down and thus increased or lowered.

Abstract: A semiconductor device including a lead frame, a die attached to the lead frame using a first solder, and a clip attached to the die using a second solder is provided. The clip includes a notch arranged for a check of the excess of the second solder.

Abstract: A semiconductor device has one or more substrate layers, one or more epitaxy layers positioned above the one or more substrate layers, and a buffer layer directly in between the one or more substrate layers and the one or more epitaxy layers. The substrate layer can be a high-doped Arsenic layer. The epitaxy layer can be low-doped. The buffer layer can be a highly Phosphorous-doped Silicon layer. The buffer layer can be relatively thin, about 1 ?m to 5 ?m. A method includes providing a substrate layer, creating a buffer layer on top of the substrate layer; and creating an epitaxy layer on top of the buffer layer.

Abstract: A semiconductor device has trenches formed in a semiconductor substrate. The trenches have a plurality of ESD protection devices formed by PN or NP junctions between respective first doped regions (e.g., a P-doped region) and second doped regions (e.g., an N-doped region). The ESD protection devices are connected in series across the trenches by connection electrodes, which connect the trenches at corresponding points. The two outer trenches comprise ESD protection devices that are connected in parallel to first and second metal layers. The first and second metal layers between which the ESD protection devices are connected can be source and gate metal layers. An ESD event causes current to flow through the ESD protection devices.

Abstract: A clip for use with a power stage device has a first portion defining a first planar surface and a second portion connected to the first portion. The second portion has a second planar surface, a cavity defined in the second planar surface, and at least one notch in a perimeter of the second planar surface. The at least one notch extends into the cavity. A power driver device can include such a clip. A method of forming a clip for use with a power stage device includes providing a frame that has a first planar portion and a second planar portion connected to the first planar portion; stamping a cavity into the second planar portion; and providing at least one notch into a perimeter of the second portion that extends into the cavity.

Abstract: A semiconductor power device has a semiconductor body including a semiconductor substrate and an epitaxial layer formed on the semiconductor substrate. An active area and a termination area adjacent the active area are arranged in the epitaxial layer. The termination area has a plurality of first rings of a first polarity and a plurality of second rings of a second polarity different from the first polarity. The semiconductor substrate and the epitaxial layer are of the second polarity. A dopant concentration in the epitaxial layer associated with the second polarity is smaller than a dopant concentration in the second rings associated with the second polarity. The termination area has a first portion directly adjacent to the active area and a second portion spaced apart from the active area by the first portion. The plurality of first rings and second rings are arranged in the second portion.

Abstract: The present disclosure relates to a trench metal-oxide-semiconductor field-effect transistor, trench MOSFET, and to a method for manufacturing such transistors. In particular, the present disclosure relates to trench MOSFETs having deep trenches adjacent to the more shallow gate defining trench for obtaining a RESURF effect. According to the present disclosure, an ion implantation region of a charge type similar to that of the drift region is formed in the drift region. The ion implantation region extends below the deep trenches of the trench MOSFET and is vertically aligned with a base of the deep trenches.

Abstract: A lead frame for a semiconductor assembly includes a first columnar array of die paddles and a second columnar array of die paddles. The die paddles in the first columnar array are offset from the die paddles in the second columnar array. Each die paddle has a first pad and a second pad. The first pad is larger than the second pad. The first pads in the first columnar array are offset from the first pads in the second columnar array.

Abstract: A heat exchanger for a power module for an inverter system includes a body that defines an inlet and an outlet. At least one enclosed channel is integrally formed within the body. The at least one enclosed channel is in fluid communication with the inlet and the outlet. A power module for an inverter system includes a substrate, the heat exchanger, and a cover that at least partially covers the substrate and the heat exchanger.

Abstract: A semi-conductor device includes: a lead frame and one or more dies. The one or more dies are secured to the lead frame. The semi-conductor device further includes: a clip that is secured to at least one of the one or more dies, a first heat sink that is secured to or is formed as part of the clip, and a cover that at least partially encloses the lead frame, the one or more dies, and the clip. A major surface of the cover defines an aperture that extends to the first heat sink. The semi-conductor device further includes a first metallic layer that is secured to the first major surface of the cover by a bi-functional adhesive and a second heat sink that is coupled to the first metallic layer.

Abstract: An open base transistor has an emitter region of a first doping polarity, a collector region of the first doping polarity, a base region of a second polarity different from the first doping polarity, and an additional region of the first doping polarity. The base region is resistively connected to the additional region via a resistor.

Abstract: An I2C repeating unit has an A-side and a B-side terminal and is operable in a first mode for receiving a signal at the A-side terminal and producing a signal at the B-side terminal based on the A-side signal. The repeating unit further has a B-side rise time accelerator element and a controller unit configured to, in the first mode, control the B-side rise time accelerator element to pull up a voltage at the B-side terminal when the voltage at the A-side terminal surpasses a first threshold voltage during a rising edge of the voltage, and to subsequently control the B-side rise time accelerator element to stop pulling up the voltage at the B-side terminal when the voltage at the B-side terminal surpasses a second threshold voltage. The controller unit is further configured to disable the B-side rise time accelerator element when sending or receiving a handshake bit.

Abstract: A semiconductor package for a PCB includes: a die paddle; a die; a plurality of terminals, and an encapsulant. The die is coupled to the die paddle. The plurality of terminals are electrically connected to the die. The plurality of terminals include a first array of terminals, disposed along a first side of the semiconductor package, and a second array of terminals, disposed along a second side of the semiconductor package. The second side is opposite to the first side. Each of the plurality of terminals comprises a pad with a flank. The encapsulant at least partly surrounds the die. The recess is defined between each terminal of each of the first and second arrays of terminals.

Abstract: A semiconductor device includes: a substrate having a front and back surface. A main junction region, a terminal region and a field cut-off region are sequentially arranged in the substrate close to the front surface. A trench is formed in the terminal region near the field cut-off region, surrounded by field limiting rings. The junction depth of rings around the trench is greater than that of rings not surrounding it. By arranging trench structures in the terminal region, the depth of ion implantation can be increased, so that a larger junction depth can be formed subsequently. The larger junction depth can reduce a peak electric field strength on the surface; the peak electric field strength shifts from the surface to the inside of silicon; and the curvature radius of the terminal P-type implantation region is increased, thereby increasing the breakdown voltage of the terminal structure.

Abstract: The present disclosure relates to a switching device including a RC snubber network. The present disclosure further relates to a RC snubber network for a switching device. A switching device is provided that includes a trench transistor and an RC snubber network connected in between a first terminal and a second terminal of the trench transistor. The RC snubber network includes at least one current concentrating segment that is configured to locally force a major part of the snubber current passing through the trench capacitors to flow through a reduced number of trench capacitors to thereby increase the Ohmic losses associated with the snubber current.