Abstract: A frame module for a semiconductor integrated circuit (IC) including a substrate having the IC, a module to enclose the IC, a Direct Current (DC) supply terminal to provide DC power to the substrate, a DC return terminal to provide a return line for the DC power and an Alternating Current (AC) terminal to provide AC connections to the substrate, the DC supply terminal connects to the substrate at a first end, the DC return terminal connects to the substrate at a second end, the second end being opposite to the first, and the DC return terminal extends above the substrate towards the first end of the substrate, the DC return terminal has at least one opening, located at a part of the DC return terminal that extends above the substrate and the AC terminal connects to the substrate via at least one opening provided in the DC return terminal.

Abstract: The present disclosure relates to a pin used for a connection of an electronic device, such electronic device with the pin and the method of assembling such electronic device. The signal pin, which is suitable to be placed in a slot, includes a metal pin having a first end, a second end and a side surface, and a metal ribbon having a first end and a second end. The first end of the metal ribbon and the first end of the metal pin and/or the side surface of the metal pin form a galvanic connection.

Abstract: A semiconductor device is proposed, including a substrate, at least a first semiconductor die having a first die surface and a second die surface opposite to the first die surface, the at least one semiconductor die is mounted with the first die surface on the substrate, and at least one heat transfer component including a spatial configuration composed of a first component face and a second component face spaced apart from each other defining a spatial enclosure comprising a heat transfer medium, and the at least one heat transfer component is in heat exchanging contact with the second die surface and the substrate.

Abstract: A method for manufacturing a semiconductor package assembly, the method including the steps of: after a Die Attach Clip Attach (DACA) process on a semiconductor package, performing a flux cleaning treatment process and exposed surfaces of the semiconductor package are cleaned; performing a surface roughening treatment process and the exposed surfaces are roughened, the surface roughening treatment process is performed separately from the flux cleaning treatment process; and after performing the surface roughening treatment process, encapsulating the semiconductor package with a molding resin, thereby forming the encapsulated semiconductor package assembly.

Abstract: A vertical semiconductor component including: a substrate; an epitaxial layer doped with a first conductivity type, preferably n-doped, provided on the substrate; a metal layer deposited on the epitaxial layer to form a Schottky contact with the epitaxial layer; a plurality of first regions embedded in the epitaxial layer and contacting the metal layer, and doped with a second conductivity type, in order to form a plurality of pn-junctions with the epitaxial layer; and a plurality of second regions embedded in a first region and contacting the metal layer, and doped with a second conductivity type, at a higher concentration, in order to form a plurality of low-resistance ohmic contacts with the metal layer. The semiconductor component includes a lateral cross section along which there are more first regions than second regions.

Abstract: A current-controlled semiconductor system is provided, including a signal and a ground line, and a semiconductor controlled rectifier (SCR) device including a first SCR layer doped with a first type of charge carriers; a second SCR layer doped with a second type different from the first type; a third SCR layer doped with the first type; a fourth SCR layer doped with the second type; an input terminal connected with the first SCR layer and the signal line and an output terminal connected with the fourth SCR layer and ground line; at least a first SCR junction element connected with the second SCR layer and the signal line, and/or a second SCR junction element connected with the third SCR layer and the ground line, the system includes at least one current trigger device connecting the signal line with the third SCR layer or the ground line with second SCR layer.

Abstract: This disclosure relates to an adhesive dispense unit for a semiconductor die bonding apparatus. The adhesive dispense unit includes an adhesive dispense nozzle and a pin member; the pin member comprising a down stand portion and a sheath portion, and the down stand is reciprocatable within the sheath portion.

Abstract: Aspects of the present disclosure relate to a semiconductor power device, in particular to a Silicon Carbide, SiC, Merged P-I-N Schottky (MPS) diode. The device includes an active area and a termination area adjacent the active area. The termination area includes first rings having a first polarity. By including second rings having a second polarity opposite to the first polarity, a reduced effect of interface charges on the performance of the semiconductor power device can be observed.

Abstract: Aspects of the present disclosure relate to a pick-and-place apparatus that is configured to cause components to be placed on a substrate in a number of passes, and during each pass, components among a plurality of components are placed on the substrate in a respective placement pattern among a collection of interleaved placement patterns.

Abstract: An electrostatic discharge protection device is provided. In particular, the present disclosure relates to a semiconductor device that is particularly useful for ESD protection purposes. The semiconductor device further includes a second electronic component integrated on the semiconductor body and being spaced apart from the first electronic component, the second electronic component includes a first secondary region of the first charge type and a second secondary region of the second charge type arranged adjacent to the first secondary region, and the second secondary region is electrically connected to the second device terminal; and a first capacitive element, a first terminal thereof being electrically connected to the second primary region, and a second terminal thereof being electrically connected to the first secondary region.

Abstract: A semiconductor device is provided that includes a lead frame, a die attached to the lead frame using a first solder, a clip attached to the die using a second solder, and a copper slug attached to the clip. First gull wing leads are attached to the leadframe for a drain connection of the semiconductor device. Second gull wing leads are attached to the clip for a gate connection and for a source connection of the semiconductor device.

Abstract: A trigger circuit for controlling a electrostatic discharge (ESD), protection switch is provided. The present disclosure further relates to a high-voltage trigger circuit for use in eFuse (electronic fuse), load switch or ideal diode applications, or in any other application with a large n-channel FET between two pins. The trigger circuit ensures that the ESD protection gate can be left floating after the ESD event.

Abstract: An insulated-gate bipolar transistor device is provided including: a first region doped with a first type of charge carriers; a second region doped with a second type of charge carriers different from the first type; a third region doped with the first type; a fourth region doped with the second type; a first, emitter terminal electrically connected with the first region and a second, collector terminal electrically connected with the third region and the fourth region; and a gate structure disposed on the third region with one end adjacent to the second region and with another end adjacent the fourth region; as well as a diode structure having a first diode structure terminal electrically connected with the collector terminal and a second diode structure terminal electrically connected with the gate terminal of the gate structure; and the diode structure is a paired with a antiparallel diode.

Abstract: A semiconductor device is provided including: an epitaxial layer doped with a first type of charge carrier; at least one junction termination extension (JTE), embedded in the epitaxial layer so that an upper surface of the JTE is flush with an upper surface of the epitaxial layer, the JTE is doped with a second type of charge carrier different from the first type and at a higher doping concentration than the concentration of the epitaxial layer; a passivation layer containing a sufficient quantity of the second type of charge carrier disposed on a part of an upper surface of the JTE, so that the passivation layer is arranged to induce a surface charge density greater than 5E11 cm?2 of the second type of charge on the part of the upper surface of the JTE, by depleting an interior area of the JTE of free charge carriers of the second type.

Abstract: A carrier for laser die transfer of semiconductor dies to a wafer and a pick-and-place apparatus is provided. The carrier includes an optically transparent secondary support layer, an optically transparent primary support layer attached to the secondary support layer, the primary support layer including regions of an optically transparent first material, and a dynamic release layer attached to the primary support layer, the dynamic release layer contacts the regions of a first material. The dynamic release layer is configured to be coupled to semiconductor dies, and to release semiconductor dies among the semiconductor dies when a region of the dynamic release layer directly adjacent to the semiconductor dies is illuminated using laser light. The secondary support layer has a material composition different from the first material for reducing a flow of heat away from the primary support layer during the laser die transfer process.

Abstract: The present disclosure proposes an encapsulated semiconductor package and a method of manufacturing such a encapsulated semiconductor package, the semiconductor package includes at least one lead terminal having an exposed lead end extending from the encapsulated semiconductor package, the exposed lead end includes a free lead end surface, the free lead end surface at least one notch, and the free lead end surface and the notch are plated with a plating material.

Abstract: A package structure for a power semiconductor device is provided, including: a substrate; two or more semiconductor dies on the substrate, each of the semiconductor dies includes a first power switching pad, a second power switching pad and a gate; a gate control conductive trace, a first power switching contact and a second power switching contact are further arranged on the substrate, the gate control conductive trace is connected to each of the semiconductor dies via a bonding component, and the bonding component connecting a first semiconductor die to the gate control conductive trace is sandwiched between circuit lines formed by connecting the second power switching pads of the first semiconductor die and the neighboring second semiconductor die, to second power switching contact of the substrate.

Abstract: A pass gate circuit arranged for providing an input to an output based on a control signal, the pass gate circuit including a pass gate switch circuit including a P-Metal Oxide Semiconductors (PMOS) Field Effect Transistor (FE), PMOS FET, cascaded in parallel with an NMOS FET, the pass gate switch circuit is arranged to provide the input to the output, and includes a control circuit including two in series cascaded inverters, an output of a first of the two inverters is provided to a gate of the PMOS FET and an output of a second of the two inverters is provided to a gate of the NMOS FET, and the inverters are powered by a supply voltage.

Abstract: An MPS diode and a manufacturing method is provided. The diode includes a semiconductor body including an active area and an adjacent termination area, the active area includes a drift region of a first conductivity type, and a plurality of wells of a second type different from the first conductivity type, the wells being mutually spaced apart, each well forming a respective PN-junction with the drift region. The diode further includes a metal layer assembly arranged on a surface of the semiconductor body and at least one metal layer, the metal layer assembly forming a plurality of Schottky contacts together with the drift region and a plurality of respective Ohmic contacts with the wells. The drift region includes a doped region surrounding each of the wells and having a higher dopant concentration than a remainder of the drift region, and the doped region is spaced apart from the termination area.

Abstract: A semiconductor device and method of manufacturing thereof is provided, including one or more mutually separated trench structures and semiconductor devices in which a first polysilicon body and a second polysilicon body are provided in the trenches, and the first and second polysilicon bodies can be individually biased. The method according to the present disclosure includes the step of performing a wet oxidation for oxidizing the first polysilicon body and the exposed upper surface of the sidewall for forming, within the active area, a first part of a second dielectric layer and subsequently performing a dry oxidation for forming a remaining part of the second dielectric layer. A second polysilicon body is arranged next within the active area on the second dielectric layer in the trench so that the second polysilicon body is separated from the sidewall of the trench and from the first polysilicon body by the second dielectric layer.