Abstract: A semiconductor power device and a method for manufacturing the same is provided. The semiconductor power device includes a semiconductor body including a conductive substrate and an epitaxial layer of a first charge type grown on the conductive substrate, and one or more inner wells of a second charge type different from the first charge type in an active area of the semiconductor power device. At least some of the one or more inner wells of the second charge type are formed using at least two ion implantation steps. One step is dedicated to forming the inner wells of the second type whereas one or more further ion implantation steps are simultaneously used for forming a respective JTE structure and for increasing a dopant concentration of at least one well of the second charge type.

Abstract: A semiconductor device is provided, including: a lead frame, a semiconductor chip, a mold, and an adhesion promoter. The lead frame includes a first surface and a second frame surface opposite the first surface, and the chip includes a first and a second surface opposite the first surface, the first frame surface is an outer surface of the device, with the second frame surface attached to the first chip surface so that the second frame surface is partially covered by the first chip surface. An uncovered surface part of the second frame surface and the second chip side are in contact with the mold by the adhesion promoter, that is on the uncovered surface part of the second frame surface and/or on the second chip surface. The adhesion promoter enhances adhesion between the mold, and either the second frame surface or the second chip surface of the chip.

Abstract: A semiconductor package assembly and molding resin case is provided. The package includes a lead frame having a first and a second lead frame side opposite to the first; a semiconductor die structure having a first and a second die side opposite to the first, the die structure being mounted with its second die side on the first lead frame side, resulting in a first connection; a bond element connected to the first die of the die structure, resulting in another connection; with the molding resin case encapsulating at least the die structure, the lead frame and a first part of at least one bond element connected to the die structure, leaving the second lead frame side and the at least one bond element partly exposed; and at least one bond element is provided with electric field modulation structures configured to alter an electric field created between the connections.

Abstract: The present disclosure generally relates to a four-layer semiconductor device, such as a silicon-controlled rectifier. Further aspects of the present disclosure relate to an electrostatic discharge (ESD), protection circuit including the same. In the four-layer semiconductor device in accordance with the present disclosure, an electrical insulation is provided that extends at least partially inside the epitaxial layer and that prevents a current from flowing between the first device terminal and the second device terminal that does not at least partially flow through the semiconductor substrate.

Abstract: The disclosure relates to an Electrostatic Discharge (ESD) protection semiconductor device for providing ESD protection between a first and a second terminal of another semiconductor device, the ESD protection device includes a semiconductor body having a first major surface, the semiconductor device further includes a first ESD terminal arranged to be connected to a first terminal of the other semiconductor device, a second ESD terminal arranged to be connected to a second terminal of the other semiconductor device, and a floating terminal.

Abstract: A method of manufacturing a semiconductor package is provided, with an integrated heatsink and electrical connection feature. The semiconductor die can be attached to the terminal using eutectic bonding, preferably CuSn eutectic, Ag containing adhesives or Ag sintering material. These bondings are lead (Pb) free connection methods, which make the finished semiconductor package RoHS compliant (restriction of hazardous materials).

Abstract: According to an aspect of the present disclosure, an electrical power converter unit for converting Direct Current to Direct Current (DC-DC) is provided. Specifically, an improved electrical power converter unit for converting DC-DC is provided which applies a MPPT mechanism which is both efficient and allows flexibility in use.

Abstract: The present disclosure relates to a method of singulation of dies from a wafer, the wafer includes a semiconductor layer and a coating applied to the backside of the wafer after backgrinding, and the coating includes at least one metallization layer, the dies being separated along saw streets running in multiple directions. The method includes the steps of: dicing the wafer along the saw streets from a topside of the wafer; and the dicing is performed through plasma dicing for a dicing depth corresponding to the interface between the semiconductor layer and the coating. The method further includes the step of: etching the wafer in accordance with an etch mask corresponding to the saw streets, for each of the remaining metallization layers in the coating, and for singulating the dies from the wafer.

Abstract: The present disclosure relates to a method of improving semiconductor package creepage. The package includes a semiconductor device, and a plurality of electrically conductive contacts at a surface of the package, the package includes insulating material for electrically insulating the package between the plurality of electrically conductive contacts and an initial creepage distance is defined by the shortest distance over the surface of the package between two of the plurality of contacts, and the method includes the steps of: applying a layer of insulating material over at least part of at least one of the two contacts, the insulating material is applied in a thin layer and selected to obtain a package thermal resistance increase less than a factor 3 as compared to an uncoated semiconductor package, to increase the initial creepage distance and improve package creepage of the semiconductor package.

Abstract: A method of forming a semiconductor device includes: disposing an isolation oxide layer and a shield polysilicon in trenches formed in a substrate, with the shield polysilicon being partially surrounded by the isolation oxide layer; etching the isolation oxide layer; disposing an inter-poly oxide (IPO) layer on an upper surface of the shield polysilicon with the IPO layer laterally surrounded in the trenches by the isolation oxide layer; etching the IPO layer and the isolation oxide layer; lining at least upper sidewalls of the trenches with a gate oxide layer; disposing a gate polysilicon on an upper surface of the IPO layer and on an upper surface of the isolation oxide layer, with the gate polysilicon laterally surrounded by the gate oxide layer; etching the isolation oxide layer so that a thickness of the isolation oxide layer tapers from the shield polysilicon a top opening of the trench.

Abstract: This disclosure relates to a discrete half bridge semiconductor device including a first cascode arrangement and a second cascode arrangement. Each of the first cascode and second cascode arrangements include a high voltage FET device die and a low voltage FET device die; and the source of the high voltage FET device die is mounted on and connected to a drain of the low voltage FET device die. The source of the low voltage FET device die and gate of the high voltage FET device die are connected to a drain terminal of the high voltage FET device die of the second cascode arrangement at a common connection pad.

Abstract: Aspects of the present disclosure relate to a semiconductor power device, in particular to a Silicon Carbide, SiC, Merged P-I-N Schottky (MPS) diode. The device includes an active area and a termination area adjacent the active area. The termination area includes first rings having a first polarity. By including second rings having a second polarity opposite to the first polarity, a reduced effect of interface charges on the performance of the semiconductor power device can be observed.

Abstract: A lead frame for connecting a semiconductor die to a base plate is provided. The lead frame includes: one or more lead portions, configured for connecting the lead frame to the base plate; a first contact element configured to be connected to a source of the semiconductor die; and a second contact element configured to be connected to a drain of the semiconductor die, the second contact element includes at least two contact portions that in an assembled state of the lead frame each contact the drain of the semiconductor die with a contact area thereof, the contact areas of the respective contact portions are spaced apart from each other.

Abstract: An MPS diode and a manufacturing method thereof is provided. The MPS diode includes a semiconductor body with an active area, that includes a drift region of a first conductivity type, and wells of a second type different from the first type, the wells being mutually spaced apart, each well forming a respective PN-junction with the drift region. The MPS diode includes a metal layer assembly arranged on a surface of the semiconductor body and at least one metal layer, the assembly forming Schottky contacts together with the drift region and the respective Ohmic contacts with the wells. The drift region includes a doped region surrounding the wells, the doped region having a higher dopant concentration than a remainder of the drift region. The dopant concentration in the doped region decreases in a first direction from a center of the doped region to an edge of the doped region.

Abstract: Aspects of the present disclosure generally relate to an MPS diode and a manufacturing method therefor. The MPS diode includes a semiconductor body including an active area, the active area includes a drift region of a first conductivity type, and a plurality of wells of a second conductivity type different from the first conductivity type, the plurality of wells being mutually spaced apart, each well forming a respective PN-junction with the drift region. The MPS diode further includes a metal layer assembly arranged on a surface of the semiconductor body and at least one metal layer, the metal layer assembly forming a plurality of Schottky contacts together with the drift region and a plurality of respective Ohmic contacts with the plurality of wells. A spacing between adjacently arranged wells increases in an outward direction from a center of the active area.

Abstract: The disclosure provides a method for manufacturing a semiconductor package assembly, which results in a semiconductor package assembly with a more even distributed stress concentrations, reduced solder crack occurrences and limited solder filler joint connections.

Abstract: Aspects of the present disclosure generally relate to an MPS diode and a manufacturing method therefor. The MPS diode includes a semiconductor body including an active area, the active area includes a drift region of a first conductivity type, and a plurality of wells of a second conductivity type different from the first conductivity type, the plurality of wells being mutually spaced apart, each well forming a respective PN-junction with the drift region. The MPS diode further includes a metal layer assembly arranged on a surface of the semiconductor body and at least one metal layer, the metal layer assembly forming a plurality of Schottky contacts together with the drift region and a plurality of respective Ohmic contacts with the plurality of wells. A spacing between adjacently arranged wells increases in an outward direction from a center of the active area.

Abstract: An MPS diode and a manufacturing method is provided. The diode includes a semiconductor body including an active area and an adjacent termination area, the active area includes a drift region of a first conductivity type, and a plurality of wells of a second type different from the first conductivity type, the wells being mutually spaced apart, each well forming a respective PN-junction with the drift region. The diode further includes a metal layer assembly arranged on a surface of the semiconductor body and at least one metal layer, the metal layer assembly forming a plurality of Schottky contacts together with the drift region and a plurality of respective Ohmic contacts with the wells. The drift region includes a doped region surrounding each of the wells and having a higher dopant concentration than a remainder of the drift region, and the doped region is spaced apart from the termination area.

Abstract: The present disclosure relates to a cooling stage for cooling down a heated carrier on which a plurality of components has been mounted. Further aspects of the present disclosure relate to a pick-and-place apparatus that includes such a cooling stage and to a method for cooling down a heated carrier on which a plurality of components has been mounted. The cooling stage according to an aspect of the present disclosure uses supporting members for keeping the heated carrier separated from a cooling body. By relying on thermal convection between the heated carrier and the cooling body, dependency of the cooling stage on the type of carrier used is reduced compared to known cooling stages. For example, for different types of carries, it generally suffices to use different supporting members, e.g. having a different height, and/or to use a different temperature of the cooling body.

Abstract: The present disclosure proposes a semiconductor device including a silicon substrate; a channel positioned on the top surface of the substrate; a drift region positioned on the top of the channel; a trench; a first polysilicon layer positioned within the channel and the drift region on the bottom of the trench; a second polysilicon layer positioned on the top of the first polysilicon layer, and positioned within the drift region inside of the trench; a third polysilicon layer positioned on the top of the second polysilicon layer, and positioned within the drift region inside of the trench. The first polysilicon layer and the second polysilicon layer and the third polysilicon layer are isolated by a gate oxide and a RESURF oxide respectively, from the channel and from the drift and from each other forming at least partially three separated structures.