Patents Assigned to Nexperia B.V.
  • Publication number: 20230408556
    Abstract: A system for sensing a current through a transistor is provided and a DC-DC converter including one or more such systems. The system includes a transistor module, including: a primary transistor electrically connected between a first and a second terminal; and a secondary transistor electrically connected between the first and a third terminal, a control terminal of the secondary transistor is electrically connected to a control terminal of the primary transistor. The system includes a current sensing module electrically connected to the transistor module and having an output terminal. The system is operable in a first mode in which the current sensing module outputs, at the output terminal, a first output signal indicative of a current through the primary transistor in a first current direction based on a voltage difference between the third and the second terminal, the first current direction being from the first to the second terminal.
    Type: Application
    Filed: June 19, 2023
    Publication date: December 21, 2023
    Applicant: NEXPERIA B.V.
    Inventors: Yong Qu, Katarzyna Nowak, Joel Turchi
  • Publication number: 20230402351
    Abstract: According to the disclosure a semiconductor package assembly is proposed, at least including: a lead metallic frame; a semiconductor die structure being mounted on a die pad of the lead metallic frame; at least a first bond clip connected with the semiconductor die structure; at least a further bond clip connected with the die pad of the lead metallic frame via a solder junction; and the die pad is provided with at least one recess near the connection with the at least further bond clip for accommodating solder for the solder junction. The disclosure also pertains to a method for manufacturing such a semiconductor package assembly.
    Type: Application
    Filed: June 6, 2023
    Publication date: December 14, 2023
    Applicant: NEXPERIA B.V.
    Inventors: Ricardo Yandoc, Matthew Anthony, Zhou Zhou, Adam Brown
  • Publication number: 20230402308
    Abstract: Aspects of the present disclosure relate to a transfer device, system, and method for transferring an electronic component onto a placement position on a substrate. The transfer device is based on a fluidic process principle in which electronic components are transferred in a transfer liquid. In accordance with an aspect of the present disclosure, the transfer device further includes a plurality of acoustic transducers, and a controller for controlling the plurality of acoustic transducers. The controller is configured to control the plurality of acoustic transducers to create an acoustic trap in the transfer liquid for capturing an electronic component when it is released in the transfer liquid and to subsequently manipulate the position and/orientation of the acoustic trap for the purpose of positioning the electronic component at the placement position on the substrate.
    Type: Application
    Filed: June 6, 2023
    Publication date: December 14, 2023
    Applicant: NEXPERIA B.V.
    Inventors: Joep Stokkermans, Gijs van der Veen, Jasper Wesselingh, Raymond Rosmalen, Regnerus Hermannus Poelma
  • Publication number: 20230402541
    Abstract: A lateral oriented Metal-Oxide-Semiconductor device is provided, including a semiconductor body having a first surface, the body includes a first region having a first conductivity type; a trench extending from the first surface into the first region, the trench includes an insulating element and a conductive element, the insulating element is in between the conductive element and the first region, and the insulating element has a substantially uniform width; second and third regions having a second conductivity type, the second conductivity being different from the first conductivity type, the second and third regions extend from the first surface into the first region and are located on either side of, and adjacent to the trench, and are not in contact; and a further insulating region on the first surface includes openings for providing electrical contact to the second and third regions. A method of manufacturing the device is also provided.
    Type: Application
    Filed: June 6, 2023
    Publication date: December 14, 2023
    Applicant: NEXPERIA B.V.
    Inventors: Manoj Kumar, Kilian Ong
  • Publication number: 20230402302
    Abstract: Aspects of the present disclosure relate to a system for transporting an electronic component. Further aspects of the present disclosure relate to a method for transporting an electronic component. According to an aspect of the present disclosure a system for transporting an electronic component is provided that includes a carrier for carrying the electronic component, and a transducer system including a plurality of transducers, the transducer system being configured for generating a levitation field in which the carrier levitates. The system also includes an input unit for arranging the electronic component onto the carrier, and an output unit for receiving the electronic component from the carrier. A controller is used for controlling the transducer system to change the levitation field for the purpose of moving the carrier from the input unit to the output unit.
    Type: Application
    Filed: June 9, 2023
    Publication date: December 14, 2023
    Applicant: NEXPERIA B.V.
    Inventors: Joep Stokkermans, Raymond Rosmalen, Gijs van der Veen, Jasper Wesselingh
  • Publication number: 20230400503
    Abstract: A method of testing a semiconductor device, in a package, having a junction between a semiconductor material of a first type and a semiconductor material of a second type. The junction has a temperature dependent breakdown voltage, and the method includes the steps of determining the breakdown voltage, providing a fixed voltage over the junction, via pins of the package, and the fixed voltage is higher than the breakdown voltage, and measuring, via pins of the package, a breakdown current flowing through the junction, determining a dissipated power based on the fixed voltage and the measured breakdown current, and the dissipated power is a qualitive measure for the semiconductor device.
    Type: Application
    Filed: June 9, 2023
    Publication date: December 14, 2023
    Applicant: NEXPERIA B.V.
    Inventor: Magnus Siegfried RUMMEY
  • Publication number: 20230402355
    Abstract: An electronic package and a method for manufacturing the same is provided. The electronic package includes a first substrate, an electronic component arranged on and/or formed in the first substrate, a thermally conductive second substrate including a first portion and a second portion integrally connected to the first portion, and at least the first portion among the first and second portion is fixedly attached to the electronic component, and a package material arranged to encapsulate the electronic component and to at least partially encapsulate the first and second substrate, and the package material includes a recess formed therein that extends up to a surface of the first portion.
    Type: Application
    Filed: June 8, 2023
    Publication date: December 14, 2023
    Applicant: NEXPERIA B.V.
    Inventors: Wei Leong Tan, Wai Wai Lee, Hing Suan Cheam
  • Publication number: 20230402550
    Abstract: A vertical semiconductor component including: a substrate; an epitaxial layer doped with a first conductivity type, preferably n-doped, provided on the substrate; a metal layer deposited on the epitaxial layer to form a Schottky contact with the epitaxial layer; a plurality of first regions embedded in the epitaxial layer and contacting the metal layer, and doped with a second conductivity type, in order to form a plurality of pn-junctions with the epitaxial layer; and a plurality of second regions embedded in a first region and contacting the metal layer, and doped with a second conductivity type, at a higher concentration, in order to form a plurality of low-resistance ohmic contacts with the metal layer. The semiconductor component includes a lateral cross section along which there are more first regions than second regions.
    Type: Application
    Filed: June 9, 2023
    Publication date: December 14, 2023
    Applicant: NEXPERIA B.V.
    Inventors: Tim BÖTTCHER, Sönke HABENICHT, Romain ESTEVE
  • Publication number: 20230386869
    Abstract: This disclosure relates to an adhesive dispense unit for a semiconductor die bonding apparatus. The adhesive dispense unit includes an adhesive dispense nozzle and a pin member; the pin member comprising a down stand portion and a sheath portion, and the down stand is reciprocateable within the sheath portion.
    Type: Application
    Filed: August 11, 2023
    Publication date: November 30, 2023
    Applicant: NEXPERIA B.V.
    Inventors: Erik Eltink, Theo Ter Steeg
  • Publication number: 20230378950
    Abstract: A load switch and a power system are provided. The load switch includes a power input terminal, a power output terminal, a voltage-current conversion circuit, a capacitor and a comparator. The power input terminal is configured to receive an input voltage. The power output terminal is configured to provide an output voltage. The voltage-current conversion circuit includes a first input terminal, a second input terminal and a current difference output terminal. The first input terminal and the second input terminal are connected to the power output terminal and the power input terminal, respectively, and configured to receive the output voltage and the input voltage, respectively. A current difference characterizing a voltage difference between the output voltage and the input voltage is output at the current difference output terminal.
    Type: Application
    Filed: May 19, 2023
    Publication date: November 23, 2023
    Applicants: Nexperia Technology (Shanghai) Ltd., NEXPERIA B.V.
    Inventors: Menghan Sun, Jianhua Duan
  • Publication number: 20230369140
    Abstract: A method of creating a vertical semiconductor device, the method includes the steps of performing a LOCal Oxidation of Silicon, LOCOS, process in a vertical trench of a semiconductor material so that oxide material is formed inside the vertical trench, and ledges are formed by the oxide material, inside the vertical trench, as a result of the LOCOS process, so that a lower region of reduced lateral distance is formed between the oxide material, at a base of the trench, depositing the trench with polysilicon and etching the polysilicon downward up to the oxide material using interferometric end point detection, so that polysilicon remains in the lower region.
    Type: Application
    Filed: May 9, 2023
    Publication date: November 16, 2023
    Applicant: NEXPERIA B.V.
    Inventors: Steven Peake, MD Imran Siddiqui
  • Patent number: 11817360
    Abstract: A semiconductor device and a method of manufacturing a semiconductor device. The chip scale package semiconductor device comprises: a semiconductor die having a first major surface and an opposing second major surface, the semiconductor die comprising at least two terminals arranged on the second major surface; a carrier comprising a first major surface and an opposing second major surface, wherein the first major surface of the semiconductor die is mounted on the opposing second major surface of the carrier; and a molding material partially encapsulating the semiconductor die and the carrier, wherein the first major surface of the carrier extends and is exposed through molding material, and the at least two terminals are exposed through molding material on a second side of the device.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: November 14, 2023
    Assignee: Nexperia B.V.
    Inventors: Loh Choong Keat, Edward Then, Weng Khoon Mong
  • Publication number: 20230361172
    Abstract: A semiconductor device and a method for manufacturing the same is provided. The semiconductor device includes: a semiconductor body having a first surface and a second surface, the semiconductor body includes: a depletion region, a drift region having a first conductivity type, an island region having the first conductivity type, a buffer region having the first conductivity type, the drift region is more proximal to the first surface of the semiconductor body than the buffer region, the depletion region is located within the drift region, and the island region is located within the drift region, an ion concentration of the first conductivity type of the island region is higher than an ion concentration of the first conductivity type of the drift region.
    Type: Application
    Filed: May 2, 2023
    Publication date: November 9, 2023
    Applicants: Nexperia Technology (Shanghai) Ltd., NEXPERIA B.V.
    Inventors: Chunlin Zhu, Ke Jiang, Junli Xiang, Huiling Zuo, Xukun Zhang, Jinshan Shi, Yuan Fang
  • Publication number: 20230344342
    Abstract: An inductor-less power converter for converting an input voltage at an input terminal to an output voltage at an output terminal is provided, with a conversion ratio between the input and output voltage. The converter can be an inductor-less power converter which is configured for Direct Current, DC, to DC, DC-DC conversion of an input voltage to an output voltage. The input voltage is provided at an input terminal pair whereas the output voltage is provided at an output terminal pair. The ratio between the input voltage and the output voltage defines the conversion ratio, which may be either larger than one or smaller than one, meaning that the voltage may be stepped-up or stepped-down and thus increased or lowered.
    Type: Application
    Filed: April 20, 2023
    Publication date: October 26, 2023
    Applicant: NEXPERIA B.V.
    Inventor: Joram Pieter van der Velden
  • Publication number: 20230344270
    Abstract: The present disclosure relates to an energy harvesting system for converting a low-voltage input of an energy harvesting source into a Direct Current (DC) output voltage. The energy harvesting source is one of an energy harvesting source providing an Alternating Current (AC) output such as a piezoelectric energy harvesting source, and an energy harvesting source providing a DC output such as a photovoltaic energy harvesting source.
    Type: Application
    Filed: April 20, 2023
    Publication date: October 26, 2023
    Applicant: NEXPERIA B.V.
    Inventors: Joram Pieter van der Velden, Gustavo Campos Martins
  • Publication number: 20230335634
    Abstract: A trench-gate semiconductor device and a manufacturing method therefore is provided. The device includes one or more unit cells, each unit cell includes a trench a first oxide layer arranged on an upper portion of a side wall of the trench, the first oxide layer forming a gate oxide of the unit cell, and a second oxide layer arranged on a lower portion of the side wall and on a bottom of the trench.
    Type: Application
    Filed: April 13, 2023
    Publication date: October 19, 2023
    Applicant: NEXPERIA B.V.
    Inventors: MD Imran Siddiqui, Steven Peake
  • Publication number: 20230326835
    Abstract: Aspects of the present disclosure relate to a molded electronic package and a method for manufacturing the same. The molded electronic package includes a first substrate, a second substrate, an electronic component arranged on the first substrate, a spring member arranged between the second substrate and the electronic component, the spring member including a first contact portion being fixated relative to the second substrate, and a second contact portion physically contacting the electronic component, and a body of solidified molding compound configured to encapsulate the electronic component and the spring member and to mutually fixate the first substrate, the second substrate, the electronic component and the spring member. The second substrate and the spring member are electrically and/or thermally conductive.
    Type: Application
    Filed: April 11, 2023
    Publication date: October 12, 2023
    Applicant: NEXPERIA B.V.
    Inventors: Hing Suan Cheam, Wei Leong Tan, Ting Wei Chang
  • Publication number: 20230326836
    Abstract: Aspects of the present disclosure relate to a semiconductor device package and to a method for manufacturing the same. The semiconductor device package includes a semiconductor die having a circuit integrated thereon, a first clip including a first planar portion and one or more first leads extending from the first planar portion, the first planar portion including one or more first protrusions, and a second clip including a second planar portion and one or more second leads extending from the second planar portion, the second planar portion including a plurality of second protrusions. The first planar portion and the second planar portion each physically and electrically connected to a terminal of the circuit arranged on the semiconductor die. At least one of the one or more first protrusions extends in a space between a pair of second protrusions among the plurality of second protrusions.
    Type: Application
    Filed: April 11, 2023
    Publication date: October 12, 2023
    Applicant: NEXPERIA B.V.
    Inventors: Ricardo Yandoc, Matthew Anthony, Jorex Lumanog
  • Publication number: 20230328935
    Abstract: This disclosure provides a design method for a radiator of a vehicle power module. The design method includes: selecting a plurality of specific values from the possible value ranges of the first distance D1, the second distance D2 and the radius R, respectively, to form different combinations of the plurality of specific values, performing simulation calculations on the different combinations, and obtaining a temperature rise ?Tj and a pressure drop ?Pf corresponding to each combination to form a plurality of samples; through a response surface method, fitting explicit functions of the temperature rise ?Tj and the pressure drop ?Pf with the first distance D1, the second distance D2 and the radius R as dependent variables; and through a multi-objective optimization, determining the first distance D1, the second distance D2 and the radius R with an optimization objective that the temperature rise ?Tj and the pressure drop ?Pf are simultaneously minimized.
    Type: Application
    Filed: April 6, 2023
    Publication date: October 12, 2023
    Applicants: Nexperia Technology (Shanghai) Ltd., Chongqing University, NEXPERIA B.V.
    Inventors: Ke Jiang, Zheng Zeng, Chunlin Zhu, Jiawei Zhang, Richard Qian, Peng Sun, Minhui Ma, Yuxi Liang
  • Publication number: 20230326907
    Abstract: A package structure for a power semiconductor device is provided, including: a substrate; two or more semiconductor dies on the substrate, each of the semiconductor dies includes a first power switching pad, a second power switching pad and a gate; a gate control conductive trace, a first power switching contact and a second power switching contact are further arranged on the substrate, the gate control conductive trace is connected to each of the semiconductor dies via a bonding component, and the bonding component connecting a first semiconductor die to the gate control conductive trace is sandwiched between circuit lines formed by connecting the second power switching pads of the first semiconductor die and the neighboring second semiconductor die, to second power switching contact of the substrate.
    Type: Application
    Filed: April 6, 2023
    Publication date: October 12, 2023
    Applicants: Nexperia Technology (Shanghai) Ltd., NEXPERIA B.V.
    Inventors: Wei Gong, Chunlin Zhu, Ke Jiang