Abstract: An apparatus for transferring chips from a first position to at least a second position includes: a rotatable transfer assembly including at least two transfer heads, each head for picking up a chip in the first position, and positioning the chip in the at least second position through rotation of the transfer assembly about an axis of rotation; a transfer assembly actuator for driving the transfer assembly together with the at least two transfer heads about the axis; and at least a first transfer head actuator structured for actuating at least one transfer head in a radial direction relative to the axis, the at least first transfer head actuator being mounted to the rotatable transfer assembly actuator and including an actuator element coupled to the at least one transfer head, the actuator element structured to be actuated in the direction of the axis relative to the rotatable transfer assembly actuator.

Abstract: A vertical oriented semiconductor device is provided that includes a semiconductor body having a first major surface, the semiconductor body includes a first region of a first conductivity type, a second region of a second conductivity type, and the second region is adjacent the first region so that a junction is provided between the first region and the second region. The junction has a maximum distance to the first major surface, and the semiconductor device further includes a trench extending into the semiconductor body from the first major surface to an extension depth at least equal to the maximum distance. The trench includes a material arranged to provide electrical insulation to limit a lateral field termination distance associated with the junction.

Abstract: A semiconductor product, including: a base region doped with a first conductivity type; a plurality of stripe regions doped with a second conductivity type, provided on an upper surface of the base region, and the second conductivity type is different from the first conductivity type; a plurality of cell regions doped with the second conductivity type, provided on the upper surface of the base region; and a metal layer arranged on the upper surface of the base region, so that the metal layer defines a Schottky barrier with the base region and covers the plurality of stripe regions and the plurality of cell regions; and each cell region of a majority of the plurality of cell regions contacts at least one neighboring stripe region of the plurality of stripe regions and the stripe regions and the cell regions extend into the base region to different depths.

Abstract: This disclosure relates to an adhesive dispense unit for a semiconductor die bonding apparatus. The adhesive dispense unit includes an adhesive dispense nozzle and a pin member; the pin member comprising a down stand portion and a sheath portion, and the down stand is reciprocateable within the sheath portion.

Abstract: The disclosure relates to an apparatus for transferring a semiconductor die from an arrangement of semiconductor dies to a target and to a wafer stage to be used in such an apparatus. The wafer chuck includes a rotationally mounted curved shell on which the arrangement of semiconductor dies can be arranged, and the wafer stage includes a first motor for rotating the curved shell around a rotational axis. The curved configuration allows an improved throughput of the wafer stage. The film frame carrier used with this wafer stage comprises a ring-shaped body with an asymmetric bending stiffness allowing the ring-shaped body to be bent so that the mounting surface of the ring-shaped body changes from having a first shape to a second more concave shape and prevents or limits the ring-shaped body to be bent so that the shape of the mounting surface becomes more convex than the first shape.

Abstract: An apparatus for transferring a semiconductor die from an arrangement dies to a target is provided and relates to a wafer stage, and film frame carrier, and to an assembly including the film frame carrier and arrangement of dies. The wafer chuck includes a rotationally mounted curved shell on which the arrangement of semiconductor dies can be arranged. The wafer stage includes a motor for rotating the curved shell around a rotational axis. The configuration allows improved throughput of the wafer stage. The carrier used with this wafer stage includes a ring-shaped body with an asymmetric bending stiffness allowing the ring-shaped body to be bent so that the mounting surface of the ring-shaped body changes from a first shape to a second more concave shape and prevents or limits the ring-shaped body to be bent so that the mounting surface becomes more convex than the first shape.

Abstract: A surface mount semiconductor device and method of manufacture. A semiconductor die is mounted on a first support surface; a leadframe is attached to the semiconductor die, the leadframe comprising: an electrical lead having a first lead region connected to the semiconductor die; and a second lead region distal the first lead region, wherein the second lead region is connected to a second support surface; encapsulating the semiconductor die, first support surface and the first lead region; the second lead region is severed from the second support surface to expose a lead end; and the second lead region is electro-plated with a metallic material, such that the lead end is coated with said metallic material.

Abstract: A Metal Oxide Semiconductor (MOS), Field Effect Transistor (FET), (MOSFET) is provided, including a semiconductor body having a first major surface, and two trenches extending in the semiconductor body from the first major surface, a source region of a first conductivity type adjacent sidewalls of the two trenches at the first major surface, a drain region of the first conductivity type adjacent the two trenches at a position distant from the source region, a channel-accommodating region, of a second conductivity type opposite to the first conductivity type, adjacent the sidewalls of the two trenches between the source region and the drain region, and a first of the two trenches extends further into the semiconductor body compared to a second of the two trenches.

Abstract: A semiconductor device such as a chip-scale package is provided. Aspects of the present disclosure further relate to a method for manufacturing such a device. According to an aspect of the present disclosure, a semiconductor device is provided that includes a conformal coating arranged on its sidewalls and on the perimeter part of the semiconductor die of the semiconductor device. To prevent the conformal coating from covering unwanted areas, such as electrical terminals, a sacrificial layer is arranged prior to arranging the conformal coating. By removing the sacrificial layer, the conformal coating can be removed locally. The conformal coating covers the perimeter part of the semiconductor die by the semiconductor device, in which part a remainder of a sawing line or dicing street is provided.

Abstract: An electrostatic discharge (ESD), protection device is provided. In accordance with the present disclosure, an ESD protection device is provided that includes a series connection of a first unit having strong snapback and low series capacitance and a second high-voltage unit that displays a relatively high holding/trigger voltage to ensure latch up and improper triggering of the ESD protection device while at the same time providing high-voltage operation with low capacitive loading.

Abstract: A multi-finger high-electron mobility transistor and a method of manufacturing such a transistor, and an electronic device including such a transistor is provided. According to an aspect of the present disclosure, an etching step for reducing donor layer thickness and/or performing an ion implantation is used for locally reducing the 2DEG concentration.

Abstract: A silicon chip package structure, in particular a metal-oxide-semiconductor field-effect transistor (MOSFET) and method of manufacture is provided. The disclosure provides improvements to a Chip Silicon Package (CSP) structure by reducing the active area needed to be sacrificed to create a drain area.

Abstract: A semiconductor device package and a method for manufacturing the same is provided. The semiconductor device package includes a semiconductor die having an electronic component integrated thereon and having a die terminal that is electrically connected to the electronic component, a stress relief substrate fixedly and electrically connected to the die terminal, and a clip lead. The substrate is configured to provide an electrical short between the clip lead and the die terminal. The stress relief substrate may form an interface between the clip lead and the semiconductor die and can thereby reduce stress exerted on the semiconductor die by the clip lead.

Abstract: The disclosure provides a semiconductor package substrate made from non-metallic material having a first top surface, a second bottom surface opposite from the first surface, and at least one side surface, the substrate includes at least two pads positioned on the first surface and suitable for receiving an electronic element, an encapsulant material layer covering the first surface, at least two terminals positioned on the second surface and electrically connected to the pads, and a portion of at least one of the two terminals is exposed at the at least one side surface and structured as a wettable flank.

Abstract: The present disclosure relates to a technology of manufacturing electronic components, especially semiconductor components with an irregular shape. The present disclosure provides an improved alignment method and system which may be used in cases, where features on a top surface of the semiconductor component or device are not sufficient due to process limitations and where a bottom surface might also not show any alignment correlation with the top surface.

Abstract: This disclosure relates to a semiconductor device including a device with high clamping voltage (HVC device), and an OTS device. Such a semiconductor device provides very advantageous ESD protection. The semiconductor device can be realized in two ways: an OTS device and a device with high clamping voltage can be realized as discrete, independent devices that are combined in one semiconductor package, or an OTS device can be integrated into interconnect layers of a device with high clamping voltage by integration.

Abstract: An electronic package and a method for manufacturing is provided, having first and opposing second surfaces, and a circuit thereon, each of the first and second surfaces has a terminal connected to the circuit; a conductive element spaced apart from the die with top and a bottom surfaces; a body of molding compound encapsulating the die and the element, the body having a top side facing the first surface and a bottom side facing the second surface; a first package terminal at the top side connected to the terminal at the first surface, and a second package terminal at the top side connected to the top surface of the conductive element, the conductive element is formed from the first package terminal and the second package terminal; and a conductive layer connecting the bottom surface of the conductive element to the terminal arranged on the second surface of the die.

Abstract: A semiconductor device including an interconnect. The interconnect is arranged to transfer current from one terminal to another, and the interconnect includes a first layer including a plurality of interweaved fingers, and each of the interweaved fingers varies in width in a direction of propagation current thereby resulting in a difference of resistance within each of the interweaved fingers in the direction of propagation of current; a second layer arranged below the first layer. The second layer compensates for the difference of resistance in the first layer.

Abstract: A semiconductor device is provided including a die having an electronic component integrated thereon. The component includes regions in the die, including a first region of a first charge type electrically connected to a first device terminal, a second region of a second charge type forming a first PN junction with the first region, a third region of the first charge type forming a second PN junction with the second region, the third region being spaced apart from the first region by the second region and being electrically connected to the second device terminal, a fourth region of the first charge type forming a third PN junction with the second region, the fourth region being spaced apart from the first region and third region by the second region. The device further includes an electronic unit electrically connected between the first device terminal, the second device terminal and the fourth region.

Abstract: The disclosure relates to an electronic component packing reel for a tape and reel packaging system and the electronic components are supported in pockets of a carrier tape wound around the reel, the packing reel includes: a central hub; two wall elements attached on both sides of the centrale hub defining a retaining space for retaining the carrier tape wound around the central hub; a hub insert arranged for placement of the hub insert over the central hub, the hub insert having an outer rim diameter for increasing a diameter of the central hub, and the hub insert includes at least two sections having mating locking means for interlocking the sections upon placement of the hub insert over the central hub.