Abstract: This disclosure relates to a semiconductor device and method of manufacture, including: a semiconductor die having a first major surface and a first contact terminal arranged thereon and an opposing second major having a second contact terminal arranged thereon and a first lead frame having first and second opposing major surfaces. The first major surface is fixedly attached to the first contact terminal of the semiconductor die. A second lead frame has first and second opposing major surfaces and the first major surface is fixedly attached to the second contact terminal of the semiconductor die. The first lead frame includes an integrally formed external contact portion extending from the first major surface thereof to a plane substantially co-planar with the second major surface of the second leadframe.

Abstract: This disclosure relates to a power semiconductor device and a method of manufacturing the same, including: a semiconductor layer defining a first major surface and a drift region and a trench extending from the first major surface into the semiconductor layer. The trench includes a gate electrode surrounded by a gate dielectric configured and arranged to electrically isolate the gate electrode from the semiconductor layer; and a source region extending from the first major surface and abutting a top side-wall portion of the trench, and the source region extends to a depth corresponding to a top surface of the gate electrode.

Abstract: This disclosure relates to a discrete semiconductor device and associated method of manufacture, the discrete semiconductor device includes: a high voltage depletion mode device die; and a low voltage enhancement mode device die connected in cascode configuration with the high voltage depletion mode device die. The high voltage depletion mode device includes a gate, source and drain terminals arranged on a first surface thereof and the gate source and drain terminals are inverted with respect to the low voltage enhancement mode device die and the low voltage device is arranged adjacent to the high voltage device.

Abstract: This disclosure relates to a semiconductor device structure and method of manufacturing a semiconductor device. The semiconductor device structure comprises a semiconductor substrate having an edge region laterally separated from a device region; an edge termination structure arranged on the semiconductor substrate; wherein the edge termination structure comprises: a first oxide layer arranged on the substrate to extend from the active region to the edge region; an isolation layer arranged on top of the first oxide layer; and a metal layer arranged to at least partially cover the isolation layer and wherein the metal layer is further arranged to extend from the isolation layer to contact the edge region.

Abstract: The present disclosure relates to a semiconductor device, and associated method of manufacture. The semiconductor device includes, MOSFET integrated with a p-n junction, the p-n junction arranged as a clamping diode across a source contact and a drain contact of the MOSFET. The MOSFET defines a first breakdown voltage and the clamping diode defines a second breakdown voltage, with the first breakdown voltage being greater than the second breakdown voltage so that the clamp diode is configured and arranged to receive a low avalanche current and the MOSFET is configured and arranged to receive a high avalanche current.

Abstract: The present disclosure relates to a lead frame assembly for a semiconductor device. The leadframe assembly includes a clip frame structure with a die connection portion configured and arranged for contacting to one or more contact terminals on a top side of a semiconductor die; and one or more electrical leads extending from the die connection portion at a first end. The die connection portion includes a hooking tab extending therefrom configured and arranged to engage with a wire loop of a wire pull test equipment. The disclosure also relates to an interconnected matrix of such leadframe.

Abstract: A field effect transistor semiconductor device having a compact device footprint for use in automotive and hot swap applications. The device includes a plurality of field effect transistor cells with the plurality of transistor cells having at least one low threshold voltage transistor cell and at least one high threshold voltage transistor cell arranged on a substrate. The field effect transistor semiconductor device is configured and arranged to operate the at least one high threshold voltage transistor cell during linear mode operation, and operate both the low threshold voltage transistor cell and the high threshold voltage transistor cell during resistive mode operation. Further provided is a method of operating field effect transistor semiconductor device including a plurality of field effect transistor cells that includes at least one low threshold voltage transistor cell and at least one high threshold voltage transistor cell.

Abstract: The disclosed device includes a single electric motor for linear and rotary movement with a stator. The stator includes a multi-phase coil arrangement with a plurality of coils or coil sets and a rotor. The rotor is movable in an axial direction of a rotational axis thereof and includes a plurality of poles respectively with at least one permanent magnet The device further includes a control unit operative to determine currents (Ir, Is, It) by calculation formulas and based on at least a number of coils or coil sets of the plurality of coils or coil sets, and an angle of rotation of said rotor and a parameter depending on an axial position of the rotor. Each current (Ir, Is, It) has a current component (Ir?, Is?, It?) for generating a torque and a current component (Irx, Isx, Itx) for generating an axial force, and to supply the determined currents in open loop to the number of coils or coil sets, so that the sum of the currents is zero. Further, at least one of the stator and the rotor, includes a back-iron.

Abstract: The disclosure relates to an electrical contact structure, and corresponding method of manufacturing an electrical contact structure, for a discrete semiconductor device. The electrical contact includes a first metal layer configured and arranged to contact a strained active area of a semiconductor die, a second metal layer configured and arranged to contact the first metal layer, and a third metal layer configured and arranged to contact the second metal layer.

Abstract: The present disclosure relates to a lead frame assembly for a semiconductor device. The leadframe assembly includes a clip frame structure with a die connection portion configured and arranged for contacting to one or more contact terminals on a top side of a semiconductor die; and one or more electrical leads extending from the die connection portion at a first end. The die connection portion includes a hooking tab extending therefrom configured and arranged to engage with a wire loop of a wire pull test equipment. The disclosure also relates to an interconnected matrix of such leadframe.

Abstract: The present disclosure relates to a semiconductor chip scale package including a semiconductor die. The semiconductor die has a first major surface opposing a second major surface, a plurality of side walls extending between the first major surface and second major surface, a plurality of electrical contacts arranged on the second major surface of the semiconductor die, and an insulating material disposed on the plurality of side walls and on the first major surface. The insulating material includes a machine readable identifier by which a semiconductor chip scale packaging type is identifiable by an identification apparatus that reads the machine readable identifier, and the machine readable identifier includes a colour component.

Abstract: The present disclosure relates to a bipolar transistor semiconductor device including: a substrate layer, a collector epitaxial layer supported by the substrate layer, a base region supported by a portion of the collector epitaxial layer, and an emitter region supported by a portion of the base region. The emitter region includes a polysilicon material.

Abstract: Various aspects of the disclosure are directed to circuitry coupled for controlling current flow, such as in a cascode arrangement. As may be consistent with one or more embodiments, an apparatus includes a first transistor having a gate, source, channel and drain, and a second transistor having a gate, and having a stacked source, channel and drain. A conductive clip plate electrically connects the drain of the second transistor to the source of the first transistor, and another conductor electrically connects the source of the second transistor to the gate of the first transistor. The second transistor operates with the connecting structure to provide power by controlling the first transistor in an off-state and in an on-state.

Abstract: An electronic device including a die and at least one lead. The electronic device further includes a corresponding at least one connector, each connector for connecting the die to a corresponding lead or leads, and each connector having a first end disposed in bondable proximity to a complementary surface of the corresponding lead and a second end disposed in bondable proximity to a complementary surface of the die. An end portion of at least one of the first end and second end has a formation, the formation in combination with the complementary surface of one, or both, of the respective lead or the die defining therebetween a first region and at least a second region configured to attract by capillary action an electrically conductive bonding material to consolidate therein.

Abstract: A semiconductor device and a method of making the same. The device includes a semiconductor substrate provided in a chip-scale package (CSP). The device also includes a plurality of contacts provided on a major surface of the substrate. The device further includes an electrically floating metal layer forming an ohmic contact on a backside of the semiconductor substrate. The device is operable to conduct a current that passes through the substrate from a first of said plurality of contacts to a second of said plurality of contacts via the metal layer on the backside.

Abstract: This disclosure relates to a filter circuit for an output stage of an electronic circuit. The filter circuit includes a capacitor connected between a supply voltage and a first transistor. The first transistor is arranged as a diode connected transistor; a second transistor is connected to the first transistor so that the first and second transistors are arranged as a current mirror. The capacitor is connected to the first and second transistors and configured and arranged so that during operation the first transistor, the second transistor and the capacitor operate as a high pass filter.

Abstract: A method comprising; transferring a holding liquid into at least one pocket of a carrier tape, the at least one pocket comprising a recess within the carrier tape configured to receive an electronic component; placing an electronic component into the at least one pocket whereby the holding liquid acts to retain the electronic component within the pocket; and applying a sealing tape over the carrier tape to close the pocket with the electronic component therein.

Abstract: A semiconductor device and a method of making the same is provided. The device includes a semiconductor substrate having a major surface and a back surface. The device also includes a bipolar transistor. The bipolar transistor has a collector region located in the semiconductor substrate; a base region located within the collector region and positioned adjacent the major surface; an emitter region located within the base region and positioned adjacent the major surface; and a collector terminal located on the major surface of the semiconductor substrate. The collector terminal includes: a first electrically conductive part electrically connected to the collector region; an electrically resistive part electrically connected to the first electrically conductive part, and a second electrically conductive part for allowing an external electrical connection to be made the collector terminal. The second conductive part is electrically connected to the first conductive part via the resistive part.

Abstract: A field effect transistor semiconductor device having a compact device footprint for use in automotive and hot swap applications. The device includes a plurality of field effect transistor cells with the plurality of transistor cells having at least one low threshold voltage transistor cell and at least one high threshold voltage transistor cell arranged on a substrate. The field effect transistor semiconductor device is configured and arranged to operate the at least one high threshold voltage transistor cell during linear mode operation, and operate both the low threshold voltage transistor cell and the high threshold voltage transistor cell during resistive mode operation. Further provided is a method of operating field effect transistor semiconductor device including a plurality of field effect transistor cells that includes at least one low threshold voltage transistor cell and at least one high threshold voltage transistor cell.

Abstract: Various aspects of the disclosure are directed to circuitry that may be used to shunt current. As may be consistent with one or more embodiments a first circuit has a plurality of alternating p-type and n-type semiconductor regions with respective p-n junctions therebetween, arranged between an anode end and a cathode end. A second (e.g., bypass) circuit is connected to one of the alternating p-type and n-type semiconductor regions, and forms a further p-n junction therewith. The second circuit operates to provide carrier flow, which influences operation of the first circuit.