Patents Assigned to Nexperia B.V.
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Patent number: 10546816Abstract: A semiconductor device and a method of making the same. The device includes a substrate comprising a major surface and a backside. The device also includes a dielectric partition for electrically isolating a first part of the substrate from a second part of the substrate. The dielectric partition extends through the substrate from the major surface to the backside.Type: GrantFiled: November 18, 2016Date of Patent: January 28, 2020Assignee: Nexperia B.V.Inventors: Hans-Martin Ritter, Joachim Utzig, Frank Burmeister, Godfried Henricus Josephus Notermans, Jochen Wynants, Rainer Mintzlaff
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Patent number: 10529644Abstract: A semiconductor device and a method of making the same. The device includes an electrically conductive heat sink having a first surface. The device also includes a semiconductor substrate. The device further includes a first contact located on a first surface of the substrate. The device also includes a second contact located on a second surface of the substrate. The first surface of the substrate is mounted on the first surface of the heat sink for electrical and thermal conduction between the heat sink and the substrate via the first contact. The second surface of the substrate is mountable on a surface of a carrier.Type: GrantFiled: February 22, 2016Date of Patent: January 7, 2020Assignee: Nexperia B.V.Inventors: Shun Tik Yeung, Pompeo Umali, Hans-Juergen Funke, Chi Ho Leung, Wolfgang Schnitt, Zhihao Pan
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Publication number: 20190393137Abstract: The disclosure relates to a lead frame assembly for a semiconductor device, the lead frame assembly including: a die attach structure and clip frame structure. The clip frame structure includes: a die connection portion configured to contact to one or more contact terminals on a top side of the semiconductor die; one or more electrical leads extending from the die connection portion at a first end, and a lead supporting member extending from a second end of the one or more leads; and a plurality of clip support members arranged orthogonally to the one or more electrical leads. The plurality of support members and the lead supporting member are configured to contact the die attach structure. The present disclosure also relates a die attach structure and clip frame structure for a semiconductor device, a semiconductor device including the same and a method of manufacturing the semiconductor device.Type: ApplicationFiled: June 20, 2019Publication date: December 26, 2019Applicant: NEXPERIA B.V.Inventors: Ricardo Lagmay YANDOC, Adam Richard BROWN, Arnel Biando TADURAN
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Patent number: 10410941Abstract: A semiconductor device includes a semiconductor die having a top surface that has one or more electrical contacts formed thereon, and an opposite bottom surface. A molding material encapsulates the top surface and at least a part of a side surface of the semiconductor die. The molding material defines a package body that has a top surface and a side surface. Openings are formed on the top surface of the package body, and the electrical contacts are partially exposed from the molding material through the openings. A metal layer is formed over and electrically connected to the electrical contacts through the openings. The metal layer extends to and at least partially covers the side surface of the package body.Type: GrantFiled: September 8, 2016Date of Patent: September 10, 2019Assignee: Nexperia B.V.Inventors: Chi Ho Leung, Pompeo V. Umali, Shun Tik Yeung, Kan Wae Lam
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Patent number: 10403747Abstract: A semiconductor device and a method of making the same is disclosed. The device includes a substrate having an AlGaN layer located on a GaN layer for forming a two dimensional electron gas at an interface between the AlGaN layer and the GaN layer. The device also includes a plurality of contacts. At least one of the contacts includes an ohmic contact portion located on a major surface of the substrate. The ohmic contact portion comprises a first electrically conductive material. The at least one of the contacts also includes a trench extending down into the substrate from the major surface. The trench passes through the AlGaN layer and into the GaN layer. The trench is at least partially filled with a second electrically conductive material. The second electrically conductive material is a different electrically conductive material to the first electrically conductive material.Type: GrantFiled: November 18, 2016Date of Patent: September 3, 2019Assignee: Nexperia B.V.Inventors: Godefridus Adrianus Maria Hurkx, Johannes Josephus Theodorus Marinus Donkers, Jan Sonsky, Jeroen Antoon Croon
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Publication number: 20190263546Abstract: A tape-and-reel system for processing components is disclosed. In the embodiment, the tape-and-reel system includes a first carrier tape reel for holding unloaded carrier tape, a component loading system for loading components into pockets of the unloaded carrier tape, an air-guided cover tape feeder through which cover tape travels, an alignment tool for guiding the cover tape into alignment with the loaded carrier tape and adhering the cover tape to the loaded carrier tape to secure the components into the loaded carrier tape, and a second carrier tape reel for holding the loaded carrier tape.Type: ApplicationFiled: May 13, 2019Publication date: August 29, 2019Applicant: NEXPERIA B.V.Inventor: Antonius Johannes Hendrikus Vissers
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Patent number: 10388778Abstract: A heterojunction semiconductor device is disclosed. The heterojunction semiconductor device includes a substrate and a multilayer structure disposed on the substrate. The multilayer structure includes a first layer comprising a first semiconductor disposed on top of the substrate, and a second layer comprising a second semiconductor disposed on top of the first layer to define an interface between the first layer and the second layer. The second semiconductor is different from the first semiconductor such that a Two-Dimensional Electron Gas forms adjacent to the interface. The device also includes a first terminal electrically coupled to a first area of the interface between the first layer and second layer and a second terminal electrically coupled to a second area of the interface between the first layer and second layer. The device also includes an electrically conducting channel comprising an implanted region at bottom and sidewalls.Type: GrantFiled: November 18, 2016Date of Patent: August 20, 2019Assignee: Nexperia B.V.Inventors: Saurabh Pandey, Jan Sonsky
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Publication number: 20190252409Abstract: A semiconductor device structure and method of manufacturing a semiconductor device is provided. The method includes providing a first semiconductor substrate having a first major surface and an opposing second major surface, the first major surface having a first metal layer formed thereon; providing a second semiconductor substrate having a first major surface and an opposing second major surface, with the second semiconductor substrate including a plurality of active device regions formed therein and a second metal layer formed on the first major surface connecting each of the plurality of active device regions; bonding the first metal layer of the first semiconductor substrate to the second metal layer of the second semiconductor substrate; and forming device contacts on the second major surface of the second semiconductor substrate for electrical connection to each of the plurality of active device regions.Type: ApplicationFiled: February 11, 2019Publication date: August 15, 2019Applicant: NEXPERIA B.V.Inventors: Hans-Martin RITTER, Frank BURMEISTER
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Publication number: 20190229109Abstract: A semiconductor device arrangement and a method of operating a semiconductor device arrangement. The semiconductor device can be arranged for bidirectional operation. The semiconductor device arrangement can comprise: a field effect transistor comprising first and second input terminals; a control terminal; a first diode connected between the first terminal and the control terminal; and a second diode connected between the second terminal and the control terminal; wherein the first terminal and the second terminal are configured and arranged to be connected to respective signal lines.Type: ApplicationFiled: January 22, 2019Publication date: July 25, 2019Applicant: NEXPERIA B.V.Inventors: Hans-Martin RITTER, Andreas ZIMMERMAN
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Publication number: 20190206829Abstract: A bonding and indexing apparatus has a first index head to move a substrate in an indexing direction from a first position to a second position and a second index head to move the substrate in an indexing direction from the second position to a third position. The first and/or second index head has a bonding element to effect a bonding process between the substrate and an element disposed against the substrate so that bonding and movement in the indexing direction is implemented simultaneously by the first index head and/or bonding and movement in the indexing direction is implemented simultaneously by the second index head.Type: ApplicationFiled: December 27, 2018Publication date: July 4, 2019Applicant: NEXPERIA B.V.Inventors: Ralph HUYBERS, Hans VAN DE RIJDT
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Patent number: 10336480Abstract: A tape-and-reel system for processing components is disclosed. In the embodiment, the tape-and-reel system includes a first carrier tape reel for holding unloaded carrier tape, a component loading system for loading components into pockets of the unloaded carrier tape, an air-guided cover tape feeder through which cover tape travels, an alignment tool for guiding the cover tape into alignment with the loaded carrier tape and adhering the cover tape to the loaded carrier tape to secure the components into the loaded carrier tape, and a second carrier tape reel for holding the loaded carrier tape.Type: GrantFiled: June 18, 2015Date of Patent: July 2, 2019Assignee: Nexperia B.V.Inventor: Antonius Johannes Hendrikus Vissers
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Publication number: 20190189468Abstract: A semiconductor device structure and method of manufacturing a semiconductor device. The semiconductor device may comprise a semiconductor die having a top major surface that has one or more electrical contacts formed thereon, an opposing bottom major surface, and side surfaces; a molding material encapsulating the top major surface, the bottom major surface and the side surfaces of the semiconductor die, wherein the molding material defines a package body that has a top surface and a side surface; wherein the plurality of electrical contacts are exposed on the top surface of the package body and a metal layer is arranged over and electrically connected to the electrical contacts and wherein the metal layer extends to and at least partially covers a side surface of the package body.Type: ApplicationFiled: December 14, 2018Publication date: June 20, 2019Applicant: NEXPERIA B.V.Inventors: Leung CHI HO, Pompeo V. UMALI, Shun Tik YEUNG
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Publication number: 20190189545Abstract: An electronic device including a die and at least one lead. The electronic device further includes a corresponding at least one connector, each connector for connecting the die to a corresponding lead or leads, and each connector having a first end disposed in bondable proximity to a complementary surface of the corresponding lead and a second end disposed in bondable proximity to a complementary surface of the die. An end portion of at least one of the first end and second end has a formation, the formation in combination with the complementary surface of one, or both, of the respective lead or the die defining therebetween a first region and at least a second region configured to attract by capillary action an electrically conductive bonding material to consolidate therein.Type: ApplicationFiled: December 17, 2018Publication date: June 20, 2019Applicant: NEXPERIA B.V.Inventors: Tim BOETTCHER, Haibo FAN, Wai Wong CHOW, Pompeo V. UMALI, Shun Tik YEUNG, Chi Ho LEUNG
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Publication number: 20190189544Abstract: A semiconductor package and a method of manufacturing a semiconductor package. The semiconductor package includes a leadframe having a die attach portion and a lead portion; a semiconductor die mounted on the die attach portion, the semiconductor die having a contact terminal arranged thereon; a clip portion having: a first tab portion receivably mounted in a hole in the lead portion, and a second tab portion arranged on either side of the first tab portion. The second tab portions are fixedly mounted to connect the clip portion to the lead portion.Type: ApplicationFiled: December 17, 2018Publication date: June 20, 2019Applicant: NEXPERIA B.V.Inventors: Ricardo Lagmay YANDOC, Adam Richard BROWN
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Publication number: 20190189530Abstract: A semiconductor device and a method of manufacturing a semiconductor device. The chip scale package semiconductor device comprises: a semiconductor die having a first major surface and an opposing second major surface, the semiconductor die comprising at least two terminals arranged on the second major surface; a carrier comprising a first major surface and an opposing second major surface, wherein the first major surface of the semiconductor die is mounted on the opposing second major surface of the carrier; and a molding material partially encapsulating the semiconductor die and the carrier, wherein the first major surface of the carrier extends and is exposed through molding material, and the at least two terminals are exposed through molding material on a second side of the device.Type: ApplicationFiled: December 14, 2018Publication date: June 20, 2019Applicant: NEXPERIA B.V.Inventors: Loh Choong KEAT, Edward THEN, Weng Khoon MONG
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Publication number: 20190189478Abstract: An apparatus is provided for transferring a semiconductor device from a wafer to a target position. The apparatus has at least one rotatable transfer assembly, which has a transfer head rotatable about an axis of rotation of the rotatable transfer assembly to transfer a semiconductor device from a pick-up position to a transfer position. The apparatus also has a transfer assembly actuator arrangement operative to effect movement of the at least one rotatable transfer assembly in an axial direction relative to a plane of rotation of the transfer head.Type: ApplicationFiled: December 17, 2018Publication date: June 20, 2019Applicant: NEXPERIA B.V.Inventors: Ralph HUYBERS, Hans VAN DE RIJDT
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Publication number: 20190165111Abstract: This disclosure relates to a semiconductor device structure and method of manufacturing a semiconductor device. The semiconductor device structure comprises a semiconductor substrate having an edge region laterally separated from a device region; an edge termination structure arranged on the semiconductor substrate; wherein the edge termination structure comprises: a first oxide layer arranged on the substrate to extend from the active region to the edge region; an isolation layer arranged on top of the first oxide layer; and a metal layer arranged to at least partially cover the isolation layer and wherein the metal layer is further arranged to extend from the isolation layer to contact the edge region.Type: ApplicationFiled: November 20, 2018Publication date: May 30, 2019Applicant: NEXPERIA B.V.Inventors: Martin ROEVER, Soenke HABENICHT, Stefan BERGLUND, Seong-Woo BAE
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Patent number: 10304759Abstract: An electronic device has a first surface, a second surface opposite to the first surface, and sidewalls located between and adjoining the first and second surfaces. The electronic device includes contact pads on the first surface. The contact pads extend from the first surface to adjoining sidewalls, and abut the sidewalls.Type: GrantFiled: August 5, 2016Date of Patent: May 28, 2019Assignee: Nexperia B.V.Inventors: Kan Wae Lam, Shun Tik Yeung, Pompeo V. Umali, Chi Ho Leung, Chi Ling Shum
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Patent number: 10297500Abstract: A method of dicing a bowed or warped semiconductor wafer includes cutting along the saw streets in a first direction on a first half of the wafer, where the first direction is parallel to the bowing, cutting along the saw streets in the first direction on a second half of the wafer opposite to the first half, and step-cutting along the saw streets in the second direction, such that all of the dies are separated from each other, and the sides of the die in the bowing direction are flat and the sides of the die perpendicular to the bowing direction are stepped.Type: GrantFiled: December 15, 2016Date of Patent: May 21, 2019Assignee: Nexperia B.V.Inventors: Crispulo Estira Lictao, Jr., Pitak Seantumpol, Siriluck Wongratanaporngoorn, Matthew Mondala Fernandez, Amileth Dejan Cabrera
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Publication number: 20190123037Abstract: A semiconductor device and method of manufacturing a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a semiconductor layer located on the substrate; at least one shallow trench and at least one deep trench. Each of the at least one shallow trench and the at least one deep trench extending from a first major surface of the semiconductor layer. Sidewall regions and base regions of the trenches comprise a doped trench region and the trenches are at least partially filled with a conductive material contacting the doped region. The shallow trenches terminate in the semiconductor layer and the deep trench terminates in the semiconductor substrate.Type: ApplicationFiled: October 18, 2018Publication date: April 25, 2019Applicant: NEXPERIA B.V.Inventors: Steffen Holland, Zhihao Pan, Jochen Wynants, Hans-Martin Ritter, Tobias Sprogies, Thomas lgel-Holtzendorff, Wolfgang Schnitt, Joachim Utzig