Abstract: A reference voltage generating circuit is provided, including a first depletion type metal-oxide semiconductor field-effect transistor (MOSFET), a first enhancement type MOSFET, a reference voltage output connected between the first depletion type MOSFET and the first enhancement type MOSFET, and a second depletion type MOSFET.

Abstract: A lateral oriented transistor embodied in a semiconductor material, including a first group of directly adjacently placed transistor cells, a second group of directly adjacently placed transistor cells, the second group is spaced apart from the first group thereby providing a spacing, each of the transistor cells includes a drain, a source and a gate, and the lateral oriented transistor further includes a gate interconnect placed in the spacing between the first and second group, and the gate interconnect connects to the gates of the transistor cells.

Abstract: An electrostatic discharge protection device is provided. The present device relates to a semiconductor device that is particularly suitable as a component for electrostatic discharge protection. The semiconductor device comprises a first structure, including: a third semiconductor region of the second charge type, a fourth semiconductor region of the first charge type and being spaced apart from the third semiconductor region, and a first connection element configured to electrically connect the third semiconductor region to the fourth semiconductor region. The third semiconductor region is arranged in between the first semiconductor region and the fourth semiconductor region, and the fourth semiconductor region is arranged in between the second semiconductor region and the third semiconductor region.

Abstract: A method of testing a semiconductor device, in a package, having a junction between a semiconductor material of a first type and a semiconductor material of a second type. The junction has a temperature dependent breakdown voltage, and the method includes the steps of determining the breakdown voltage, providing a fixed voltage over the junction, via pins of the package, and the fixed voltage is higher than the breakdown voltage, and measuring, via pins of the package, a breakdown current flowing through the junction, determining a dissipated power based on the fixed voltage and the measured breakdown current, and the dissipated power is a qualitive measure for the semiconductor device.

Abstract: A module for electric circuitry having lower parasitic inductance is provided. The module for an electric circuit includes a substrate having circuitry containing a Direct Current (DC) pad and an Alternating Current (AC) pad. A first group of semiconductor dies is mounted on the AC pad, and a second group is mounted on the DC pad. Furthermore, the module includes a first DC terminal electrically connected to the first group, a second DC terminal electrically isolated from the first DC terminal and electrically connected to the DC pad of the circuitry, and an AC terminal at least connected to the AC pad of the circuitry. The module has connecting means to electrically connect the first group to the AC pad, second connecting means to electrically connect the second group to the DC pad, and third connecting means to electrically connect the second group to the AC pad.

Abstract: The present disclosure provides a semiconductor package including: a semiconductor die attached to a lead frame having lead terminals; at least one bond clip connecting the die to a lead terminal; a die top solder connecting the bond clip and the die, and an encapsulant. The clip includes a die attachment portion having a die attachment portion side structured to be connected to the die, the side is provided with a cavity functioning as an expansion space for the die top solder. This enables preventing the molten die top solder from spreading toward die edge and lead terminals, since the molten solder flow is directed inward to the cavity, instead of flowing outward. A bond clip for use in a semiconductor package is also provided, including a cavity functioning as an expansion space for the die top solder.

Abstract: The present disclosure relates to a semiconductor device and a method of manufacturing the semiconductor device. In particular, the disclosure relates to a semiconductor power packaging including the semiconductor device. It is a goal of the present disclosure to provide a method for manufacturing a semiconductor device without an insulation layer as a support layer for semiconductor dies thereby enhancing thermal and electrical performance as well as such a semiconductor device.

Abstract: A semiconductor device and a semiconductor package including such a semiconductor device are presented. The semiconductor device includes one or more dies, a power source clip, a signal source clip, a signal gate clip and a power drain clip, with each clip electrically connected to each of the dies. A Kelvin source connection is integrated on the signal source clip. At least one of the dies have an angle between a path of a power source current between the power source clip and a die and a path of a signal source current between the signal source clip and the die is equal to or larger than 90°.

Abstract: An encapsulated semiconductor package is proposed, including a plurality of rivets, and a plurality of connection pins, each connection pin having a pin tip and a pin end, the plurality of rivets are disposed in the encapsulant of the encapsulated semiconductor package, each rivet having a first rivet end and a second rivet end, each rivet being electrically mounted with a first rivet end on a corresponding bond pad of the semiconductor package; each rivet includes a rivet cavity configured to receive the pin tip of the connection pin; the pin tip of the connection pin is configured as a press-fit pin tip having an outer diameter larger than an inner diameter of the rivet cavity and configured for friction-based engagement with the rivet cavity.

Abstract: The present disclosure relates to the field of semiconductors and, more specifically, to the field of lateral Metal-Oxide-Semiconductor Field Effect Transistors. The present disclosure provides a MOSFET device operating with more than 40V BVDS (Break Down Voltage Drain to Source). This disclosure also relates to a method of manufacturing a lateral oriented Metal-Oxide-Semiconductor device.

Abstract: A package structure for a semiconductor device is provided, including: a substrate layer configured for thermal management and electrical insulation; one or more semiconductor dies on the substrate layer, each semiconductor die including: a first power contact configured to connect to a first terminal of the package, a second power contact configured to connect to a second terminal of the package, and a gate contact configured to connect to a gate terminal of the package; an integrated resistor structure disposed within the substrate layer.

Abstract: A method of manufacturing a semiconductor package having a connection pin for creating a connection between the semiconductor package and an external circuit, including the steps of, providing the semiconductor package having a bond pad for receiving a rivet; mounting the rivet onto the bond pad of the semiconductor package, the rivet is arranged to receive, in a rivet cavity of the rivet, the connection pin for creating the connection; molding the semiconductor package, having the mounted rivet, with a molding compound, and during the molding, an opening of the rivet is covered by a cover, the opening leading to the rivet cavity; removing the cover and providing the connection pin in the rivet cavity via the rivet opening of the rivet.

Abstract: The present disclosure is directed to the stacking of semiconductor structures, such as dies, and the stacked semiconductor assembly is suitable to be directly mounted to a Printed Circuit Board, PCB. The present disclosure allows for a small sized stacked semiconductor assembly utilizing both the MOSFET and the HEMT in a single assembly.

Abstract: A semiconductor package including a first and at least one further or second semiconductor device positioned at an interspacing from each other. Each of the semiconductor devices includes a die paddle having a semiconductor die region, and a stacked semiconductor device having a first surface and a second surface opposite to the first surface, and the first surface is mounted to the semiconductor die region. The semiconductor package further includes a half bridge clip having a first bridge clip portion electrically and mechanically connected to the second surface of the first semiconductor device and a further bridge clip portion electrically and mechanically connected to the second surface of the at least one further semiconductor device, and the half bridge clip includes at least one conductive element electrically and mechanically connecting to at least one of the die paddles of the first and the at least one further semiconductor device.

Abstract: A method of creating a vertical semiconductor device, the method includes the steps of performing a LOCal Oxidation of Silicon, LOCOS, process in a vertical trench of a semiconductor material so that oxide material is formed inside the vertical trench, and ledges are formed by the oxide material, inside the vertical trench, as a result of the LOCOS process, so that a lower region of reduced lateral distance is formed between the oxide material, at a base of the trench, depositing the trench with polysilicon and etching the polysilicon downward up to the oxide material using interferometric end point detection, so that polysilicon remains in the lower region.

Abstract: In the first aspect of the present disclosure, there is provided a method of manufacturing a semiconductor device, including the steps of: providing a substrate; mounting a semiconductor die having a first die surface and a second die surface opposite to the first die surface, with the first die surface mounted to the substrate; mounting a spacer having a first spacer surface and a second spacer surface opposite to the first spacer surface, with the first spacer surface mounted on the second die surface; fusing bonding to the second spacer surface by using ultrasonic fusing.

Abstract: The present disclosure relates to a method of manufacturing a semiconductor device, specifically of the connection of a bonding wire to a semiconductor die. In a first aspect of the disclosure, there is provided a method of manufacturing a semiconductor device, including the steps of: providing a semiconductor die onto a substrate; applying a paste to the semiconductor die; and connecting a bonding wire to the paste by ultrasonic motion.

Abstract: A semiconductor device, a semiconductor package including such a semiconductor device and a method of manufacturing such a semiconductor package are presented. The semiconductor device includes a die and a leadframe. The semiconductor device further includes a wire-bond interconnect structure including one or more pairs of wires. Herein, a pair of wires includes two wires that are bonded together at one end at the die and that are bonded together on the other end at the leadframe.

Abstract: A method limits an inrush current of a buck converter having an inductor element during a startup period in which the buck converter is first enabled. The inrush current flows through the inductor element by enabling a zero current detection algorithm for a first few operational cycles. A system is also configured to limit the inrush current of a buck converter having an inductor element during a startup period in which the buck converter is first enabled.

Abstract: A Switched Mode Power Supply (SMPS) with a switching stage has a high-side switch, a low-side switch, and an output inductor. The SMPS also has control circuitry for controlling the high-side switch and the low-side switch based on a clock signal. The control circuitry is configured to detect that an output voltage of the switching stage deviates from a reference voltage and thereby enable negative valley regulation. Upon enabling negative valley regulation, the control circuitry detects that a current flowing through the inductor falls below a threshold and, based on the detection, initiates a next clock cycle of the clock signal.