Abstract: Aspects of the present disclosure relate to an apparatus for transferring an electronic component or a piece of material using light. Aspects of the present disclosure further relate to a method for transferring an electronic component or a piece of material. According to an aspect of the disclosure the apparatus includes a donor stage for holding a donor substrate, an optical source for generating a pulse of collimated light, and a reflection unit including a plurality of micro-mirrors of which an orientation relative to the pulse of collimated light can be individually controlled. The micro-mirrors are configured to reflect the generated pulse of collimated light towards one or more donor positions on a donor substrate body for releasing one or more electronic components or one or more pieces of material among the plurality of electronic components or the plurality of pieces of material at those donor positions, respectively.

Abstract: A system for sensing a current through a transistor is provided and a DC-DC converter including one or more such systems. The system includes a transistor module, including: a primary transistor electrically connected between a first and a second terminal; and a secondary transistor electrically connected between the first and a third terminal, a control terminal of the secondary transistor is electrically connected to a control terminal of the primary transistor. The system includes a current sensing module electrically connected to the transistor module and having an output terminal. The system is operable in a first mode in which the current sensing module outputs, at the output terminal, a first output signal indicative of a current through the primary transistor in a first current direction based on a voltage difference between the third and the second terminal, the first current direction being from the first to the second terminal.

Abstract: A cascode transistor circuit including a depletion mode semiconductor device, an enhancement mode transistor having a drain terminal connected to a source terminal of the depletion mode semiconductor device, and a gate driver coupled to a first node between the source of the depletion mode semiconductor device and the drain of the enhancement mode transistor. The gate driver is powered by the depletion mode semiconductor device.

Abstract: A vertical oriented semiconductor device is provided. The present disclosure further provides that at least one of the well regions of the device have at least two lateral doping gradients, at different depths in the semiconductor material, and each doping gradient has a monotonic decreasing doping concentration, from a higher doping concentration at a first lateral end of the well regions towards a lower doping concentration at a second, opposite lateral end thereof facing the current-accommodating region. These two doping gradients, at different depths, differ from each other, with one of the advantages being that the semiconductor device is made more robust. Multiple ways of implementing the two different lateral doping gradients are provided. Some of the advantages are that the electric field crowding at the corners of the well regions is gradually reduced, and the current distribution can be improved.

Abstract: A peak-current mode (PCM), buck converter is provided, including a slope compensation element, the PCM buck converter is arranged to detect an entering or exiting of a pulse frequency modulation (PFM), mode of operation. The slope compensation element is arranged to disable or reduce a slope compensation when the PCM buck converter detects the entering of the PFM. The slope compensation element is arranged to enable the slope compensation when the PCM buck converter detects the exiting of the PFM.

Abstract: A semiconductor package assembly and molding resin case is provided. The package includes a lead frame having a first and a second lead frame side opposite to the first; a semiconductor die structure having a first and a second die side opposite to the first, the die structure being mounted with its second die side on the first lead frame side, resulting in a first connection; a bond element connected to the first die of the die structure, resulting in another connection; with the molding resin case encapsulating at least the die structure, the lead frame and a first part of at least one bond element connected to the die structure, leaving the second lead frame side and the at least one bond element partly exposed; and at least one bond element is provided with electric field modulation structures configured to alter an electric field created between the connections.

Abstract: An electronic circuit for sensing a current through a pass FET is provided. A first sense circuit passes a first sense current in case a difference between a supply voltage and a source voltage of the pass FET and is small, and a second sense circuit passes a second sense current in case the difference between the supply voltage and the source voltage of the pass FET is large. The first sense current and the second sense current are representative of the current through the pass FET.

Abstract: A trench-gate semiconductor device and a manufacturing method thereof is provided. The device is provided with each unit cell including a first trench, and a second trench extending from a bottom of the first trench. The device includes a gate oxide layer arranged on a first side wall of the first trench, a second oxide layer arranged on a second side wall and bottom of the second trench, a first polysilicon region arranged inside the first trench, separated from the first side wall by the gate oxide layer, forming a gate of the unit cell. The device includes a second polysilicon region arranged inside the second trench, separated from the second side wall and bottom of the second trench by the second oxide layer, forming a buried source of the unit cell, and a third oxide layer arranged in between the first polysilicon region and the second polysilicon region.

Abstract: An insulated-gate bipolar transistor device is provided including: a first region doped with a first type of charge carriers; a second region doped with a second type of charge carriers different from the first type of charge carriers; a third region doped with the first type of charge carriers; a fourth region doped with the second type of charge carriers; a first, emitter terminal electrically connected with the first region and a second, collector terminal electrically connected with the third region and the fourth region; and a gate structure disposed on the third region with one end adjacent to the second region and with another end adjacent the fourth region; as well as a diode structure having a first diode structure terminal electrically connected with the collector terminal and a second diode structure terminal electrically connected with the gate terminal of the gate structure.

Abstract: A power semiconductor device has a power semiconductor die forming a power switch with an input pad, an output pad, and a control pad; a collector power terminal coupled to the input pad of the power switch; an auxiliary gate terminal coupled to the control pad of the power switch; an emitter power terminal; two or more inductance/resistance pairs, with each inductance/resistance pair having a common stray inductance and a resistance arranged in series between the output pad of the power switch and the emitter power terminal; and a plurality of auxiliary emitter terminals that are coupled to both sides of the inductance/resistance pairs so that one auxiliary emitter terminal is coupled to one side of one inductance/resistance pair. A control circuit for di/dt control can control the power semiconductor device. An electronic device can include the power semiconductor device and control circuit.

Abstract: A cell structure of an insulated gate bipolar transistor (IGBT) with a control gate and a carrier storage layer, is provided including: an N-type drift layer with a first surface, an active region on a second surface opposing the first and an N-type storage layer, a P-type body layer and an N-type doped layer sequentially stacked in the active region from the first to the second surface, gate trench bodies, each of which extends from the second to the first surface in a first direction perpendicular to the first surface and contacts the N-type drift layer, and each of the at least three gate trench bodies is a gate trench or a control gate trench. A sidewall of the gate trench is in contact with the active region, and a sidewall of the control gate trench is in contact with the P-type layer but not with the N-type layer.

Abstract: A method of manufacturing semiconductor devices, the method includes the steps of providing a carrier layer including a first surface and a second surface opposite to the first surface, attaching a first metallization layer to the first surface of the carrier layer, transferring a metal paste to the first metallization layer for creating first patterned metal pads and dicing the carrier layer to provide the plurality of semiconductor devices.

Abstract: Aspects of the present disclosure generally relate to an MPS diode and a manufacturing method therefor. The MPS diode includes a semiconductor body including an active area, the active area includes a drift region of a first conductivity type, and a plurality of wells of a second conductivity type different from the first conductivity type, the plurality of wells being mutually spaced apart, each well forming a respective PN-junction with the drift region. The MPS diode further includes a metal layer assembly arranged on a surface of the semiconductor body and at least one metal layer, the metal layer assembly forming a plurality of Schottky contacts together with the drift region and a plurality of respective Ohmic contacts with the plurality of wells. A spacing between adjacently arranged wells increases in an outward direction from a center of the active area.

Abstract: A method for soft recovery for switched mode power supplies includes: (a) detecting a drop of the output voltage value FB; (b) starting the output voltage values FB recovery using a current FB value stored as a Vref start value from which the recovery is to be made; (c) detecting the start of the recovery of the output voltage; (d) generating a timing pulse; (e) measuring a FB value on the rising edge of the timing pulse and comparing the FB value with the Vref value, and if the FB value is greater than the Vref value, storing the FB value and setting the FB value as the new Vref start value from which the recovery is to be made going forward; and (f) repeating step (d) and (e), after a preset time delay, until the FB value is less than or equal to the Vref for the FB value.

Abstract: A frame module for a semiconductor integrated circuit (IC) including a substrate having the IC, a module to enclose the IC, a Direct Current (DC) supply terminal to provide DC power to the substrate, a DC return terminal to provide a return line for the DC power and an Alternating Current (AC) terminal to provide AC connections to the substrate, the DC supply terminal connects to the substrate at a first end, the DC return terminal connects to the substrate at a second end, the second end being opposite to the first, and the DC return terminal extends above the substrate towards the first end of the substrate, the DC return terminal has at least one opening, located at a part of the DC return terminal that extends above the substrate and the AC terminal connects to the substrate via at least one opening provided in the DC return terminal.

Abstract: The present disclosure relates to a pin used for a connection of an electronic device, such electronic device with the pin and the method of assembling such electronic device. The signal pin, which is suitable to be placed in a slot, includes a metal pin having a first end, a second end and a side surface, and a metal ribbon having a first end and a second end. The first end of the metal ribbon and the first end of the metal pin and/or the side surface of the metal pin form a galvanic connection.

Abstract: A method for manufacturing a semiconductor package assembly, the method including the steps of: after a Die Attach Clip Attach (DACA) process on a semiconductor package, performing a flux cleaning treatment process and exposed surfaces of the semiconductor package are cleaned; performing a surface roughening treatment process and the exposed surfaces are roughened, the surface roughening treatment process is performed separately from the flux cleaning treatment process; and after performing the surface roughening treatment process, encapsulating the semiconductor package with a molding resin, thereby forming the encapsulated semiconductor package assembly.

Abstract: A semiconductor device is proposed, including a substrate, at least a first semiconductor die having a first die surface and a second die surface opposite to the first die surface, the at least one semiconductor die is mounted with the first die surface on the substrate, and at least one heat transfer component including a spatial configuration composed of a first component face and a second component face spaced apart from each other defining a spatial enclosure comprising a heat transfer medium, and the at least one heat transfer component is in heat exchanging contact with the second die surface and the substrate.

Abstract: A vertical semiconductor component including: a substrate; an epitaxial layer doped with a first conductivity type, preferably n-doped, provided on the substrate; a metal layer deposited on the epitaxial layer to form a Schottky contact with the epitaxial layer; a plurality of first regions embedded in the epitaxial layer and contacting the metal layer, and doped with a second conductivity type, in order to form a plurality of pn-junctions with the epitaxial layer; and a plurality of second regions embedded in a first region and contacting the metal layer, and doped with a second conductivity type, at a higher concentration, in order to form a plurality of low-resistance ohmic contacts with the metal layer. The semiconductor component includes a lateral cross section along which there are more first regions than second regions.

Abstract: A current-controlled semiconductor system is provided, including a signal and a ground line, and a semiconductor controlled rectifier (SCR) device including a first SCR layer doped with a first type of charge carriers; a second SCR layer doped with a second type different from the first type; a third SCR layer doped with the first type; a fourth SCR layer doped with the second type; an input terminal connected with the first SCR layer and the signal line and an output terminal connected with the fourth SCR layer and ground line; at least a first SCR junction element connected with the second SCR layer and the signal line, and/or a second SCR junction element connected with the third SCR layer and the ground line, the system includes at least one current trigger device connecting the signal line with the third SCR layer or the ground line with second SCR layer.