Abstract: A current-controlled semiconductor system is provided, including a signal and a ground line, and a semiconductor controlled rectifier (SCR) device including a first SCR layer doped with a first type of charge carriers; a second SCR layer doped with a second type different from the first type; a third SCR layer doped with the first type; a fourth SCR layer doped with the second type; an input terminal connected with the first SCR layer and the signal line and an output terminal connected with the fourth SCR layer and ground line; at least a first SCR junction element connected with the second SCR layer and the signal line, and/or a second SCR junction element connected with the third SCR layer and the ground line, the system includes at least one current trigger device connecting the signal line with the third SCR layer or the ground line with second SCR layer.

Abstract: A method of forming a gate of a split-gate trench MOSFET in an epitaxial layer is provided, the epitaxial layer includes a source polysilicon rib which extends perpendicularly to a plane of the layer; providing trenches on either side of an upper portion of the source polysilicon rib, with inner walls of the trenches formed by a deposited insulator, providing mask material which extends into the trench, providing photoresist on the epitaxial layer and using photolithography to pattern the photoresist, using the photoresist to etch the insulator, a portion of the insulator in contact with the source polysilicon is protected from etching by the mask, removing the mask and forming trenches on either side of the source polysilicon, each trench having an inner wall formed by the insulator which was protected from etching providing an insulator on the epitaxial layer, and providing a bar of gate polysilicon in each trench.

Abstract: A semiconductor device is provided, more particularly, a semiconductor controlled rectifier device (SCR) device, which achieves low capacitance, low trigger voltage, fast turn-on, and low on-resistance. Additionally, the semiconductor controlled rectifier device (SCR) device can achieve low capacitance, low trigger voltage, fast turn-on, and low on-resistance at the same time.

Abstract: The present disclosure relates to a power converter and to a buck DC-to-DC power converter, such as a constant-on-time (COT) Buck DC-to-DC power converter. Additionally, a COT Buck DC-to-DC converter is provided which has a seamless transition between the normal operation mode and the 100% duty operation mode.

Abstract: A cascode transistor circuit including a depletion mode semiconductor device, an enhancement mode transistor having a drain terminal connected to a source terminal of the depletion mode semiconductor device, and a gate driver coupled to a first node between the source of the depletion mode semiconductor device and the drain of the enhancement mode transistor. The gate driver is powered by the depletion mode semiconductor device.

Abstract: According to an aspect of the present disclosure, a drive voltage generator for driving a GaN high electron mobility transistor is provided. According to another aspect there is provided a GaN high electron mobility transistor unit including a GaN high electron mobility transistor, and a drive voltage generator connected to the GaN high electron mobility transistor. A method for generating a drive voltage for a GaN high electron mobility transistor is also provided.

Abstract: A control circuit for an output driver with a slew rate control circuit is disclosed. The control circuit includes a turn-on facilitating module having a control input and configured to be connected to the output driver and to supply a supplementary voltage to the output driver in response to a control voltage at the control input; and a sensing module configured to be connected to the turn-on facilitating module and the output driver and to switch off the turn-on facilitating module in response to an input voltage of the output driver sensed by the sensing module.

Abstract: The present disclosure relates to a bipolar transistor semiconductor device including: a substrate layer, a collector epitaxial layer supported by the substrate layer, a base region supported by a portion of the collector epitaxial layer, and an emitter region supported by a portion of the base region. The emitter region includes a polysilicon material.

Abstract: A repeater for open-drain bus communication and a system including the same is provided. The repeater includes at least one repeating unit having an A-side terminal connected to an A-side open-drain bus, and a B-side terminal electrically connected to a B-side open-drain bus. The repeater has a first mode to receive a signal at the A-side and to produce a signal at the B-side. The repeating unit includes a B-side accelerator element connected to the B-side terminal. The repeating unit when in a first mode includes a first control unit to, control the B-side accelerator element to pull up a voltage at the B-side when the voltage at the A-side surpasses a first threshold voltage during a rising edge of the voltage, and to subsequently control the B-side accelerator element to stop pulling up the voltage at the B-side when the voltage at the B-side surpasses a second threshold voltage.

Abstract: A semiconductor package including a lead frame, an Ag plated surface positioned on the lead frame, an adhesion promotion layer positioned on the top of the Ag plated surface, and mold body covering the top of the lead frame is provided. The Ag plated surface covers a significant part of an interconnection area of the lead frame surface, and the Ag plating surface does not exceed the area of the mold body.

Abstract: A method of manufacturing a semiconductor trench-gate semiconductor device is provided, that includes a trench divided into a first trench and a second trench and the source poly is arranged in the second trench and a gate poly is arranged in the first trench and separated from the source poly by means of an inter poly oxide layer. The width of the second trench is larger than the width of the first trench and the depth of the second trench is larger than the depth of the first trench and the liner oxide layer is thicker than the gate oxide layer. Also, the ratio between the first trench width A and the second trench width B is in a range from 1:1.7 to 1:2.

Abstract: A semiconductor device is provided that includes a first n+ region, a first p+ region within the first n+ region, a second n+ region, a second p+ region, positioned between the first n+ region and the second n+ region. The first n+ region, the second n+ region and the second p+ region are positioned within a p? region. A first space charge region and a second space charge region are formed within the p? region. The first space region is positioned between the first n+ region and the second p+ region, and the second space region is positioned between the second p+ region and the second n+ region.

Abstract: The invention relates to an electrical power energy converter unit for converting Direct Current to Direct Current, DC-DC, with maximum power point tracking that measures converted power at the output and controller module.

Abstract: A locking system for a semiconductor device is provided, that includes a locking clip and a lead frame, having a first and a second lead frame surface. The clip has a first and a second locking clip surface and includes a first and a second locking means. The first locking means is structured to align with the second locking means, so that a movement of the locking clip relative to the lead frame is possible in only one direction, and the locking clip is placed on the lead frame, so that the first locking clip surface of the locking clip is in contact with the second lead frame surface. This configuration prevents clip swaying during assembly and maximizes the use of copper material for both clips and lead frame components while making the density of manufactured semiconductor devices higher. Additionally, a semiconductor device and a method for manufacturing is provided.

Abstract: The disclosure relates to an electrical contact structure, and corresponding method of manufacturing an electrical contact structure, for a discrete semiconductor device. The electrical contact includes a first metal layer configured and arranged to contact a strained active area of a semiconductor die, a second metal layer configured and arranged to contact the first metal layer, and a third metal layer configured and arranged to contact the second metal layer.

Abstract: A semiconductor device and method of manufacturing is provided, including a lead frame with a first and a second lead frame surface, a semiconductor die including a first and a second semiconductor die surface, a clip including a flat and a corrugated part, the corrugated part includes at least one peak and one valley, and a mold compound, the second lead frame surface is connected to the first die surface of the die, and the second die surface of the die is connected to the corrugated part, and the mold compound encapsulates the semiconductor die, and the valley of the corrugated part, so that the mold compound forms an outer surface of the device with the peak of the corrugated part, at least part of the flat part of the clip, and the first lead frame surface of the lead frame is exposed.

Abstract: This disclosure relates to a lead frame assembly for a semiconductor device, a semiconductor device and an associated method of manufacture. The lead frame assembly includes a die attach structure and a clip frame structure. The clip frame structure includes a die connection portion configured to contact a contact terminal on a top side of the semiconductor die; and a continuous lead portion extending along the die connection portion. The continuous lead portion is integrally formed with the die connection portion.

Abstract: A semiconductor power device and a method for manufacturing the same is provided. The semiconductor power device includes a semiconductor body including a conductive substrate and an epitaxial layer of a first charge type grown on the conductive substrate, and one or more inner wells of a second charge type different from the first charge type in an active area of the semiconductor power device. At least some of the one or more inner wells of the second charge type are formed using at least two ion implantation steps. One step is dedicated to forming the inner wells of the second type whereas one or more further ion implantation steps are simultaneously used for forming a respective JTE structure and for increasing a dopant concentration of at least one well of the second charge type.

Abstract: A semiconductor device is provided, including: a lead frame, a semiconductor chip, a mold, and an adhesion promoter. The lead frame includes a first surface and a second frame surface opposite the first surface, and the chip includes a first and a second surface opposite the first surface, the first frame surface is an outer surface of the device, with the second frame surface attached to the first chip surface so that the second frame surface is partially covered by the first chip surface. An uncovered surface part of the second frame surface and the second chip side are in contact with the mold by the adhesion promoter, that is on the uncovered surface part of the second frame surface and/or on the second chip surface. The adhesion promoter enhances adhesion between the mold, and either the second frame surface or the second chip surface of the chip.

Abstract: A method of manufacturing a semiconductor package is provided, with an integrated heatsink and electrical connection feature. The semiconductor die can be attached to the terminal using eutectic bonding, preferably CuSn eutectic, Ag containing adhesives or Ag sintering material. These bondings are lead (Pb) free connection methods, which make the finished semiconductor package RoHS compliant (restriction of hazardous materials).