Abstract: A plurality of low-pass filters (2-1, 2-2, 2-3) are cascaded to the post-stage of an OTA (1) and a plurality of high-pass notch filters (3-1, 3-2, 3-3) are cascaded further to the post-stage thereof so that a high-pass filter having a high Q is not connected to the output of the OTA (1) having a high output impedance and a capacitor having a low capacitance is not connected with the output of the OTA (1) thus preventing multifeedback and avoiding such problems as the zero point of the notch filter (BEF) deviates from a design value or oscillation takes place.

Abstract: A differential amplifier circuit at the input stage is configured with a twin differential type having a first differential amplifier circuit (11) and a second differential amplifier circuit (12), respective outputs of which are received by a first and a second source-grounded amplifier (M5, M10). The second source-grounded amplifier (M10) is connected to a current mirror circuit (M11, M12), which is driven by the drain current of the second source-grounded amplifier (M10). With this configuration, the dynamic range for the upper half portion of an alternating signal output from an output terminal (OUT) is determined by the current supply capability of the first source-grounded amplifier (M5) and the dynamic range for the lower half portion is determined by the current supply capability of the second source-grounded amplifier (M10). This eliminates the need of a constant current circuit of a large current for generating a signal having lower half portion in which the waveform distortion is improved.

Abstract: By A/D converting a signal output from a mixer (4) and inputting the A/D converted signal to a DSP (8), and generating AGC control data (DL) corresponding to a level of the signal to control a gain of an LNA (3) in such a manner that a voltage input to an A/D converting circuit (7) is lower than a full scale voltage of the A/D converting circuit (7), it is possible to prevent a signal having an excessively high level beyond a dynamic range of the A/D converting circuit (7) from being input to the A/D converting circuit (7). By controlling the gain of the LNA (3) corresponding to a level of a broad band signal before passing through a BPF (11) and controlling a gain of an IF amplifier (12) corresponding to a level of a narrow band signal after passing through the BPF (11), moreover, it is possible to properly control a gain of an AGC as a whole in consideration of signal levels of both a desirable wave and a disturbing wave.

Abstract: An FM transmitter improved in degree of freedom of selecting components.

Abstract: An operational amplifier comprises: a differential amplifier circuit (11) that performs a differential amplification operation based on the difference of signals received at two input terminals (IN1, IN2); and a source-grounded amplifier (M5) connected to an output of the differential amplifier circuit (11). In the operational amplifier, there are provided a bias resistor (Rb) connected to the gate of the source-grounded amplifier (M5) and a bias circuit (M20) connected to the bias resistor (Rb). The gate bias of the source-grounded amplifier (M5) is supplied from the bias circuit (M20) through the bias resistor (Rb) so that the input resistance of the source-grounded amplifier (M5) is determined by the bias resistor (Rb) and the input resistance of the source-grounded amplifier (M5) can be reduced.

Abstract: An idling current setting circuit (3) includes: current setting transistors (Q3, Q4) connected to output transistors (Q1, Q2) in a driver (2) in current mirror form; a plurality of current setting resistors (R1 to R4); and a plurality of switches (ASW1 to ASW4) for switching to any of the current setting resistors (R1 to R4). This enables the idling current to be set by the current mirror ratio between the current setting transistors (Q3, Q4) having no connection with the open gain of the power amplifier and the output transistors (Q1, Q2), so that the idling current can be arbitrarily set independently of the open gain.

Abstract: A clock generating circuit having a simple constitution and an audio system are disclosed. The clock generating circuit (300) comprises an oscillator (12) for generating a reference frequency signal by means of a crystal oscillator (10) of a resonance frequency of 32.

Abstract: There are included a signal generating circuit (8) that generates, based on a comparison signal outputted from a phase comparator (3) and a clock signal outputted from a crystal oscillation circuit (1) and having a shorter pulse width than the comparison signal, a control signal obtained from a logical product of the two signals; and a charge pump circuit that performs, based on the control signal from the signal generating circuit (8), a charging or discharging operation of a capacitor. The charging or discharging operation of the capacitor is gradually performed little by little based on the control signal having the shorter pulse width than the conversional comparison signal, whereby even if the capacitance value of the capacitor is reduced, the substantial time constant can be enlarged, resulting in a stable operation of a frequency synthesizer.

Abstract: There are provided an A/D converting circuit (10) for converting, into a digital signal, a broadband intermediate frequency signal which is output from a frequency converting circuit (5), and a DSP (11) for generating and outputting control data to control gains of an antenna damping circuit (3) and an LNA (4) based on a level of the broadband digital intermediate frequency signal which is output from the A/D converting circuit (10), and the broadband intermediate frequency signal which is output from the frequency converting circuit (5) is A/D converted and supplied to the DSP (11). Consequently, it is possible to reduce a frequency of a signal input to the A/D converting circuit (10). Thus, it is also possible to reduce a consumed current without requiring the use a special AD converter corresponding to a radio frequency input.

Abstract: A frequency synthesizer includes an AND circuit (17) for detecting whether a frequency synthesizer is in a lock state according to a signal outputted from an Up terminal and a Down terminal of a phase comparator and switching circuits (18, 19) for switching between presence and absence of connections of constant current circuits (14, 15) constituting a charge pump circuit (4) according to the output signal of the AND circuit (17). When the AND circuit (17) has detected a high impedance state of the charge pump circuit (4), the switching circuits (18, 19) disconnects the constant current circuits (14, 15) by the switching circuits (18, 19). Thus, it is possible to eliminate current flowing into the charge pump circuit (4) without using a control signal from outside such as a power cut signal and an intermittent signal.

Abstract: A received signal level is detected in each of a wide band, middle band, and narrow band and each detected signal is converted to a digital signal. A DSP 18 determines the enabled/disabled state of an LNA 3 and an attenuator 4 as well as a gain adjustment amount based on the signal level of each band. For example, the gain adjustment is not performed when the signal level of the narrow band including a desired frequency is not larger than a prescribed value even the signal level of the wide band or middle band is larger than a prescribed value. When the signal level of the narrow band is larger than the prescribed value exceeding a gain adjustable limit level in the attenuator 4, the gain of the LNA 3 is adjusted, while maintaining the gain adjustable amount in the attenuator 4 around the limit level, to reduce the gain as a whole.

Abstract: A couple of frequency doubler circuits 21 and 22 which multiplys a frequency of a reference oscillation signal outputted from a reference oscillator 12 is provided, thereby a frequency of a reference oscillation signal, as the greatest common divisor between a frequency (300 KHz) determined by multiplying the frequency (fx=75 KHz) of a crystal oscillator 11 by four and a frequency (54 KHz) determined by multiplying an assigned frequency per one channel in AM radio broadcasting by a prescribed divide ratio, can be higher than a conventional frequency. This way realizes the decrease of a divide ratio in a programmable counter 17, resulting in the reduction of the circuit scale, shortening of the lock-up time, and improvement of the S/N ratio.

Abstract: An oscillator, a PLL circuit, a receiver and a transmitter that allow the circuit scale to be reduced and that are suitable for integration. The electrostatic capacities of variable capacitance circuits 230, 230A are made variable, thereby varying the oscillation frequency of a voltage controlled oscillator 21. The variable capacitance circuit 230 comprises a plurality of variable capacitance elements 60-64 the electrostatic capacities of which can be continuously varied by use of a control signal; a plurality of capacitors 50-54 which are associated with the respective variable capacitance elements and the electrostatic capacities of which are fixed; and a plurality of switches 71-74, 81-84 that individually switch combinational circuits, each of which comprises one of the plurality of variable capacitance elements 60-64 and a respective associated one of the plurality of capacitors 50-54, for selective connections.

Abstract: A second operational amplifier (7) is arranged, as an interface circuit (6), between a first operational amplifier (5) outputting the control voltage (Vcd) of a dummy filter (2) and a main filter (1), and the reference voltage (Vr) of the second operational amplifier (7) is optimized such that the control voltage (Vcd) obtained by using the dummy filter (2) is converted through the interface circuit (6) into a control voltage (Vcm) most suitable for the main filter (1), thereby obtaining a control voltage (Vcm) most suitable for regulating the frequency characteristics of the main filter (1) to desired characteristics.

Abstract: There are provided a notch filter 21 for carrying out a filtering processing for inputting a broadband IF signal which is output from a frequency converting circuit 4 and attenuating a frequency component of a desirable wave and an amplifier 22 for amplifying and outputting a signal output from the notch filter 21, and a presence/absence of an intermodulation disturbance is detected depending on whether a signal having an equal frequency to the frequency of the desirable wave is output from the amplifier 22 or not though the frequency of the desirable wave is attenuated by the notch filter 21. Consequently, it is possible to easily detect the intermodulation disturbance irrespective of a level of a received signal or a desirable wave included therein without carrying out a complicated processing such as an amplitude modulation of the received signal.

Abstract: There are provided a frequency converting circuit 21 for inputting a broadband IF signal which includes a disturbing wave and carrying out a frequency conversion with an oscillating signal having a frequency of a desirable wave, and outputting a signal including a sum frequency component of a frequency component of a disturbing wave which is included in the IF signal and a frequency component of a desirable wave of the oscillating signal and a difference frequency component therebetween, and a low-pass filter 22 for attenuating the sum frequency component to output a signal of the difference frequency component, and a presence of an intermodulation disturbance is detected based on a frequency relationship between two difference frequency components output from the low-pass filter 22.

Abstract: A first MOS transistor (M1) and a second MOS transistor (M2) constitute a cascode amplifier. The second MOS transistor (M2) is in a differential connection with a gain control MOS transistor (M4), which has its gate supplied with an AGC control voltage (VAGC), and it is arranged that the device area ratio of the second MOS transistor (M2) to the gain control MOS transistor (M4) is one to N (where N?1). In this way, even in a region where the AGC control voltage (VAGC) is small, abrupt variations of the gain can be suppressed, while the drain current of the first MOS transistor (M1) can be kept constant independently of the gain control.

Abstract: There are included a first quadrature modulation part (5) that divides an input signal into an I signal and a Q signal having a phase orthogonal to the phase thereof and uses a baseband frequency to perform frequency conversions of the I and Q signals, thereby performing a quadrature modulation; and a second quadrature modulation part (8) that uses in-phase and quadrature carriers of FM frequencies, which are 90 degrees out of phase with respect to each other, to perform frequency conversions of the I and Q signals, which are generated by the first quadrature modulation part (5), thereby performing a quadrature modulation.

Abstract: A modulation output device including; a DSP 12 for subjecting MP3 music data and the like read out from an MP3 player 50 to stereo modulation, when necessary; D/A converter 14 for converting the digital data outputted from the DSP 12 to an analog signal and outputting the converted analog signal to either an earphone terminal 54 or transmission part 15; and transmission part 15 for transmitting the analog signal outputted from the D/A converter 14 to the outside through a transmission antenna 55 enables the processing concerning reproduction of music data and processing for modulation of the reproduced music data to transmit without wires to be performed by a single DSP 12 and a single D/A converter 14.

Abstract: A first switch (SW1) is connected in series between a first capacitor (1) and a grounding wire, and when an RTC oscillation apparatus is connected and an IC chip (10) is configured as an external input buffer circuit, the first switch (SW1) is turned off. Thus, the first capacitor (1) and a second capacitor (2) are prevented from being connected in parallel to a resonance capacitor of the RTC oscillation apparatus, and the first and the second capacitors (1, 2) are prevented from configuring a part of the resonance circuit of the oscillation apparatus. When an exclusive crystal oscillator is connected and the IC chip (10) is configured as a part of the oscillation apparatus, the first switch (SW1) is turned on and the first and the second capacitors (1, 2) configure a part of the resonance circuit.