Patents Assigned to Niigata Seimitsu Co., Ltd.
  • Patent number: 6922126
    Abstract: An inductor element 10 effectively functions even when formed on a substrate and comprises two upper and lower conductors 1, 2 spirally formed on the front side of a semiconductor substrate 3. The conductors 1, 2 have substantially the same shape. When viewed from the above of the front side of the substrate 3, the two conductors 1, 2 are superposed one on the other almost exactly. Lead wires 6a, 6b are connected to the outer end (outer peripheral end) and the inner end (center end) of the conductor 1, respectively. The outer end of the conductor 1 is connected to the inner end of the conductor 2 through a connection wire 6c. The conductor 1 functions as an inductor conductor and is connected to a circuit provided on the semiconductor substrate 3 through the lead wires 6a, 6b.
    Type: Grant
    Filed: May 18, 1999
    Date of Patent: July 26, 2005
    Assignee: Niigata Seimitsu Co., Ltd.
    Inventors: Akira Okamoto, Takeshi Ikeda
  • Patent number: 6919710
    Abstract: A smoothing circuit for realizing the miniaturization and the increase of integration scale of a circuit and for easily varying attack time and release time. This smoothing circuit comprises a capacitor, voltage comparator, charging circuit, and discharging circuit. The voltage comparator compares the terminal voltage of the capacitor with its input voltage and actuates the charging circuit or the discharging circuit according to a comparison result. The charging circuit charges the capacitor by intermittently supplying charging current. The discharging circuit discharges the capacitor by allowing discharging current to flow intermittently.
    Type: Grant
    Filed: December 20, 2001
    Date of Patent: July 19, 2005
    Assignee: Niigata Seimitsu Co., Ltd.
    Inventor: Hiroshi Miyagi
  • Patent number: 6920321
    Abstract: The object is to provide a measurement system of communication device that makes it possible to reduce costs and spaces for measurement. A CPU 13 gives a signal generator 4 an instruction to output a signal for measurement. A signal generator 4 outputs the signal for measurement into which a predetermined audio signal is modulated, in accordance with the instruction. A reception processing section 11 performs predetermined reception processing including demodulation processing for the signal for measurement, and outputs the demodulated signal. A low frequency analyzer 6 measures characteristics of the demodulated signal outputted from the reception processing section 11, and outputs the result of measurement to the CPU 13. The CPU 13 displays the result of measurement on an LCD 12, and adjusts the characteristics of the reception processing section 11.
    Type: Grant
    Filed: August 31, 1999
    Date of Patent: July 19, 2005
    Assignee: Niigata Seimitsu Co., Ltd.
    Inventor: Hiroshi Miyagi
  • Patent number: 6909655
    Abstract: A plurality of decoding circuits 1a to 1f are arranged near a plurality of circuit blocks 2 to 7, which are arranged on the semiconductor chip 10 in a scattered manner, and the signal lines 8 prior to decoding, including the address lines and the data lines, are wired to each decoding circuit 1a to 1f. Through these wirings, the number of wirings routed over on the semiconductor chip 10 can be made in accordance with the number of bits of the signal lines 8 alone. So, compared with the past where the signal lines 20, which were great in number after decoding, were routed over to each circuit block 2 to 7, the wiring area as a whole can be greatly reduced. This can lead to miniaturization of chip size, reduction of crosstalk noise, and facilitation of layout.
    Type: Grant
    Filed: December 19, 2003
    Date of Patent: June 21, 2005
    Assignee: Niigata Seimitsu Co., Ltd.
    Inventor: Munehiro Karasudani
  • Publication number: 20050130696
    Abstract: A keyboard section 9, whose operation keys are allocated linearly in a longitudinal direction on the cylinder chassis 1, is established except for at the location of the grip section 1a, which is held by the user when the cylinder chassis 1 is used as a writing tool. Due to this, the area of the operation keys of the keyboard section 9 can be large. And for the operation keys to be allocated linearly can preserve a great deal of space for the display section 3.
    Type: Application
    Filed: August 16, 2004
    Publication date: June 16, 2005
    Applicant: NIIGATA SEIMITSU CO., LTD.
    Inventors: Takeshi Ikeda, Akira Okamoto
  • Patent number: 6906589
    Abstract: A plurality of transistors Qi (i=1 to n), which are connected to a plurality of differential amplifiers 1, 2, and 3 and which are connected in a multistaged manner and connected to one constant current source 4 by a current mirror, are arranged collectively on an input side of the constant current source 4. Due to this, the wiring length between the constant current source 4 and the transistors Qi is shortened to the utmost, and the stability of circuit can be improved. Also, this can restrict the unfavorableness that noise is superposed on the wiring. Additionally, a voltage drop will not occur due to supplied resistance on the ground line, due to each transistor Qi being grounded to the same place via separate ground lines 6, 7, and 8. Because of this, the current can be supplied from the constant current source 4 to all transistors Qi without breaking the balance of the current mirror.
    Type: Grant
    Filed: October 9, 2003
    Date of Patent: June 14, 2005
    Assignee: Niigata Seimitsu Co., Ltd.
    Inventors: Takeshi Ikeda, Hiroshi Miyagi
  • Patent number: 6906610
    Abstract: An inductor element 100 capable of functioning properly on a substrate includes two similarly shaped conductors such as spiral conductors 120, 122 formed on the surface of a semiconductor substrate 110. The upper conductor 120 and the lower conductor 122 have substantially the same shape, and the inner end of the conductor 120 is connected electrically with the outer end of the conductor 122. The outer and inner ends of the conductor 120 are connected with lead wires 130, 132, respectively, and the lead wire 132 connected to the inner end is led between the lower conductor 122 and the semiconductor substrate 110 to the periphery of the substrate.
    Type: Grant
    Filed: July 6, 2000
    Date of Patent: June 14, 2005
    Assignee: Niigata Seimitsu Co., Ltd.
    Inventors: Akira Okamoto, Takeshi Ikeda
  • Patent number: 6894966
    Abstract: An interpolation circuit capable of performing interpolation operation with a simple constitution. A 16-times oversampling from discrete data is performed by D frip-frops 4, 5. A first convolution operation is performed by D frip-frops 4 through 11 and an adder 12, on the result of which a second convolution operation is performed by D frip-frops 13 through 20 and an adder 21. Data interpolated along a quadratic function curve interpolating the discrete data is obtained from the adder 21.
    Type: Grant
    Filed: May 11, 2000
    Date of Patent: May 17, 2005
    Assignee: Niigata Seimitsu Co., Ltd.
    Inventor: Yukio Koyanagi
  • Publication number: 20050088349
    Abstract: A keyboard section 9, whose operation keys are allocated linearly in a longitudinal direction on the cylinder chassis 1, is established except for at the location of the grip section 1a, which is held by the user when the cylinder chassis 1 is used as a writing tool. Due to this, the area of the operation keys of the keyboard section 9 can be large. And for the operation keys to be allocated linearly can preserve a great deal of space for the display section 3.
    Type: Application
    Filed: January 10, 2005
    Publication date: April 28, 2005
    Applicant: NIIGATA SEIMITSU CO., LTD.
    Inventors: Takeshi Ikeda, Akira Okamoto
  • Publication number: 20050058296
    Abstract: A radio receiver includes a noise canceller (2) for removing a pulse noise from a composite signal from an FM detection circuit (1), a stereo demodulation circuit (3) for demodulating the output signal of the noise canceller (2) to reproduce a stereo signal, and a VCO (21) for outputting a clock signal as an origin of a clock signal used in the stereo demodulation circuit (3). A clock signal used in a CCD (15) of the noise canceller (2) is generated based on a clock signal output from the VCO (21), so as to synchronize the phase of the signal used in the CCD (15) with the phase of the clock signal used in the stereo demodulation circuit (3), thereby suppressing generation of a beat signal in the output of the stereo demodulation circuit (3).
    Type: Application
    Filed: October 21, 2004
    Publication date: March 17, 2005
    Applicant: Niigata Seimitsu Co., Ltd.
    Inventor: Munehiro Karasudani
  • Patent number: 6861910
    Abstract: An initial-stage amplifier 1 that deals with microsignals and other amplifiers 2 and 3 separate a power source line, and both separated power source lines 4 and 8 are commonly connected to a power source pad 6. This enables avoidance of the occurrence of a large potential difference between the initial-stage amplifier 1 and other amplifiers 2 and 3 due to differences in currents pulled to the amplifiers 1 to 3, and can prevent the occurrence of noise arising from such potential difference. Also, feedback loops are differentiated by the initial-stage amplifier 1 and other amplifiers 2 and 3. This can also prevent unfavorable effects where a large signal would be fed back from the rear-stage amplifiers 2 and 3 to the initial-stage amplifier 1.
    Type: Grant
    Filed: January 20, 2004
    Date of Patent: March 1, 2005
    Assignee: Niigata Seimitsu Co., LTD
    Inventor: Munehiro Karasudani
  • Patent number: 6858946
    Abstract: A semiconductor device for forming a coil with a high inductance and a high Q value on a semiconductor substrate. A semiconductor device 10 comprises a rectangular semiconductor substrate 12, pads formed near four corners of this semiconductor substrate 12, pads 30 formed in the peripheral region along each side other than the corners, and a bonding wire 40 for connecting adjacent pads 20. The circulation of the bonding wire 40 along the periphery of the semiconductor substrate 12 with the pads 20 formed in the corners constitutes a coil.
    Type: Grant
    Filed: June 26, 2002
    Date of Patent: February 22, 2005
    Assignee: Niigata Seimitsu Co., Ltd.
    Inventors: Hiroshi Miyagi, Akira Okamoto
  • Publication number: 20050035182
    Abstract: By photographing pad forming faces of CSPs 400 to recognize a pad arrangement through image processing so as to transfer and position the CSPs 400 in accordance with the recognition result of the pad arrangement, even if pads 401 are formed in any arrangement state in the CSPs 400 to be transferred, the positional relation between the pads 401 included in the CSPs 400 is made to always accurately coincide with the positional region between a plurality of solder ball attracting nozzles of a solder ball mounting apparatus.
    Type: Application
    Filed: August 10, 2004
    Publication date: February 17, 2005
    Applicant: NIIGATA SEIMITSU CO., LTD.
    Inventors: Akihiro Mano, Yukihiro Ueno, Hironori Urasawa, Akihiro Tanaka
  • Publication number: 20050035184
    Abstract: A semiconductor part 1 in which a metal terminal 2 is formed on its back surface and side surface is mounted so that only the back surface portion of the metal terminal 2 is in contact with a cream solder 3. When the side surface portion of the metal terminal 2 is irradiated with laser beams, the back surface portion of the metal terminal 2 is heated by thermal conduction from the side surface portion to the back surface portion of the metal terminal 2 and the cream solder 3 in contact with the back surface portion of the metal terminal 2 is melted, whereby soldering is performed.
    Type: Application
    Filed: August 10, 2004
    Publication date: February 17, 2005
    Applicant: NIIGATA SEIMITSU CO., LTD.
    Inventors: Akihiro Mano, Yukihiro Ueno, Hironori Urasawa, Yuki Oishi, Tadashi Miyazaki
  • Publication number: 20050021949
    Abstract: An encryption apparatus 1 for performing an encrypting process and an encrypted data decrypting process is mounted to terminate the security by encryption between personal computers 7 to 9 on which encryption software is installed. For example, by connecting the apparatus between terminals 2 to 4 and the personal computers 7 to 9, the encryption can be used in an in-house LAN having the terminals 2 to 4 on which encryption software cannot be installed. Thus, a secure network 10 almost free of the risk of tapping of the confidential information in the LAN by an external unauthorized entry or attach can be successfully designed.
    Type: Application
    Filed: August 16, 2004
    Publication date: January 27, 2005
    Applicants: NIIGATA SEIMITSU CO., LTD., MICRO RESEARCH LABORATORY, INC.
    Inventors: Makoto Izawa, Hiromitsu Narita, Akira Okamoto
  • Publication number: 20050017798
    Abstract: A transformer 11, which converts input current into voltage output, is arranged between a power switch 1, which amplifies and outputs audio signals based on the power source voltage VDD supplied to MOS transistors Q1 to Q4, and a speaker 3. Through appropriately determining the turns ratio (Ns/Np), without causing the power source voltage VDD of the power switch 1 to be large, large voltage Vs is made to occur at both ends of the speaker 3 from such small power source voltage VDD. Through this, large output power can be obtained.
    Type: Application
    Filed: September 15, 2004
    Publication date: January 27, 2005
    Applicant: NIIGATA SEIMITSU CO., LTD.
    Inventor: Mamoru Kitamura
  • Publication number: 20050020302
    Abstract: A plurality of plane antennas 6-1 and 6-2 are embedded in the equipment body section 1, and every time occurrence of reception failure is detected by the internal electronics circuit, switching between the antennas used is established. Spatial diversity through selectively switching and using the plurality of plane antennas 6-1 and 6-2 is performed. Through this, even when reception sensitivity of one antenna in use deteriorates, good reception sensitivity can be gained through switching to another antenna. Thus, this can avoid inconvenience where calls are cut off.
    Type: Application
    Filed: July 19, 2004
    Publication date: January 27, 2005
    Applicant: NIIGATA SEIMITSU CO., LTD.
    Inventors: Takeshi Ikeda, Akira Okamoto
  • Patent number: 6844780
    Abstract: An automatic gain control circuit integrally fabricated on a semiconductor substrate. An AGC circuit 17 controls the gain of an intermediate-frequency amplifier circuit 15 so that the average level of the output signal (sound signal) of an AM detector 16 may be substantially constant. The AGC circuit 17 includes a time-constant circuit 100, which comprises a charging circuit for intermittently charging the capacitor and a discharging circuit for intermittently discharging the same. By this intermittent charging and discharging of the capacitor having a small capacitance, a large time constant is set.
    Type: Grant
    Filed: November 12, 2002
    Date of Patent: January 18, 2005
    Assignee: Niigata Seimitsu Co., Ltd.
    Inventor: Hiroshi Miyagi
  • Patent number: 6844777
    Abstract: A transformer 11, which converts input current into voltage output, is arranged between a power switch 1, which amplifies and outputs audio signals based on the power source voltage VDD supplied to MOS transistors Q1 to Q4, and a speaker 3. Through appropriately determining the turns ratio (Ns/Np), without causing the power source voltage VDD of the power switch 1 to be large, large voltage Vs is made to occur at both ends of the speaker 3 from such small power source voltage VDD. Through this, large output power can be obtained.
    Type: Grant
    Filed: December 2, 2003
    Date of Patent: January 18, 2005
    Assignee: Niigata Seimitsu Co., Ltd.
    Inventor: Mamoru Kitamura
  • Publication number: 20050008160
    Abstract: An encryption apparatus 1 includes encryption/decryption means for performing an encrypting/decrypting process on data to terminate encryption-based security between the encryption apparatus and a terminal having an encrypting capability. Further, a manager terminal 12 can be used in inputting various information for controlling encrypted-data communications into each of the encryption apparatus 1 and terminals 7-9 remotely from the manager terminal, so that settings for the encrypted data communications on each of the apparatus and the terminals are completed. Furthermore, the encryption system is formed by connecting the encryption apparatus 1, the manager terminal 12 and the terminals 2-9 which are capable of encrypted data communications. This configuration makes it possible for an in-house LAN including terminals where installation of a dedicated encryption program is impossible to utilize the encryption.
    Type: Application
    Filed: August 16, 2004
    Publication date: January 13, 2005
    Applicants: NIIGATA SEIMITSU CO., LTD., MICRO RESEARCH LABORATORY, INC.
    Inventors: Makoto Izawa, Hiromitsu Narita, Akira Okamoto