Patents Assigned to Niigata Seimitsu Co., Ltd.
  • Patent number: 7102426
    Abstract: A digital ?? modulated signal produced by a quantizer (1c) in a ?? modulation processing unit (1) is put in to a feedback loop before inputted to a power switch (2) and converted into an analog signal by a D/A converter (1d). This analog signal is fed back to the input stage (a differentiator (1a)) of the ?? processing unit (1) to prevent the switching distortion of the power switch (2) itself from being introduced into the feedback loop thereby to suppress the influence of the switching distortion.
    Type: Grant
    Filed: December 22, 2003
    Date of Patent: September 5, 2006
    Assignee: Niigata Seimitsu Co., Ltd.
    Inventor: Mamoru Kitamura
  • Publication number: 20060192707
    Abstract: An integrated circuit includes CMOS circuit blocks and analog control lines arranged outside a layout of the CMOS circuit blocks so that the analog wiring and circuit blocks do not overlap each other. The distance of signal lines within a circuit block and the analog control lines can become as long as necessary, and the signal line within the circuit block and the analog control lines are not coupled via parasitic capacitance, and mutual interference is suppressed. In another aspect, a method of arranging a semiconductor integrated circuit includes providing a plurality of functional circuit blocks and connecting analog control wiring to the functional circuit blocks. The analog control wiring is arranged outside a layout of the functional circuit blocks on the semiconductor integrated circuit so that the analog control wiring does not overlap any one of the functional circuit blocks so as to reduce or eliminate interference between signal lines within a circuit block and the analog control lines.
    Type: Application
    Filed: April 27, 2006
    Publication date: August 31, 2006
    Applicant: Niigata Seimitsu Co., Ltd.
    Inventor: Munehiro KARASUDANI
  • Patent number: 7084439
    Abstract: In order for circuit blocks 1 to 3 composed by the CMOS process, and analog lines 5-1, 5-2, and 5-3 connected thereto not to overlap on the layout, the analog lines 5-1 and 5-2 are wired so that such lines roundabout the layout of the AM/FM common circuit block 3. Through this, the distance of the signal line within the AM/FM common circuit block 3 and the analog lines 5-1 and 5-2 can become as long as possible, the signal line within the AM/FM common circuit block 3 and the analog lines 5-1 and 5-2 would not be coupled via parasitic capacity, and mutual interference occurring between the signal line and the analog lines 5-1 and 5-2 can be suppressed.
    Type: Grant
    Filed: December 20, 2003
    Date of Patent: August 1, 2006
    Assignee: Niigata Seimitsu Co., Ltd.
    Inventor: Munehiro Karasudani
  • Patent number: 7076272
    Abstract: A keyboard section 9, whose operation keys are allocated linearly in a longitudinal direction on the cylinder chassis 1, is established except for at the location of the grip section 1a, which is held by the user when the cylinder chassis 1 is used as a writing tool. Due to this, the area of the operation keys of the keyboard section 9 can be large. And for the operation keys to be allocated linearly can preserve a great deal of space for the display section 3.
    Type: Grant
    Filed: January 10, 2005
    Date of Patent: July 11, 2006
    Assignee: Niigata Seimitsu Co., Ltd.
    Inventors: Takeshi Ikeda, Akira Okamoto
  • Patent number: 7055072
    Abstract: It is object to provide a memory system for reliably detecting an error, if any, in management information that is read out. The same content of telephone number data is stored in memories 8, 9, 10. When telephone number data is read out of the memories 8, 9, 10, a comparing section 20 judges if all the contents of the telephone number data are the same. If not, a parity error detecting section 22 performs parity check of the telephone number data and excludes the content from which a parity error is detected as an object not to be processed thereafter. After the parity check, an object-to-be-processed determining section 24 determines whether or not there is any telephone number data in the majority on the basis of the criterion that the sum of the pieces of the telephone number data that is read out. If there is not such telephone number data, it judges that there is an error.
    Type: Grant
    Filed: November 16, 2001
    Date of Patent: May 30, 2006
    Assignee: Niigata Seimitsu Co., Ltd.
    Inventor: Hiroshi Miyagi
  • Patent number: 7049895
    Abstract: An FET band amplifier for providing a high gain. An FET band amplifier 5 included in an AM receiver comprises amplifiers 11 to 15 e.g. at five stages and a BPF 16 inserted halfway in their connection. Each of the amplifiers 11 to 15 acts as a differential amplifier comprising a p-channel FET as an amplification element. The BPF 16 allows the passage of a component of a band wider than the amplification band of the whole of the FET band amplifier and reduces a 1/f noise by removing the low-band component of a signal amplified by the amplifiers 11 to 13 at three stages and thermal noise by removing the high-band component. Thus, each of the amplifiers 14, 15 connected to the rear stage of the BPF 16 is not saturated by a noise component.
    Type: Grant
    Filed: June 28, 2005
    Date of Patent: May 23, 2006
    Assignee: Niigata Seimitsu Co., Ltd.
    Inventor: Hiroshi Miyagi
  • Patent number: 7046113
    Abstract: An inductor element having good characteristics is formed on a substrate. An inductor element 100 includes two spiral conductors 120, 122 formed on the surface of a semiconductor substrate 110. The upper conductor 120 and the lower conductor 122 have substantially the same shape, and the conductor 120 is used as an inductor conductor, while the conductor 122 is used as a floating conductor. The outer and inner ends of the conductor 120 are connected with lead wires 130, 132, respectively, and the lead wire 132 connected with the inner ene extends outside between the lower conductor 122 and the semiconductor substrate 110.
    Type: Grant
    Filed: August 10, 2000
    Date of Patent: May 16, 2006
    Assignee: Niigata Seimitsu Co., Ltd.
    Inventors: Akira Okamoto, Takeshi Ikeda
  • Patent number: 7046086
    Abstract: An FET band amplifier for reducing a residual noise during gain control. An FET band amplifier 5 included in an AM receiver comprises amplifiers 11 to 15 e.g. at five stages, a BPF 16 inserted halfway in their connection, and an AGC circuit 8. The BPF 16 allows the passage of a component of a band wider than the amplification band of the whole of the FET band amplifier and reduces a 1/f noise by removing a low-band component of a signal output from the amplifier 13 at the third stage and thermal noise by removing the high-band component. This process enables a reduction in a residual noise during gain control included in a signal output from the amplifier 15 at the final stage.
    Type: Grant
    Filed: June 28, 2005
    Date of Patent: May 16, 2006
    Assignee: Niigata Seimitsu Co., Ltd.
    Inventor: Hiroshi Miyagi
  • Patent number: 7038548
    Abstract: An amplifier circuit for AM broadcasting for amplifying an inputted AM broadcast signal by an FET and outputting it. The amplifier circuit comprises FETs for signal amplification which are P-channel MOSFETs (4, 5) of relatively small flicker noise. While suppressing the flicker noise to a lowest possible level, more circuits including the RF amplifier for AM broadcasting can be integrated on one chip, thereby realizing small size and low noise of the circuits.
    Type: Grant
    Filed: February 25, 2004
    Date of Patent: May 2, 2006
    Assignee: Niigata Seimitsu Co., Ltd.
    Inventors: Takeshi Ikeda, Hiroshi Miyagi
  • Patent number: 7034885
    Abstract: An image processing circuit capable of carrying out high-speed processing and improving the horizontal and vertical resolutions even with its simple structure. The pixel values a to i of a total of nine pixels, three pixels in the horizontal direction along a scanning line by three pixels in the vertical direction in which the line and adjacent lines are abreast, are extracted by a pixel value extracting section. The pixel values A1 to A4 of four pixels Q1 to Q4 generated additionally around the center pixel P5 are determined by calculation by a pixel value calculation section. These pixel values are outputted in units of one scanning line by correlating them with two scanning lines by a pixel value output section.
    Type: Grant
    Filed: April 20, 2000
    Date of Patent: April 25, 2006
    Assignee: Niigata Seimitsu Co., Ltd.
    Inventors: Yukio Koyanagi, Kazuo Toraichi
  • Publication number: 20060040627
    Abstract: The present invention prevents sound quality from degrading due to a change in electric field intensity or due to multi-path noise. An arithmetic unit subtracts a signal based on the detection signal of multi-path noise whose time constant is specified by a second time constant circuit from a signal based on an RSSI signal whose time constant is specified by a first time constant. An output signal from this arithmetic unit is applied, as a control signal, to a stereo-noise control circuit or the like. This can control the degradation of separation and the like in accordance with multi-path fading to prevent sound quality from degrading.
    Type: Application
    Filed: October 1, 2003
    Publication date: February 23, 2006
    Applicants: Kabushiki Kaisha Toyota Jidoshokki, Niigata Seimitsu Co., Ltd.
    Inventors: Tsuyoshi Koike, Hiroshi Miyagi
  • Patent number: 6989720
    Abstract: A receiver capable of reducing the number of pads of a semiconductor device used for connection with a tuning circuit. The receiver includes a semiconductor device 100 containing various circuits and a tuning circuit 130 connected as a separate part to this semiconductor device 100. The semiconductor device 100 has a pad 112 formed on a semiconductor substrate 110, a processing circuit 114 connected via a capacitor 120 to the pad 112, and a D/A converter 122 connected via a resistor 124 to the pad 112. A tuning voltage generated by the D/A converter 122 is applied via the pad 112 to the tuning circuit 130. Moreover, an output signal of the tuning circuit 130 is supplied to the pad 112 and fed via the capacitor 120 to the processing circuit 114.
    Type: Grant
    Filed: November 12, 2002
    Date of Patent: January 24, 2006
    Assignee: Niigata Seimitsu Co., Ltd.
    Inventor: Hiroshi Miyagi
  • Publication number: 20060008090
    Abstract: A current amount of a current that flows in the transistor (23) of a current mirror circuit that retrieves an L?R component signal from a stereo composite signal is adjusted based on a control signal that is generated by the control circuit (25).
    Type: Application
    Filed: June 27, 2003
    Publication date: January 12, 2006
    Applicants: Niigata Seimitsu Co., Ltd.
    Inventors: Tsuyoshi Koike, Hiroshi Miyagi
  • Patent number: 6976616
    Abstract: By photographing pad forming faces of CSPs 400 to recognize a pad arrangement through image processing so as to transfer and position the CSPs 400 in accordance with the recognition result of the pad arrangement, even if pads 401 are formed in any arrangement state in the CSPs 400 to be transferred, the positional relation between the pads 401 included in the CSPs 400 is made to always accurately coincide with the positional region between a plurality of solder ball attracting nozzles of a solder ball mounting apparatus.
    Type: Grant
    Filed: August 10, 2004
    Date of Patent: December 20, 2005
    Assignee: Niigata Seimitsu Co., Ltd.
    Inventors: Akihiro Mano, Yukihiro Ueno, Hironori Urasawa, Akihiro Tanaka
  • Publication number: 20050269240
    Abstract: A tray of parts for inspection has a simple structure having only a tray holder that has a plurality of groove sections that store a plurality of parts for inspection on the surface, and contact sections, comprised in each groove, which have the conductor to electrically connect the electrodes of the stored parts for inspection in each groove section extends to the back surface. Under conditions where the plurality of parts for inspection are stored in the tray of parts for inspection, such tray is held by the tray holder, and the plurality of probe needles are placed on the plurality of contact sections equipped by the tray of parts for inspection all at once. Through this, electrical examination of a plurality of parts for inspection can be simultaneously performed.
    Type: Application
    Filed: May 13, 2005
    Publication date: December 8, 2005
    Applicant: NIIGATA SEIMITSU CO., LTD.
    Inventors: Takeshi Ikeda, Hiroshi Miyagi
  • Publication number: 20050265126
    Abstract: A device is provided with: a counter 11 for measuring a period of time from turning on an electronic apparatus 1 to receiving via a network 3 a first network event that occurs after turning on the electronic apparatus 1; and a value determining section 12 for determining a value of an initial random number on the basis of the time information obtained by the counter 11. In this device, an initial random number for random numbers is generated utilizing the fact that the first network event is received in a “random” period of time after turning on the electronic apparatus 1. In addition, since existing electronic apparatuses are generally provided with various devices including the counter 11 and a CPU with the value determining section 12, an initial random number for random numbers can be generated utilizing an existing hardware configuration.
    Type: Application
    Filed: October 6, 2004
    Publication date: December 1, 2005
    Applicants: MICRO RESEARCH LABORATORY, INC., NIIGATA SEIMITSU CO., LTD.
    Inventors: Makoto Izawa, Hiromitsu Narita, Akira Okamoto
  • Patent number: 6969623
    Abstract: A semiconductor device and a method for manufacturing the semiconductor device mountable with high density, which includes a simplified process but is capable of reducing a defect rate. A plurality of identical memory chips are formed on a semiconductor wafer, and a go/no-go test is conducted on all the memory chips. The semiconductor wafer is cut and divided into pieces that each consists of one, or two, or four good memory chips, and they are mounted on a substrate to form a memory module.
    Type: Grant
    Filed: November 17, 2000
    Date of Patent: November 29, 2005
    Assignee: Niigata Seimitsu Co., Ltd.
    Inventors: Kouichi Ikeda, Takeshi Ikeda
  • Patent number: 6937092
    Abstract: A transformer 11, which converts input current into voltage output, is arranged between a power switch 1, which amplifies and outputs audio signals based on the power source voltage VDD supplied to MOS transistors Q1 to Q4, and a speaker 3. Through appropriately determining the turns ratio (Ns/Np), without causing the power source voltage VDD of the power switch 1 to be large, large voltage Vs is made to occur at both ends of the speaker 3 from such small power source voltage VDD. Through this, large output power can be obtained.
    Type: Grant
    Filed: September 15, 2004
    Date of Patent: August 30, 2005
    Assignee: Niigata Seimitsu Co., Ltd.
    Inventor: Mamoru Kitamura
  • Patent number: 6930552
    Abstract: An FET band amplifier for reducing a residual noise during gain control. An FET band amplifier 5 included in an AM receiver comprises amplifiers 11 to 15 e.g. at five stages, a BPF 16 inserted halfway in their connection, and an AGC circuit 8. The BPF 16 allows the passage of a component of a band wider than the amplification band of the whole of the FET band amplifier and reduces a 1/f noise by removing a low-band component of a signal output from the amplifier 13 at the third stage and thermal noise by removing the high-band component. This process enables a reduction in a residual noise during gain control included in a signal output from the amplifier 15 at the final stage.
    Type: Grant
    Filed: February 21, 2002
    Date of Patent: August 16, 2005
    Assignee: Niigata Seimitsu Co., Ltd.
    Inventor: Hiroshi Miyagi
  • Publication number: 20050176396
    Abstract: A receiver (11) converts a received signal directly to a baseband signal, and includes: a switched-capacitor filter (19) controlling a cutoff frequency when the baseband signal is filtered according to a control signal provided for a switched-capacitor element (27); an oscillator generating a periodic signal; and a divider (31) dividing a periodic signal generated by the oscillator according to the received signal, and an output signal from the divider (31) is provided as the control signal for the switched-capacitor element (27).
    Type: Application
    Filed: March 18, 2003
    Publication date: August 11, 2005
    Applicant: KABUSHIKI KAISHA TOYOTA JIDOSHOKKI NIIGATA SEIMITSU CO. LTD
    Inventor: Hiroshi Miyagi